Pub Date : 2023-10-24DOI: 10.1007/s10825-023-02100-1
Sugandha Yadav, Poornima Mittal, Shubham Negi
In this paper, a highly efficient charge generation layer (CGL)-based blue organic light-emitting diode is proposed. The proposed device contains a CGL composed of two materials, 1,1-bis[(di-4-tolyamino)phenyl]cyclohexane (TAPC) and 1,4,5,8,9,11-hexaazatriphenylene-hexacarbonitrile (HAT-CN), which act as hole and electron injectors, respectively. The CGL in the proposed device is placed outside the emissive layer, which provides better luminescence and current as compared with four other CGL-based devices D2, D3, D4 and D5 where CGL is utilized below the cathode, above the anode, near both electrodes (cathode and anode) and inside the emissive layer, respectively. The proposed device exhibits noteworthy results, achieving peak current and luminescence values of 0.44 A and 3636.3 cd/m2, respectively. The luminescence obtained is improved by about 16.8, 2.3, 1.7, 3, and 1.6 times compared with D1, D2, D3, D4 and D5. Thickness optimization of the proposed device is also outlined. The optimized device shows maximum luminescence of 4670 cd/m2.
{"title":"Characteristic performance and analysis of the positional variation of the charge generation layer to enhance the performance of OLEDs","authors":"Sugandha Yadav, Poornima Mittal, Shubham Negi","doi":"10.1007/s10825-023-02100-1","DOIUrl":"10.1007/s10825-023-02100-1","url":null,"abstract":"<div><p>In this paper, a highly efficient charge generation layer (CGL)-based blue organic light-emitting diode is proposed. The proposed device contains a CGL composed of two materials, 1,1-bis[(di-4-tolyamino)phenyl]cyclohexane (TAPC) and 1,4,5,8,9,11-hexaazatriphenylene-hexacarbonitrile (HAT-CN), which act as hole and electron injectors, respectively. The CGL in the proposed device is placed outside the emissive layer, which provides better luminescence and current as compared with four other CGL-based devices D<sub>2</sub>, D<sub>3</sub>, D<sub>4</sub> and D<sub>5</sub> where CGL is utilized below the cathode, above the anode, near both electrodes (cathode and anode) and inside the emissive layer, respectively. The proposed device exhibits noteworthy results, achieving peak current and luminescence values of 0.44 A and 3636.3 cd/m<sup>2</sup>, respectively. The luminescence obtained is improved by about 16.8, 2.3, 1.7, 3, and 1.6 times compared with D<sub>1</sub>, D<sub>2</sub>, D<sub>3</sub>, D<sub>4</sub> and D<sub>5</sub>. Thickness optimization of the proposed device is also outlined. The optimized device shows maximum luminescence of 4670 cd/m<sup>2</sup>.</p></div>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":null,"pages":null},"PeriodicalIF":2.1,"publicationDate":"2023-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71910243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this investigation, we develop CdS-free non-toxic thin-film solar cell structure with antimony sulfide (Sb2S3) as an absorber material. Sb2S3 has found to be a promising candidate for production of renewable energy. Solar cells based on Sb2S3 have been attracted worldwide attraction due to their outstanding efficiency and low cost. To serve as an optimistic buffer layer, 3C-SiC (cubic silicon carbide) is used thanks to its suitable bandgap to replace toxic cadmium sulfide (CdS). SCAPS-1D (one-dimensional solar cell capacitance simulator) software has been employed to numerically investigate the performance of Sb2S3-based n-ZnO/n-3C-SiC/p-Sb2S3 heterostructure solar cells. The influence of absorber/buffer layer thickness, acceptor/donor densities, and defect density on device working have been investigated. Consequently, the role of defects in p-Sb2S3 along with the significance of n-3C-SiC/p-Sb2S3 interface defects has been studied to provide recommendations for achieving high efficiency. The proposed structure provides the enhanced efficiency of 17% under 1.5 G illumination spectrum. The parameters regarding solar cell performance such as Voc, Jsc, FF, QE and η have been studied graphically. This novel structure may have considerable influence on progress of improved photovoltaic devices in future.
{"title":"Optimization of CdS-free non-toxic electron transport layer for Sb2S3-based solar cell with notable enhanced performance","authors":"Sameen Maqsood, Zohaib Ali, Khuram Ali, Rimsha Bashir Awan, Yusra Arooj, Ayesha Younus","doi":"10.1007/s10825-023-02106-9","DOIUrl":"10.1007/s10825-023-02106-9","url":null,"abstract":"<div><p>In this investigation, we develop CdS-free non-toxic thin-film solar cell structure with antimony sulfide (Sb<sub>2</sub>S<sub>3</sub>) as an absorber material. Sb<sub>2</sub>S<sub>3</sub> has found to be a promising candidate for production of renewable energy. Solar cells based on Sb<sub>2</sub>S<sub>3</sub> have been attracted worldwide attraction due to their outstanding efficiency and low cost. To serve as an optimistic buffer layer, 3C-SiC (cubic silicon carbide) is used thanks to its suitable bandgap to replace toxic cadmium sulfide (CdS). SCAPS-1D (one-dimensional solar cell capacitance simulator) software has been employed to numerically investigate the performance of Sb<sub>2</sub>S<sub>3</sub>-based n-ZnO/n-3C-SiC/p-Sb<sub>2</sub>S<sub>3</sub> heterostructure solar cells. The influence of absorber/buffer layer thickness, acceptor/donor densities, and defect density on device working have been investigated. Consequently, the role of defects in p-Sb<sub>2</sub>S<sub>3</sub> along with the significance of n-3C-SiC/p-Sb<sub>2</sub>S<sub>3</sub> interface defects has been studied to provide recommendations for achieving high efficiency. The proposed structure provides the enhanced efficiency of 17% under 1.5 G illumination spectrum. The parameters regarding solar cell performance such as <i>V</i><sub>oc</sub>, <i>J</i><sub>sc</sub>, FF, QE and η have been studied graphically. This novel structure may have considerable influence on progress of improved photovoltaic devices in future.</p></div>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":null,"pages":null},"PeriodicalIF":2.1,"publicationDate":"2023-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71910047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-20DOI: 10.1007/s10825-023-02105-w
Vineet Jaiswal, Trailokya Nath Sasamal
Nanomagnetic logic is a recent technology used in electronic devices and systems. The current challenge in circuit miniaturization has prompted a move away from the traditional metal-oxide-semiconductor technology. Nanomagnetic logic-based devices have no leakage current, and they are also non-volatile. In this paper, we propose run-time reconfigurable layout designs for the logic gates, and to show the applicability of the logic gates, we implement a single-bit comparator design. For the logic gate designs, we use slant-edge nanomagnets of different shapes as inputs. The proposed layout designs are verified using the MuMax3 micro-magnetic simulation tool, and results are compared with a previous approach. The implementation of a single-bit comparator design can significantly reduce the number of nanodots required, typically by (sim)50–80%, as well as the area occupancy, which can be reduced by (sim)56–99%.
{"title":"Run-time reconfigurable nanomagnetic logic gates and comparator designs using very high-permeability material","authors":"Vineet Jaiswal, Trailokya Nath Sasamal","doi":"10.1007/s10825-023-02105-w","DOIUrl":"10.1007/s10825-023-02105-w","url":null,"abstract":"<div><p> Nanomagnetic logic is a recent technology used in electronic devices and systems. The current challenge in circuit miniaturization has prompted a move away from the traditional metal-oxide-semiconductor technology. Nanomagnetic logic-based devices have no leakage current, and they are also non-volatile. In this paper, we propose run-time reconfigurable layout designs for the logic gates, and to show the applicability of the logic gates, we implement a single-bit comparator design. For the logic gate designs, we use slant-edge nanomagnets of different shapes as inputs. The proposed layout designs are verified using the <i>MuMax3</i> micro-magnetic simulation tool, and results are compared with a previous approach. The implementation of a single-bit comparator design can significantly reduce the number of nanodots required, typically by <span>(sim)</span>50–80%, as well as the area occupancy, which can be reduced by <span>(sim)</span>56–99%.</p></div>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":null,"pages":null},"PeriodicalIF":2.1,"publicationDate":"2023-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71910110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-19DOI: 10.1007/s10825-023-02103-y
El-Sayed R. Khattab, Walid M. I. Hassan, Tamer S. El-Shazly, Magdy A. M. Ibrahim, Sayed S. Abd El Rehim
First-principles calculations using the Hubbard approach (DFT + U) with PBEsol correlation were performed to compare the effects of incorporating 3d, 4d, and 5d metal atoms on the electronic and optical properties of m-HfO2. Incorporating metal atoms in the HfO2 crystal structure shifted the band gap edges and lowered the conduction band minimum, reducing the band gap as follows: 5.24 eV for HfO2, 3.26 eV for HfO2:Ti, 1.12 eV for HfO2:W, and 0.92 eV for HfO2:Nb. Total and partial density of states calculations showed that the valence band maximum of pristine HfO2 is mainly constructed from O 2p states, while the conduction band minimum is mainly from Hf 4d states. For doped crystals, the conduction band minimum is mainly from 3d states of Ti, 4d states of Nb, and 5d states of W. For pristine HfO2, the calculated dielectric constant, reflectivity and refractive index match available experimental and theoretical data. For doped systems, incorporating Nb (4d metal) and W (5d metal) had similar effects on the electronic and optical properties of HfO2, differing more from incorporating Ti (3d metal). HfO2 absorption roughly doubled upon Ti atom insertion (HfO2:Ti). Based on the results of this study, we would like to emphasize that these results provide a solid theoretical starting point that motivates further experimental studies into the application potential of these doped metal oxide systems.
{"title":"Comparative study for effect of Ti, Nb and W incorporation on the electronic and optical properties of pristine hafnia (m-HfO2): DFT theoretical prospective","authors":"El-Sayed R. Khattab, Walid M. I. Hassan, Tamer S. El-Shazly, Magdy A. M. Ibrahim, Sayed S. Abd El Rehim","doi":"10.1007/s10825-023-02103-y","DOIUrl":"10.1007/s10825-023-02103-y","url":null,"abstract":"<div><p>First-principles calculations using the Hubbard approach (DFT + U) with PBEsol correlation were performed to compare the effects of incorporating 3d, 4d, and 5d metal atoms on the electronic and optical properties of<i> m</i>-HfO<sub>2</sub>. Incorporating metal atoms in the HfO<sub>2</sub> crystal structure shifted the band gap edges and lowered the conduction band minimum, reducing the band gap as follows: 5.24 eV for HfO<sub>2</sub>, 3.26 eV for HfO<sub>2</sub>:Ti, 1.12 eV for HfO<sub>2</sub>:W, and 0.92 eV for HfO<sub>2</sub>:Nb. Total and partial density of states calculations showed that the valence band maximum of pristine HfO<sub>2</sub> is mainly constructed from O 2p states, while the conduction band minimum is mainly from Hf 4d states. For doped crystals, the conduction band minimum is mainly from 3d states of Ti, 4d states of Nb, and 5d states of W. For pristine HfO<sub>2</sub>, the calculated dielectric constant, reflectivity and refractive index match available experimental and theoretical data. For doped systems, incorporating Nb (4d metal) and W (5d metal) had similar effects on the electronic and optical properties of HfO<sub>2</sub>, differing more from incorporating Ti (3d metal). HfO<sub>2</sub> absorption roughly doubled upon Ti atom insertion (HfO2:Ti). Based on the results of this study, we would like to emphasize that these results provide a solid theoretical starting point that motivates further experimental studies into the application potential of these doped metal oxide systems.</p></div>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":null,"pages":null},"PeriodicalIF":2.1,"publicationDate":"2023-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71909901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-13DOI: 10.1007/s10825-023-02099-5
Neha Garg, Yogesh Pratap, Sneha Kabra
The aim of this paper is to propose a compact device to design a multiplexer and demultiplexer which can reduce the circuit area while maintaining competitive performance. A novel device, the dielectric-separated independent-gate junctionless transistor (DSIG-JLT), is used to implement functional logic of a multiplexer and demultiplexer. The DSIG-JLT has four gates that can be electrically controlled in multiple ways to realize different digital logics. The DSIG-JLT is used to realize a 2 × 1 multiplexer and 1 × 2 demultiplexer by two different logic styles. The 2 × 1 multiplexer is implemented using four transistors, and the 1 × 2 demultiplexer is implemented using five transistors by NAND logic (logic style-1). Further, by using mixed logic, the 2 × 1 multiplexer is designed using three transistors, and the 1 × 2 demultiplexer using four transistors (logic style-2). A 4 × 1 multiplexer is also implemented using eight transistors. The propagation delay, rise time, and fall time of the 2 × 1 multiplexer (logic style-1) are calculated and are found to be 24.45 ps, 31 ps, and 8.2 ps, respectively, at a supply voltage (VDD) of 1 V. It is found that with a change in supply voltage from 0.7 to 1.0 V, the delay, rise time, and fall time decrease by 17.2%, 11.4%, and 65.69%, respectively. Simulations are carried using the ATLAS 3D device simulator in mixed mode.