Journal of Computational Electronics最新文献

Quantum cellular automata (QCAs) are a promising alternative to traditional CMOS technology due to their lower power consumption and ability to function at the nanoscale. However, challenges such as fault tolerance and energy efficiency remain, especially for arithmetic circuits like multipliers. The Vedic multiplier, known for its reduced computational complexity, presents a valuable opportunity to address these issues. By implementing fault-tolerant mechanisms within the QCA architecture, we aim to improve the reliability and performance of n x n multipliers in critical applications, such as cryptography, signal processing, and neural network accelerators. The proposed Vedic multiplier is designed using a hybrid of Urdhva Tiryakbhyam Sutra (vertical and crosswise technique) and error-correcting QCA gates to ensure fault tolerance. The design is implemented in a hierarchical manner, utilizing optimized QCA logic gates to form the partial product generation and summation stages. Error detection and correction techniques, such as cellular redundancy and parity-based correction, are embedded within the architecture to ensure resilience against cell misalignment and tunneling errors. Power consumption is minimized by optimizing the layout to reduce wire crossings and cell interactions. The energy efficiency and fault tolerance of the design are evaluated using QCADesigner. Simulation results demonstrate that the proposed Vedic multiplier achieves a 30% reduction in power consumption compared to conventional QCA multiplier designs. Fault tolerance is improved, with the system being able to detect and correct up to 95% of single-cell faults during operation. The delay is minimized by 20%, ensuring high-speed performance. Additionally, the energy dissipation per computation is found to be 8.5 aJ (attojoules), making the design highly energy efficient for nanoscale applications. The proposed Robust and Energy-Efficient Fault-Tolerant n x n Vedic Multiplier offers significant improvements in power efficiency and fault tolerance, making it ideal for next-generation QCA-based systems. The Vedic multiplier's inherent simplicity, combined with advanced error correction mechanisms, enables reliable and high-performance multiplication operations at the nanoscale. These results highlight the potential of QCA for applications requiring energy-efficient and fault-resilient computing systems, such as cryptography, machine learning, and low-power IoT devices.

Fractal structures are natural patterns that repeat themselves. They have several unique features that make them ideal for solar energy absorption and sensing applications. In this study, we present a high-performance, polarization insensitive solar absorber comprises of a nickel (Ni)-made hash-shaped fractal geometry develop over a thin layer of gallium-doped zinc oxide (GZO) features a high absorption rate that covers the visible and near-infrared wavelengths of the spectrum. The results show that broadband aggregative absorptivity of 92% is attained between 380 nm and 3850 nm attributed to remarkable localized surface plasmon resonance (LSPR) induced by the periodic array of Ni nano-resonators and surface plasmon resonance (SPR) at the interface of GZO-SiO₂ layers. Further, the absorptivity remains above 90% from 670 nm to 3850 nm over a bandwidth of 3180 nm. With the utility of high-temperature resilient materials in the developed metamaterial structure, it shows potential for the thermal applications; as the results indicate the maximum heat radiation efficiency is 92.88% at 1600 K. Aside from that, we provide insight into the broadband high solar light capturing characteristics of the proposed device with the support of surface current density and electric field distribution study at the selective wavelengths. Furthermore, the device’s parametric study revealed a minor impact on its absorptivity/emissivity characteristics while also suggesting its robustness, which could be useful in device manufacture process. The overall benefits of the proposed device show its potential for high-temperature solar energy harvesting applications and solar thermophotovoltaic (STPV) cells.

An in-plane high-g microelectromechanical systems (MEMS) accelerometer is designed for ultra-large acceleration measurements. The proposed device is a piezoresistive MEMS accelerometer, in which piezoresistors are employed as signal transduction elements. Unlike conventional cantilever-beam-supported structures, the proof mass is supported by four suspended thin plates to enhance structural stiffness and reliability under high-g shock loading. The sensing structure is bonded to the substrate using bonding technology. The accelerometer adopts an in-plane sensing configuration, where the applied acceleration is perpendicular to the surface of the proof mass. This configuration effectively avoids large shear stresses at the bonding interface under extreme acceleration, thereby improving the mechanical robustness and service life of the device in high-g applications. Four piezoresistors are symmetrically fabricated at the roots of the suspended thin plates to convert structural deformation into resistance variations. The feasibility of the proposed design is validated through theoretical analysis and finite element method (FEM) simulations, and an optimal structural design is obtained. Simulation results indicate that the measurement range of the accelerometer can reach 100,000 g, while the overload resistance can reach 200,000 g. The optimized dimensions include a proof mass side length of 1000(mu m), suspended thin plates with a length of 600(mu m) and a width of 320(mu m), a structural thickness of 80(mu m), and a gap of 5(mu m)between the lower surface of the structure and the substrate. The results demonstrate that the proposed accelerometer is suitable for high-g acceleration measurement applications

We study (Ag:HfO₂), designed to act simultaneously as an antireflective coating (ARC) and an intermediate reflective layer (IRL) in planar amorphous silicon (a-Si) solar cells. The optical behavior is analyzed using Scilab-based simulations with the Transfer Matrix Method (TMM), enabling precise modeling of light propagation and interference within multilayer structures. Silver incorporation modifies the HfO₂ permittivity via free-carrier effects described by the Drude model, producing epsilon-near-zero (ENZ) conditions and regions with negative permittivity. These properties enhance light trapping and absorption by minimizing front surface reflection and boosting internal reflection at the rear interface. The proposed planar approach improves optical absorption and internal quantum efficiency (IQE) without requiring complex nanostructures, offering a scalable, fabrication-compatible strategy for high-efficiency thin-film solar cells.

This research presents a surface plasmon resonance (SPR) sensor based on photonic crystal fiber (PCF), specifically designed for the detection of diabetes. Gold is used as the plasmonic material in a layered configuration to enhance sensor performance. The proposed design is analyzed using the finite element method (FEM) to assess its capability in identifying diabetes-related variations. The PCF structure features two rings of air holes organized in a hexagonal pattern, with a thin layer of gold plating applied to enable SPR excitation. SPR occurs when the surface plasmon polariton (SPP) mode and the fundamental core mode interact under phase-matching conditions. Diabetes-specific samples, characterized by distinct refractive indices (RI), are filled into the fiber. Variations in RI cause shifts in the SPR resonance wavelength observed through confinement loss analysis. The resonance shift between normal and diabetic samples reflects their differing RI values. The sensor attains a sensitivity of 2400 nm/RIU, based on these spectral shifts. With its straightforward sensing mechanism, the proposed PCF-based SPR sensor offers a practical, economical approach to diabetes diagnosis.

A novel structure of Low Barrier Schottky contact Super Barrier Rectifier (LB-SSBR) is proposed by introducing a partial SiGe region in the device’s anode side, creating a low electron-barrier structure. This low-barrier structure ensures that LB-SSBR can appropriately thicken the oxide layer without affecting the forward conduction characteristics, thereby improving the Single Event Gate Rupture (SEGR) tolerance. The TCAD simulation results show that, under the condition of no increase in reverse leakage current, the SEGR tolerance of LB-SSBR is significantly stronger than that of conventional SSBR. When heavy ions are incident from the most sensitive position of the device, the maximum electric field inside the oxide layer of LB-SSBR is 7.22 MV/cm, which is 46.08% lower than that of SSBR. Additionally, there is also a certain degree of improvement in both forward conduction and reverse recovery characteristics. The forward conduction voltage of LB-SSBR has decreased by 13.44%, and the reverse recovery charge of LB-SSBR has reduced by 38.34% compared to SSBR. In addition, the existing molecular-beam epitaxy (MBE) process can achieve the epitaxy of SiGe on Si substrate, making it convenient to prepare LB-SSBR structures.

Displacement and naturel frequency are the most important design parameters for diaphragms based microelectromechanical system (MEMS) pressure sensors. For nonconventional diaphragm design of MEMS devices, finite element method (FEM)-based analysis to obtain these two parameters requires quite long time and cost as compared to conventional diaphragm design including circular, square, and rectangular shape. Thus, one major disadvantage of FEM is the excessive time required for simulation. Machine learning (ML) algorithms might be an alternative approach to FEM analysis. ML algorithms, which is an easier, functional, and time and cost saving, might provide rapid prediction of essential information comprising displacement and naturel frequency of MEMS diaphragm design with accurate and reliable results. In this study, ML algorithms including XGBoost regressor, LightGBM regressor, CatBoost regressor, and TabNet regressor were used to estimate displacement (µm) and frequency (Hz) of perforated low temperature co-fired ceramic (LTCC) diaphragms using 200 FEM-based numerical results. Predicted results were compared by considering R², MAE, RMSE, and MAPE metric. According to these results, best performance was obtained by CatBoost regressor with the values of R² = 0.927 and R² = 0.995 for the displacement and frequency prediction, respectively. It was realized that CatBoost strikes an exceptional balance between computational efficiency and predictive performance, while LightGBM emerges as a strong alternative for scenarios prioritizing speed and memory efficiency. As a result, it was concluded that ML algorithms might be a useful, cost, and time effective tools for rapid analysis of displacement and naturel frequency of perforated diaphragms without requiring FEM analysis.

A Quantum Dot Cellular Automata (QCA) is a nanotechnology-driven computing method that leverages quantum mechanical principles. This work demonstrates the efficient use of reversible logic gates in QCA-based systems, a crucial aspect of scalable and energy-efficient computer designs. In this research, we propose an energy-efficient, compact XOR gate and several common reversible logic gates. The paper further illustrates the use of these gates to construct essential components, such as a one-bit comparator and an arithmetic logic unit (ALU). The ALU, designed with Feynman and Toffoli gates, is capable of performing eight arithmetic and logical operations. We conduct a comprehensive evaluation of cell complexity, area efficiency, delay, area-delay product (ADP), and energy dissipation. Additionally, we compare the characteristics of the proposed circuits with prior efforts to highlight advancements and identify areas for further improvement in reversible computing paradigms. The recommended architecture enhances the performance of the XOR gate, reversible logic gates, one-bit comparator, and ALU. The XOR gate achieves a 67.86% reduction in cell complexity, an 85% improvement in area efficiency, and a 50% reduction in quantum cost. Feynman and Toffoli gates demonstrate a 75% reduction in area and an 87.5% reduction in quantum cost. For the one-bit comparator and ALU, the proposed solution reduces area by 87% and latency by 40%, saving both space and time. With a quantum cost that is 90% lower than traditional designs, the proposed architecture optimizes quantum circuits for real-world applications.

This study investigates the scaling behavior of the Dual Interbridge Tree-shaped Nanosheet FET (DIB-TreeFET) for sub-3 nm digital logic applications. Device-level simulations using Sentaurus TCAD explore the effects of varying interbridge thickness ((IB_{T})) from 10 nm to 30 nm and nanosheet thickness ((N_{T})) from 3 to 9 nm, while keeping other parameters constant. Increasing (IB_{T}) results in a 1.71 times improvement in (I_{ON}), and similarly, increasing (N_{T}) from 3 nm to 5 nm results in an enhancement in (I_{ON}) of about 1.58 times. However, both parameters also contribute to less pronounced threshold voltage roll-off, indicating stronger short-channel effects. Optimal device performance is observed at (IB_{T}) as 20 nm and (N_{T}) as 5 nm. A CMOS inverter built with this configuration is evaluated under varying V_DD, load capacitance (10–1000 aF), and input frequency (1–50 GHz). Key metrics, including propagation delay, power-delay product (PDP), and energy-delay product (EDP), are assessed. A tradeoff point at V_DD=0.575 V offers balanced performance. At V_DD=0.7 V, the inverter achieves noise margins of 0.29 V ((NM_{H})) and 0.32 V ((NM_{L})), with a voltage gain of 9.98, demonstrating its suitability for ultra-scaled low-power logic applications.

Acoustic sensing applications are being actively explored across a wide range of fields, including consumer electronics, biomedical devices, industrial applications, space technology, and military-grade equipment. In the past, the electret condenser microphone (ECM) was the primary technology used for sound detection. However, advancements in micro-electro-mechanical systems (MEMS) acoustic sensors have transformed the landscape. With the stabilization of MEMS manufacturing processes, these sensors are now increasingly integrated into mobile phones, wearable devices, Bluetooth headsets, hearing aids, digital cameras, automotive voice control systems, and environmental monitoring equipment. Developing silicon MEMS acoustic sensors may seem straightforward, but it involves addressing a range of complex and inherent challenges. This paper provides a comprehensive overview of the materials and technologies involved in the development of MEMS acoustic sensors. We discuss various sensing mechanisms, including piezoresistive, capacitive, piezoelectric, triboelectric, optical, and Spin-MEMS technologies. Additionally, we outline the design techniques used in sensor development. Furthermore, we explore AI-based methods to improve sensor sensitivity and examine the operational parameters of commercial MEMS microphones.