Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012093
Hong-Yi Huang, Fu-Chien Tsai
This work proposes a topology using a ring oscillator with sub-feedback loops to generate multiple phases. It is composed of an N-stage main ring (arbitrary N larger than 3) and k-stage sub-feedback loops, where k is not the common divisor of N, N output phases can be obtained. With a linear model analysis, it comes to a result that oscillating frequency is related to k, and the phase difference between adjacent stages. With smaller k, higher oscillating frequency can be achieved.
{"title":"Analysis and optimization of ring oscillator using sub-feedback scheme","authors":"Hong-Yi Huang, Fu-Chien Tsai","doi":"10.1109/DDECS.2009.5012093","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012093","url":null,"abstract":"This work proposes a topology using a ring oscillator with sub-feedback loops to generate multiple phases. It is composed of an N-stage main ring (arbitrary N larger than 3) and k-stage sub-feedback loops, where k is not the common divisor of N, N output phases can be obtained. With a linear model analysis, it comes to a result that oscillating frequency is related to k, and the phase difference between adjacent stages. With smaller k, higher oscillating frequency can be achieved.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"76 1","pages":"28-29"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72637495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012110
O. Ginez, J. Portal, H. Aziza
The constant evolution of technologies involves a large amount of problems during and after Flash memory manufacturing. In this context, manufacturers must develop methods and design solutions to improve reliability especially for automotive applications. For this purpose, ECC and BISR are probably the most efficient concepts to enhance memory reliability. However, such techniques are limited to correct errors occurring punctually within a word whereas in memories the stress of peripheral circuit can lead to an entire faulty bit or word line. This phenomenon is referred as Clustering Effect. This work proposes an on-line testing structure for clustering effects according to the word line plan. This test structure allows achieving a test time acceptable and is shown as low cost in term of surface overhead (3 HV transistors, 1 XOR, 1 MUX and 1 DFF). Adding our solution to recent ECC and BISR techniques, spatial or automotive applications could be easily targeted.
{"title":"An on-line testing scheme for repairing purposes in Flash memories","authors":"O. Ginez, J. Portal, H. Aziza","doi":"10.1109/DDECS.2009.5012110","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012110","url":null,"abstract":"The constant evolution of technologies involves a large amount of problems during and after Flash memory manufacturing. In this context, manufacturers must develop methods and design solutions to improve reliability especially for automotive applications. For this purpose, ECC and BISR are probably the most efficient concepts to enhance memory reliability. However, such techniques are limited to correct errors occurring punctually within a word whereas in memories the stress of peripheral circuit can lead to an entire faulty bit or word line. This phenomenon is referred as Clustering Effect. This work proposes an on-line testing structure for clustering effects according to the word line plan. This test structure allows achieving a test time acceptable and is shown as low cost in term of surface overhead (3 HV transistors, 1 XOR, 1 MUX and 1 DFF). Adding our solution to recent ECC and BISR techniques, spatial or automotive applications could be easily targeted.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"19 1","pages":"120-123"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82543771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012127
J. Giesl, Ladislav Behal, K. Vlcek
Many image encryption schemes based on chaotic iterative maps are very expensive in terms of processing speed. This inconvenient feature causes the inapplicability in real-time processes. Hence, encryption scheme must be projected at low-level. This paper proposes hardware solution of image encryption with keeping the high security of encrypted image and speeding up the encryption process.
{"title":"Hardware solution of chaos based image encryption","authors":"J. Giesl, Ladislav Behal, K. Vlcek","doi":"10.1109/DDECS.2009.5012127","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012127","url":null,"abstract":"Many image encryption schemes based on chaotic iterative maps are very expensive in terms of processing speed. This inconvenient feature causes the inapplicability in real-time processes. Hence, encryption scheme must be projected at low-level. This paper proposes hardware solution of image encryption with keeping the high security of encrypted image and speeding up the encryption process.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"27 1","pages":"198-201"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76487055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012118
Peter Tummeltshammer, A. Steininger
The principle of duplication and comparison has proven very efficient for error detection in processor cores, since it can be applied as a generic solution for making virtually any type of core fail safe. A weakness of this approach, however, is the potential for common cause faults: Faults affecting both cores in the same way will escape detection. Shared resources and signals are especially prone to such effects. In practice the efforts for providing a redundant power source are often prohibitive, thus rendering the power supply such a shared resource. While a complete failure of the supply voltage can be relatively easily accommodated in a fail safe system, short pulses can have subtle consequences and are therefore much more dangerous. In this paper we will perform an experimental study of the potential of such power supply induced faults to create common cause effects. For this purpose we first study their effects on the operation of a processor core. In particular we will show that, when applied with the most adverse parameters, they tend to cause timing violations in the critical path. In two instances of the same core there is therefore a non-negligible risk of common cause effects. We will quantitatively assess this risk through fault injection experiments into an FPGA based dual core design.
{"title":"On the role of the power supply as an entry for common cause faults—An experimental analysis","authors":"Peter Tummeltshammer, A. Steininger","doi":"10.1109/DDECS.2009.5012118","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012118","url":null,"abstract":"The principle of duplication and comparison has proven very efficient for error detection in processor cores, since it can be applied as a generic solution for making virtually any type of core fail safe. A weakness of this approach, however, is the potential for common cause faults: Faults affecting both cores in the same way will escape detection. Shared resources and signals are especially prone to such effects. In practice the efforts for providing a redundant power source are often prohibitive, thus rendering the power supply such a shared resource. While a complete failure of the supply voltage can be relatively easily accommodated in a fail safe system, short pulses can have subtle consequences and are therefore much more dangerous. In this paper we will perform an experimental study of the potential of such power supply induced faults to create common cause effects. For this purpose we first study their effects on the operation of a processor core. In particular we will show that, when applied with the most adverse parameters, they tend to cause timing violations in the critical path. In two instances of the same core there is therefore a non-negligible risk of common cause effects. We will quantitatively assess this risk through fault injection experiments into an FPGA based dual core design.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"31 1","pages":"152-157"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82346232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012140
A. Yúfera, A. Rueda
This paper proposes a new method for bio-impedance measurement useful to 2D processing of cell cultures. It allows to represent biological samples by using a new impedance sensing method, and exploiting the electrode-to-cell model for both electrical simulation and imaging reconstruction. Preliminary electrical simulations are reported to validate the proposal for Electrical Cell Impedance Spectroscopy (ECIS) applications. The results reported show that low concentration cell culture can be correctly sensed and displayed at several frequencies using the proposed CMOS system.
{"title":"A CMOS bio-impedance measurement system","authors":"A. Yúfera, A. Rueda","doi":"10.1109/DDECS.2009.5012140","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012140","url":null,"abstract":"This paper proposes a new method for bio-impedance measurement useful to 2D processing of cell cultures. It allows to represent biological samples by using a new impedance sensing method, and exploiting the electrode-to-cell model for both electrical simulation and imaging reconstruction. Preliminary electrical simulations are reported to validate the proposal for Electrical Cell Impedance Spectroscopy (ECIS) applications. The results reported show that low concentration cell culture can be correctly sensed and displayed at several frequencies using the proposed CMOS system.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"54 1","pages":"252-257"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86601102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012103
Jacek Gradzki, T. Borejko, W. Pleskacz
In this paper, two topologies of CMOS low noise amplifiers (LNAs) have been simulated. The inductively degenerated cascode (LC), which achieves high gain and low noise figure (NF), and folded cascode (FC), which can work with ultra low supply voltage, were considered. LNAs were optimized for a GPS/Galileo receiver using UMC 90 nm CMOS technology. Chosen circuits demonstrate a gain of 16.42 dB and 17.27 dB, consuming current 2.492 mA and 3.093 mA, showing NF 1.881 dB and 1.914 dB, third order input interception point (IIP3) −14.99 dBm and −13.3 dBm, input referred 1-dB compression point (Pin-1) −29 dBm and −29.47 dBm for inductively degenerated cascode and folded cascode respectively. Both input return loss (S11) and output return loss (S22) are below −40 dB. For these circuits supply voltage is 0.6 V and die area equals 0.33 mm2.
{"title":"Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS","authors":"Jacek Gradzki, T. Borejko, W. Pleskacz","doi":"10.1109/DDECS.2009.5012103","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012103","url":null,"abstract":"In this paper, two topologies of CMOS low noise amplifiers (LNAs) have been simulated. The inductively degenerated cascode (LC), which achieves high gain and low noise figure (NF), and folded cascode (FC), which can work with ultra low supply voltage, were considered. LNAs were optimized for a GPS/Galileo receiver using UMC 90 nm CMOS technology. Chosen circuits demonstrate a gain of 16.42 dB and 17.27 dB, consuming current 2.492 mA and 3.093 mA, showing NF 1.881 dB and 1.914 dB, third order input interception point (IIP3) −14.99 dBm and −13.3 dBm, input referred 1-dB compression point (Pin-1) −29 dBm and −29.47 dBm for inductively degenerated cascode and folded cascode respectively. Both input return loss (S11) and output return loss (S22) are below −40 dB. For these circuits supply voltage is 0.6 V and die area equals 0.33 mm2.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"20 1","pages":"78-83"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87425490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012139
Kameswar Rao Vaddina, E. Nigussie, P. Liljeberg, J. Plosila
As the number of cores increases thermal challenges increase, thereby degrading the performance and reliability of the system. We approach this challenge with a self-timed thermal monitoring method which is based on the use of thermal sensors. Since leakage currents are sensitive to temperature and increase with scaling, we propose the use of a leakage current based thermal sensing for monitoring purposes. In this work we have implemented a novel thermal sensing circuit in 65nm CMOS technology, which converts analog temperature information into digital form. We have also proposed a novel thermal sensing and monitoring interconnection network structure based on self-timed signaling, comprising of an encoder/transmitter and decoder/ receiver. We have performed power supply noise, additive noise on sensor input signal and dynamic power supply voltage variation analysis on the thermal sensing circuit and show that it is robust enough under different operating temperatures.
{"title":"Self-timed thermal sensing and monitoring of multicore systems","authors":"Kameswar Rao Vaddina, E. Nigussie, P. Liljeberg, J. Plosila","doi":"10.1109/DDECS.2009.5012139","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012139","url":null,"abstract":"As the number of cores increases thermal challenges increase, thereby degrading the performance and reliability of the system. We approach this challenge with a self-timed thermal monitoring method which is based on the use of thermal sensors. Since leakage currents are sensitive to temperature and increase with scaling, we propose the use of a leakage current based thermal sensing for monitoring purposes. In this work we have implemented a novel thermal sensing circuit in 65nm CMOS technology, which converts analog temperature information into digital form. We have also proposed a novel thermal sensing and monitoring interconnection network structure based on self-timed signaling, comprising of an encoder/transmitter and decoder/ receiver. We have performed power supply noise, additive noise on sensor input signal and dynamic power supply voltage variation analysis on the thermal sensing circuit and show that it is robust enough under different operating temperatures.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"39 1","pages":"246-251"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85879921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012123
M. Kubar, O. Subrt, P. Martínek, J. Jakovenko
This paper deals with the ADC non-linearity extraction using a newly developed Virtual Testing Environment (VTE). The VTE proposed is built on Verilog-A implementation of the Servo-Loop unit fully integrated into Cadence design environment. The Servo-Loop method used is aimed at the nonlinearity extraction of static ADC transfer curve; in this paper, we prove an advanced Servo-Loop version focusing on behavioral and transistor-level example of the Residual Signed Digit (RSD) cyclic A/D converter design. Powerful capabilities of the proposed VTE were successfully confirmed by a large set of behavioral and transistor-level simulations in Spectre.
{"title":"Experience in Virtual Testing of RSD cyclic A/D converters","authors":"M. Kubar, O. Subrt, P. Martínek, J. Jakovenko","doi":"10.1109/DDECS.2009.5012123","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012123","url":null,"abstract":"This paper deals with the ADC non-linearity extraction using a newly developed Virtual Testing Environment (VTE). The VTE proposed is built on Verilog-A implementation of the Servo-Loop unit fully integrated into Cadence design environment. The Servo-Loop method used is aimed at the nonlinearity extraction of static ADC transfer curve; in this paper, we prove an advanced Servo-Loop version focusing on behavioral and transistor-level example of the Residual Signed Digit (RSD) cyclic A/D converter design. Powerful capabilities of the proposed VTE were successfully confirmed by a large set of behavioral and transistor-level simulations in Spectre.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"202 1","pages":"178-181"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78760094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012102
K. Schweiger, H. Uhrmann, H. Zimmermann
An innovative design with simulation results of a low-voltage bulk driven mixer for direct conversion receiver is presented. The circuit is designed in a 65nm digital CMOS process without analog extensions. It offers a conversion gain of 22dB at a clock frequency of 1.5GHz for GALILEO/GPS applications. The design is capable of operating at up to 7GHz with only 3dB gain decrease. The simulated noise figure is 27dB with a power consumption of 730µW. Simulations at a supply voltage of 0.9V instead of 1.2V show a gain decrease of only 3dB while the noise figure increases by 2dB.
{"title":"Low-voltage low-power double bulk mixer for direct conversion receiver in 65nm CMOS","authors":"K. Schweiger, H. Uhrmann, H. Zimmermann","doi":"10.1109/DDECS.2009.5012102","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012102","url":null,"abstract":"An innovative design with simulation results of a low-voltage bulk driven mixer for direct conversion receiver is presented. The circuit is designed in a 65nm digital CMOS process without analog extensions. It offers a conversion gain of 22dB at a clock frequency of 1.5GHz for GALILEO/GPS applications. The design is capable of operating at up to 7GHz with only 3dB gain decrease. The simulated noise figure is 27dB with a power consumption of 730µW. Simulations at a supply voltage of 0.9V instead of 1.2V show a gain decrease of only 3dB while the noise figure increases by 2dB.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"37 1","pages":"74-77"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77794041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012135
G. Borowik, T. Luba, B. Falkowski
This paper presents a new cost-efficient realization scheme of pattern matching circuits in FPGA structures with embedded memory blocks (EMB). The general idea behind the proposed method is to implement combinational circuits using a net of finite state machines (FSM) instead. The application of functional decomposition method reduces the utilization of resources by implementing FSMs using both EMBs and LUT-based programmable logic blocks available in contemporary FPGAs. Experimental results for the proposed method are also shown. A comparison with another dedicated method yields extremely encouraging results: with a comparable number of EMBs, the number of logic cells has been reduced by 95%.
{"title":"Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories","authors":"G. Borowik, T. Luba, B. Falkowski","doi":"10.1109/DDECS.2009.5012135","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012135","url":null,"abstract":"This paper presents a new cost-efficient realization scheme of pattern matching circuits in FPGA structures with embedded memory blocks (EMB). The general idea behind the proposed method is to implement combinational circuits using a net of finite state machines (FSM) instead. The application of functional decomposition method reduces the utilization of resources by implementing FSMs using both EMBs and LUT-based programmable logic blocks available in contemporary FPGAs. Experimental results for the proposed method are also shown. A comparison with another dedicated method yields extremely encouraging results: with a comparable number of EMBs, the number of logic cells has been reduced by 95%.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"81 1","pages":"230-233"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80993411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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