Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012130
A. Timár, G. Bognár
In this paper a new approach for measuring depth values of cavities of Micro-Electro Mechanical System (MEMS) is presented. This measurement was done by using a simple optical microscope and image processing techniques. The sample need not to be treated with any foreign material such as reflective or conductive coating.
{"title":"Contactless characterization of MEMS devices using optical microscopy","authors":"A. Timár, G. Bognár","doi":"10.1109/DDECS.2009.5012130","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012130","url":null,"abstract":"In this paper a new approach for measuring depth values of cavities of Micro-Electro Mechanical System (MEMS) is presented. This measurement was done by using a simple optical microscope and image processing techniques. The sample need not to be treated with any foreign material such as reflective or conductive coating.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"1 1","pages":"210-213"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76051862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012126
Y. C. Chang, H. Kao, C. Kao, Chih-Wei Yang, J. S. Fu, N. Karmakar, Li-Chun Chang
In this paper, we present the low noise amplifier using new feedback connection configurations. The UWB LNA is design in 0.18 µm TSMC CMOS technique to achieve high gain, small size and low noise. The LNA achieved 11 dB of average power gain, low 2.87 dB noise figure (NF), −10.9 dB input match, −7 dB return loss, −3 dBm of IIP3 and only 0.54 mm2 size with 15 mW power consumption.
{"title":"0.18 µm CMOS UWB LNA with new feedback configuration for optimization low noise, high gain and small area","authors":"Y. C. Chang, H. Kao, C. Kao, Chih-Wei Yang, J. S. Fu, N. Karmakar, Li-Chun Chang","doi":"10.1109/DDECS.2009.5012126","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012126","url":null,"abstract":"In this paper, we present the low noise amplifier using new feedback connection configurations. The UWB LNA is design in 0.18 µm TSMC CMOS technique to achieve high gain, small size and low noise. The LNA achieved 11 dB of average power gain, low 2.87 dB noise figure (NF), −10.9 dB input match, −7 dB return loss, −3 dBm of IIP3 and only 0.54 mm2 size with 15 mW power consumption.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"30 1","pages":"194-197"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86086692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012143
Flavius Opritoiu, M. Vladutiu, M. Udrescu, L. Prodan
This paper presents a hardware architecture for online self-test in the context of Advanced Encryption Standard (AES). From the available range of techniques and solutions to be considered for increasing Built In Self-Test (BIST) capabilities, for various reasons - especially due to area requirements - we focused on parity control methods. Therefore, the paper presents a general solution proposing both a basic architecture and a new project designed at the gate level that relies on parity prediction techniques. The contribution brought by our architecture consists of a complete separation between the functional and test channels. The conclusive arguments reveal the proposed architecture as a solution for area reduction; performance and power consumption are also analyzed.
{"title":"Round-level concurrent error detection applied to Advanced Encryption Standard","authors":"Flavius Opritoiu, M. Vladutiu, M. Udrescu, L. Prodan","doi":"10.1109/DDECS.2009.5012143","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012143","url":null,"abstract":"This paper presents a hardware architecture for online self-test in the context of Advanced Encryption Standard (AES). From the available range of techniques and solutions to be considered for increasing Built In Self-Test (BIST) capabilities, for various reasons - especially due to area requirements - we focused on parity control methods. Therefore, the paper presents a general solution proposing both a basic architecture and a new project designed at the gate level that relies on parity prediction techniques. The contribution brought by our architecture consists of a complete separation between the functional and test channels. The conclusive arguments reveal the proposed architecture as a solution for area reduction; performance and power consumption are also analyzed.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"77 1","pages":"270-275"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88558153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012114
M. Rozkovec, O. Novák
We present a new concept of the test method for FPGA devices. Instead of being focused on structural test of the device, the method tests logic and interconnection resources of the FPGA, that are actually used by implemented circuit. The method is based on reconfiguration ability of nowadays FPGAs and utilizes test vectors originally created for ASIC circuits. We present an idea of circuit partitioning and a transcription scheme, that converts the FPGA netlist to the ASIC one. Preliminary results of test patterns efficiency on transformed benchmark circuits are presented.
{"title":"Structural test of programmed FPGA circuits","authors":"M. Rozkovec, O. Novák","doi":"10.1109/DDECS.2009.5012114","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012114","url":null,"abstract":"We present a new concept of the test method for FPGA devices. Instead of being focused on structural test of the device, the method tests logic and interconnection resources of the FPGA, that are actually used by implemented circuit. The method is based on reconfiguration ability of nowadays FPGAs and utilizes test vectors originally created for ASIC circuits. We present an idea of circuit partitioning and a transcription scheme, that converts the FPGA netlist to the ASIC one. Preliminary results of test patterns efficiency on transformed benchmark circuits are presented.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"52 1","pages":"136-139"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85128899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012112
K. Asada, Takuzo Sogabe, T. Nakura, M. Ikeda
We have compared the power supply noise tolerance of a synchronous processor and a self-timed processor fabricated using 0.18µm CMOS. We have designed the self-timed processor using the same RTL as the synchronous processor, and translated it into a netlist with DCVSL circuits and completion logic trees. We have demonstrated the synchronous processor shows an error rate of 9.3% for the worst power supply noise in case of 10% timing margin design. On the other hand, the self-timed processor shows 40% speed degradation, but no error, for the same power supply noise.
{"title":"Measurement of power supply noise tolerance of self-timed processor","authors":"K. Asada, Takuzo Sogabe, T. Nakura, M. Ikeda","doi":"10.1109/DDECS.2009.5012112","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012112","url":null,"abstract":"We have compared the power supply noise tolerance of a synchronous processor and a self-timed processor fabricated using 0.18µm CMOS. We have designed the self-timed processor using the same RTL as the synchronous processor, and translated it into a netlist with DCVSL circuits and completion logic trees. We have demonstrated the synchronous processor shows an error rate of 9.3% for the worst power supply noise in case of 10% timing margin design. On the other hand, the self-timed processor shows 40% speed degradation, but no error, for the same power supply noise.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"15 1","pages":"128-131"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87574023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012104
S. Devarakond, Shreyas Sen, A. Chatterjee
The recent demand in wireless standards capable of providing short-range, high-speed data transfer has accelerated the growth of the Ultra-Wide Band (UWB) standard. MB-OFDM (Multi Band Orthogonal Frequency Division Multiplexing) UWB devices suffer from frequency dependent non-idealities due to extreme wideband operation (3.1 to 10.6 GHz). Further these characteristics are subjected to process variations when implemented in nanometer technologies. In this paper we propose two BIST assisted methodologies for estimation and compensation of these effects. The proposed solutions differ in hardware vs. software tradeoffs. The improvement in the linearity of the mixer over a set of process instances and the tradeoffs involved are presented to validate the proposed methodology.
{"title":"BIST assisted wideband digital compensation for MB-UWB transmitters","authors":"S. Devarakond, Shreyas Sen, A. Chatterjee","doi":"10.1109/DDECS.2009.5012104","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012104","url":null,"abstract":"The recent demand in wireless standards capable of providing short-range, high-speed data transfer has accelerated the growth of the Ultra-Wide Band (UWB) standard. MB-OFDM (Multi Band Orthogonal Frequency Division Multiplexing) UWB devices suffer from frequency dependent non-idealities due to extreme wideband operation (3.1 to 10.6 GHz). Further these characteristics are subjected to process variations when implemented in nanometer technologies. In this paper we propose two BIST assisted methodologies for estimation and compensation of these effects. The proposed solutions differ in hardware vs. software tradeoffs. The improvement in the linearity of the mixer over a set of process instances and the tradeoffs involved are presented to validate the proposed methodology.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"83 1","pages":"84-89"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83400080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012115
Y. Berg, O. Mirmotahari
In this paper we present ultra low voltage low power CMOS logic. The low power gate may be configured or recharged to high speed or low power compared to a complementary inverter. The low power logic presented in this paper resembles precharge CMOS logic. For a low supply voltage a sleep mode configuration is presented which may reduce the power consumption to less than 0.5% of a complementary inverter. A sleep mode configuration of the low power logic is presented and a keeper function is added to increase the noise margin and reduce the static power consumption. Simulated data for a STM 90nm process using Spectre simulator provided by Cadence is included.
{"title":"Low voltage precharge CMOS logic","authors":"Y. Berg, O. Mirmotahari","doi":"10.1109/DDECS.2009.5012115","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012115","url":null,"abstract":"In this paper we present ultra low voltage low power CMOS logic. The low power gate may be configured or recharged to high speed or low power compared to a complementary inverter. The low power logic presented in this paper resembles precharge CMOS logic. For a low supply voltage a sleep mode configuration is presented which may reduce the power consumption to less than 0.5% of a complementary inverter. A sleep mode configuration of the low power logic is presented and a keeper function is added to increase the noise margin and reduce the static power consumption. Simulated data for a STM 90nm process using Spectre simulator provided by Cadence is included.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"142 1","pages":"140-143"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80567165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012089
F. A. Parsan, A. Ayatollahi, A. Abrishamifar
Effect of asymmetric operating condition of depletion-mode MOS capacitors on the linearity of MOSFET-only switched-capacitor ΔΣ modulators is investigated. In very low-voltage switched-capacitor circuits the opamp input and output common-mode levels are separated to provide maximum overdrive voltage for MOS switches. This causes an asymmetric voltage drop on capacitors during operation. On the other hand, the depletion-mode MOS capacitors are most linear when operated under a symmetric condition. The effect of this increased nonlinearity on a ΔΣ modulator which is operated under an asymmetric condition is simulated and the results are compared with a ΔΣ modulator which is operated under a symmetric condition.
{"title":"Investigating the linearity of MOSFET-only switched-capacitor ΔΣ modulators under low-voltage condition","authors":"F. A. Parsan, A. Ayatollahi, A. Abrishamifar","doi":"10.1109/DDECS.2009.5012089","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012089","url":null,"abstract":"Effect of asymmetric operating condition of depletion-mode MOS capacitors on the linearity of MOSFET-only switched-capacitor ΔΣ modulators is investigated. In very low-voltage switched-capacitor circuits the opamp input and output common-mode levels are separated to provide maximum overdrive voltage for MOS switches. This causes an asymmetric voltage drop on capacitors during operation. On the other hand, the depletion-mode MOS capacitors are most linear when operated under a symmetric condition. The effect of this increased nonlinearity on a ΔΣ modulator which is operated under an asymmetric condition is simulated and the results are compared with a ΔΣ modulator which is operated under a symmetric condition.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"9 1","pages":"12-15"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79110923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012128
M. Manik, E. Gramatová
The paper presents a system-level diagnosis based on a general symmetric diagnostic model - the PMC model. In particular, the one-step diagnosis of t-diagnosable systems and its Boolean formalization extension are presented. This extension transforms a syndrome decoding process to solving Boolean expressions. New rules for the PMC model were defined with their application to regular systems. Using the rules for such systems improves the syndrome-decoding process in time consumption.
{"title":"Diagnosis of faulty units in regular graphs under the PMC model","authors":"M. Manik, E. Gramatová","doi":"10.1109/DDECS.2009.5012128","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012128","url":null,"abstract":"The paper presents a system-level diagnosis based on a general symmetric diagnostic model - the PMC model. In particular, the one-step diagnosis of t-diagnosable systems and its Boolean formalization extension are presented. This extension transforms a syndrome decoding process to solving Boolean expressions. New rules for the PMC model were defined with their application to regular systems. Using the rules for such systems improves the syndrome-decoding process in time consumption.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"16 1","pages":"202-205"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82476374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012131
W. Friesenbichler, T. Panhofer, M. Delvai
The continuing downscaling of integrated circuits makes modern devices more susceptible to soft errors. This paper investigates the possibility of using Four-State Logic (FSL) to improve the fault tolerance of digital circuits. FSL is a possible implementation of asynchronous Quasi Delay Insensitive (QDI) logic using a more efficient encoding and handshake protocol. The behavior of FSL circuits when subjected to transient faults is analyzed. We present a method based on duplication and rail cross-coupling that allows to detect as well as correct soft errors autonomously. The concept is demonstrated by fault injection experiments.
{"title":"A comprehensive approach for soft error tolerant Four State Logic","authors":"W. Friesenbichler, T. Panhofer, M. Delvai","doi":"10.1109/DDECS.2009.5012131","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012131","url":null,"abstract":"The continuing downscaling of integrated circuits makes modern devices more susceptible to soft errors. This paper investigates the possibility of using Four-State Logic (FSL) to improve the fault tolerance of digital circuits. FSL is a possible implementation of asynchronous Quasi Delay Insensitive (QDI) logic using a more efficient encoding and handshake protocol. The behavior of FSL circuits when subjected to transient faults is analyzed. We present a method based on duplication and rail cross-coupling that allows to detect as well as correct soft errors autonomously. The concept is demonstrated by fault injection experiments.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"36 1","pages":"214-217"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82803464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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