Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012104
S. Devarakond, Shreyas Sen, A. Chatterjee
The recent demand in wireless standards capable of providing short-range, high-speed data transfer has accelerated the growth of the Ultra-Wide Band (UWB) standard. MB-OFDM (Multi Band Orthogonal Frequency Division Multiplexing) UWB devices suffer from frequency dependent non-idealities due to extreme wideband operation (3.1 to 10.6 GHz). Further these characteristics are subjected to process variations when implemented in nanometer technologies. In this paper we propose two BIST assisted methodologies for estimation and compensation of these effects. The proposed solutions differ in hardware vs. software tradeoffs. The improvement in the linearity of the mixer over a set of process instances and the tradeoffs involved are presented to validate the proposed methodology.
{"title":"BIST assisted wideband digital compensation for MB-UWB transmitters","authors":"S. Devarakond, Shreyas Sen, A. Chatterjee","doi":"10.1109/DDECS.2009.5012104","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012104","url":null,"abstract":"The recent demand in wireless standards capable of providing short-range, high-speed data transfer has accelerated the growth of the Ultra-Wide Band (UWB) standard. MB-OFDM (Multi Band Orthogonal Frequency Division Multiplexing) UWB devices suffer from frequency dependent non-idealities due to extreme wideband operation (3.1 to 10.6 GHz). Further these characteristics are subjected to process variations when implemented in nanometer technologies. In this paper we propose two BIST assisted methodologies for estimation and compensation of these effects. The proposed solutions differ in hardware vs. software tradeoffs. The improvement in the linearity of the mixer over a set of process instances and the tradeoffs involved are presented to validate the proposed methodology.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"83 1","pages":"84-89"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83400080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012115
Y. Berg, O. Mirmotahari
In this paper we present ultra low voltage low power CMOS logic. The low power gate may be configured or recharged to high speed or low power compared to a complementary inverter. The low power logic presented in this paper resembles precharge CMOS logic. For a low supply voltage a sleep mode configuration is presented which may reduce the power consumption to less than 0.5% of a complementary inverter. A sleep mode configuration of the low power logic is presented and a keeper function is added to increase the noise margin and reduce the static power consumption. Simulated data for a STM 90nm process using Spectre simulator provided by Cadence is included.
{"title":"Low voltage precharge CMOS logic","authors":"Y. Berg, O. Mirmotahari","doi":"10.1109/DDECS.2009.5012115","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012115","url":null,"abstract":"In this paper we present ultra low voltage low power CMOS logic. The low power gate may be configured or recharged to high speed or low power compared to a complementary inverter. The low power logic presented in this paper resembles precharge CMOS logic. For a low supply voltage a sleep mode configuration is presented which may reduce the power consumption to less than 0.5% of a complementary inverter. A sleep mode configuration of the low power logic is presented and a keeper function is added to increase the noise margin and reduce the static power consumption. Simulated data for a STM 90nm process using Spectre simulator provided by Cadence is included.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"142 1","pages":"140-143"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80567165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012135
G. Borowik, T. Luba, B. Falkowski
This paper presents a new cost-efficient realization scheme of pattern matching circuits in FPGA structures with embedded memory blocks (EMB). The general idea behind the proposed method is to implement combinational circuits using a net of finite state machines (FSM) instead. The application of functional decomposition method reduces the utilization of resources by implementing FSMs using both EMBs and LUT-based programmable logic blocks available in contemporary FPGAs. Experimental results for the proposed method are also shown. A comparison with another dedicated method yields extremely encouraging results: with a comparable number of EMBs, the number of logic cells has been reduced by 95%.
{"title":"Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories","authors":"G. Borowik, T. Luba, B. Falkowski","doi":"10.1109/DDECS.2009.5012135","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012135","url":null,"abstract":"This paper presents a new cost-efficient realization scheme of pattern matching circuits in FPGA structures with embedded memory blocks (EMB). The general idea behind the proposed method is to implement combinational circuits using a net of finite state machines (FSM) instead. The application of functional decomposition method reduces the utilization of resources by implementing FSMs using both EMBs and LUT-based programmable logic blocks available in contemporary FPGAs. Experimental results for the proposed method are also shown. A comparison with another dedicated method yields extremely encouraging results: with a comparable number of EMBs, the number of logic cells has been reduced by 95%.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"81 1","pages":"230-233"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80993411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012123
M. Kubar, O. Subrt, P. Martínek, J. Jakovenko
This paper deals with the ADC non-linearity extraction using a newly developed Virtual Testing Environment (VTE). The VTE proposed is built on Verilog-A implementation of the Servo-Loop unit fully integrated into Cadence design environment. The Servo-Loop method used is aimed at the nonlinearity extraction of static ADC transfer curve; in this paper, we prove an advanced Servo-Loop version focusing on behavioral and transistor-level example of the Residual Signed Digit (RSD) cyclic A/D converter design. Powerful capabilities of the proposed VTE were successfully confirmed by a large set of behavioral and transistor-level simulations in Spectre.
{"title":"Experience in Virtual Testing of RSD cyclic A/D converters","authors":"M. Kubar, O. Subrt, P. Martínek, J. Jakovenko","doi":"10.1109/DDECS.2009.5012123","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012123","url":null,"abstract":"This paper deals with the ADC non-linearity extraction using a newly developed Virtual Testing Environment (VTE). The VTE proposed is built on Verilog-A implementation of the Servo-Loop unit fully integrated into Cadence design environment. The Servo-Loop method used is aimed at the nonlinearity extraction of static ADC transfer curve; in this paper, we prove an advanced Servo-Loop version focusing on behavioral and transistor-level example of the Residual Signed Digit (RSD) cyclic A/D converter design. Powerful capabilities of the proposed VTE were successfully confirmed by a large set of behavioral and transistor-level simulations in Spectre.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"202 1","pages":"178-181"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78760094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012114
M. Rozkovec, O. Novák
We present a new concept of the test method for FPGA devices. Instead of being focused on structural test of the device, the method tests logic and interconnection resources of the FPGA, that are actually used by implemented circuit. The method is based on reconfiguration ability of nowadays FPGAs and utilizes test vectors originally created for ASIC circuits. We present an idea of circuit partitioning and a transcription scheme, that converts the FPGA netlist to the ASIC one. Preliminary results of test patterns efficiency on transformed benchmark circuits are presented.
{"title":"Structural test of programmed FPGA circuits","authors":"M. Rozkovec, O. Novák","doi":"10.1109/DDECS.2009.5012114","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012114","url":null,"abstract":"We present a new concept of the test method for FPGA devices. Instead of being focused on structural test of the device, the method tests logic and interconnection resources of the FPGA, that are actually used by implemented circuit. The method is based on reconfiguration ability of nowadays FPGAs and utilizes test vectors originally created for ASIC circuits. We present an idea of circuit partitioning and a transcription scheme, that converts the FPGA netlist to the ASIC one. Preliminary results of test patterns efficiency on transformed benchmark circuits are presented.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"52 1","pages":"136-139"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85128899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012112
K. Asada, Takuzo Sogabe, T. Nakura, M. Ikeda
We have compared the power supply noise tolerance of a synchronous processor and a self-timed processor fabricated using 0.18µm CMOS. We have designed the self-timed processor using the same RTL as the synchronous processor, and translated it into a netlist with DCVSL circuits and completion logic trees. We have demonstrated the synchronous processor shows an error rate of 9.3% for the worst power supply noise in case of 10% timing margin design. On the other hand, the self-timed processor shows 40% speed degradation, but no error, for the same power supply noise.
{"title":"Measurement of power supply noise tolerance of self-timed processor","authors":"K. Asada, Takuzo Sogabe, T. Nakura, M. Ikeda","doi":"10.1109/DDECS.2009.5012112","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012112","url":null,"abstract":"We have compared the power supply noise tolerance of a synchronous processor and a self-timed processor fabricated using 0.18µm CMOS. We have designed the self-timed processor using the same RTL as the synchronous processor, and translated it into a netlist with DCVSL circuits and completion logic trees. We have demonstrated the synchronous processor shows an error rate of 9.3% for the worst power supply noise in case of 10% timing margin design. On the other hand, the self-timed processor shows 40% speed degradation, but no error, for the same power supply noise.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"15 1","pages":"128-131"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87574023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012143
Flavius Opritoiu, M. Vladutiu, M. Udrescu, L. Prodan
This paper presents a hardware architecture for online self-test in the context of Advanced Encryption Standard (AES). From the available range of techniques and solutions to be considered for increasing Built In Self-Test (BIST) capabilities, for various reasons - especially due to area requirements - we focused on parity control methods. Therefore, the paper presents a general solution proposing both a basic architecture and a new project designed at the gate level that relies on parity prediction techniques. The contribution brought by our architecture consists of a complete separation between the functional and test channels. The conclusive arguments reveal the proposed architecture as a solution for area reduction; performance and power consumption are also analyzed.
{"title":"Round-level concurrent error detection applied to Advanced Encryption Standard","authors":"Flavius Opritoiu, M. Vladutiu, M. Udrescu, L. Prodan","doi":"10.1109/DDECS.2009.5012143","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012143","url":null,"abstract":"This paper presents a hardware architecture for online self-test in the context of Advanced Encryption Standard (AES). From the available range of techniques and solutions to be considered for increasing Built In Self-Test (BIST) capabilities, for various reasons - especially due to area requirements - we focused on parity control methods. Therefore, the paper presents a general solution proposing both a basic architecture and a new project designed at the gate level that relies on parity prediction techniques. The contribution brought by our architecture consists of a complete separation between the functional and test channels. The conclusive arguments reveal the proposed architecture as a solution for area reduction; performance and power consumption are also analyzed.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"77 1","pages":"270-275"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88558153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012101
I. Lemberski, P. Fiser
We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints. The logic is implemented as a minimized AND-OR structure, together with the completion detection logic. We formulated and proved the product term minimization constraint that ensures a correct logic behavior. We processed the MCNC benchmarks and generated asynchronous two-level logic. The implementation complexity was compared with the state-of-the-art approach. Using our approach, we achieved a significant improvement.
{"title":"Asynchronous two-level logic of reduced cost","authors":"I. Lemberski, P. Fiser","doi":"10.1109/DDECS.2009.5012101","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012101","url":null,"abstract":"We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints. The logic is implemented as a minimized AND-OR structure, together with the completion detection logic. We formulated and proved the product term minimization constraint that ensures a correct logic behavior. We processed the MCNC benchmarks and generated asynchronous two-level logic. The implementation complexity was compared with the state-of-the-art approach. Using our approach, we achieved a significant improvement.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"42 1","pages":"68-73"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75396007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012089
F. A. Parsan, A. Ayatollahi, A. Abrishamifar
Effect of asymmetric operating condition of depletion-mode MOS capacitors on the linearity of MOSFET-only switched-capacitor ΔΣ modulators is investigated. In very low-voltage switched-capacitor circuits the opamp input and output common-mode levels are separated to provide maximum overdrive voltage for MOS switches. This causes an asymmetric voltage drop on capacitors during operation. On the other hand, the depletion-mode MOS capacitors are most linear when operated under a symmetric condition. The effect of this increased nonlinearity on a ΔΣ modulator which is operated under an asymmetric condition is simulated and the results are compared with a ΔΣ modulator which is operated under a symmetric condition.
{"title":"Investigating the linearity of MOSFET-only switched-capacitor ΔΣ modulators under low-voltage condition","authors":"F. A. Parsan, A. Ayatollahi, A. Abrishamifar","doi":"10.1109/DDECS.2009.5012089","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012089","url":null,"abstract":"Effect of asymmetric operating condition of depletion-mode MOS capacitors on the linearity of MOSFET-only switched-capacitor ΔΣ modulators is investigated. In very low-voltage switched-capacitor circuits the opamp input and output common-mode levels are separated to provide maximum overdrive voltage for MOS switches. This causes an asymmetric voltage drop on capacitors during operation. On the other hand, the depletion-mode MOS capacitors are most linear when operated under a symmetric condition. The effect of this increased nonlinearity on a ΔΣ modulator which is operated under an asymmetric condition is simulated and the results are compared with a ΔΣ modulator which is operated under a symmetric condition.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"9 1","pages":"12-15"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79110923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012090
J. Brenkus, V. Stopjaková, Ronny Vanhooren, A. Chichkov
An experiment comparing the efficiency of different test strategies on a moderate complexity mixed-signal circuit with 1300 nodes is presented. Selected test strategies from the groups of functional, structural and parametric approaches were considered. Bridging faults are taken into account and fault simulations results are shown, where fault coverage, efficiency and quality of the tests are evaluated.
{"title":"Comparison of different test strategies on a mixed-signal circuit","authors":"J. Brenkus, V. Stopjaková, Ronny Vanhooren, A. Chichkov","doi":"10.1109/DDECS.2009.5012090","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012090","url":null,"abstract":"An experiment comparing the efficiency of different test strategies on a moderate complexity mixed-signal circuit with 1300 nodes is presented. Selected test strategies from the groups of functional, structural and parametric approaches were considered. Bridging faults are taken into account and fault simulations results are shown, where fault coverage, efficiency and quality of the tests are evaluated.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"1 1","pages":"16-19"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84746013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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