Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012136
S. Deniziak, R. Tomaszewski
In this paper we present a methodology for custom topology generation, offering low latency and significantly reduced power consumption. The novelty of our approach lies in the objective - we focus on complete elimination of the contention on the links. It is achieved through alternate path generation, insertion of additional links and message scheduling. We also present a novel concept of Message Dependence Graph for traffic analysis. The methodology operates under application and design constraints, producing network topology along with routing paths. Experimental results confirming benefits of the proposed approach are provided.
{"title":"Contention-avoiding custom topology generation for network-on-chip","authors":"S. Deniziak, R. Tomaszewski","doi":"10.1109/DDECS.2009.5012136","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012136","url":null,"abstract":"In this paper we present a methodology for custom topology generation, offering low latency and significantly reduced power consumption. The novelty of our approach lies in the objective - we focus on complete elimination of the contention on the links. It is achieved through alternate path generation, insertion of additional links and message scheduling. We also present a novel concept of Message Dependence Graph for traffic analysis. The methodology operates under application and design constraints, producing network topology along with routing paths. Experimental results confirming benefits of the proposed approach are provided.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"22 1","pages":"234-237"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80117077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012120
T. Rudnicki, T. Garbolino, K. Gucwa, A. Hlawiczka
The paper is devoted to a test-per-clock method of an length.
本文研究了一种长度为一个时钟的测试方法。
{"title":"Effective BIST for crosstalk faults in interconnects","authors":"T. Rudnicki, T. Garbolino, K. Gucwa, A. Hlawiczka","doi":"10.1109/DDECS.2009.5012120","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012120","url":null,"abstract":"The paper is devoted to a test-per-clock method of an length.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"6 1","pages":"164-169"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88891609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012105
Tomáš Martínek, Jan Vozenilek, M. Lexa
Understanding the structure and function of DNA sequences represents an important area of research in modern biology. One of the interesting structures occurring in DNA is a palindrome. Biologists believe that palindromes play an important role in regulation of gene activity and other cell processes because they are often observed near promoters, introns and specific untranslated regions. Unfortunately, the time complexity of algorithms for palindrome detection increases when mutations in the form of character insertions, deletions or substitutions are taken into consideration. In recent years, several works have been aimed at acceleration of such algorithms using dedicated circuits capable of potentially large-scale searching. However, widespread use of such circuits is often complicated by varying user task details or the need to use a specific target platform. The objective of this work is therefore to create a model of hardware architecture for approximate palindrome detection and develop a technique for automatic mapping of this model to the target platform without intervention of an experienced designer. The proposed model and the mapping technique are implemented and evaluated on a family of chips with Virtex5 technology.
{"title":"Architecture model for approximate palindrome detection","authors":"Tomáš Martínek, Jan Vozenilek, M. Lexa","doi":"10.1109/DDECS.2009.5012105","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012105","url":null,"abstract":"Understanding the structure and function of DNA sequences represents an important area of research in modern biology. One of the interesting structures occurring in DNA is a palindrome. Biologists believe that palindromes play an important role in regulation of gene activity and other cell processes because they are often observed near promoters, introns and specific untranslated regions. Unfortunately, the time complexity of algorithms for palindrome detection increases when mutations in the form of character insertions, deletions or substitutions are taken into consideration. In recent years, several works have been aimed at acceleration of such algorithms using dedicated circuits capable of potentially large-scale searching. However, widespread use of such circuits is often complicated by varying user task details or the need to use a specific target platform. The objective of this work is therefore to create a model of hardware architecture for approximate palindrome detection and develop a technique for automatic mapping of this model to the target platform without intervention of an experienced designer. The proposed model and the mapping technique are implemented and evaluated on a family of chips with Virtex5 technology.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"13 1","pages":"90-95"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87301020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012111
M. Donoval, M. Daricek, J. Marek, V. Stopjaková
Power devices current sensors based on magnetic force of is presented. The proposed sensors are aimed to be used for switched current testing in power devices with high switched currents above amperes. The advantage of the proposed monitors is in elimination of the undesired voltage reduction and compatibility with the power device control electronics. Description of horizontal and novel vertical magnetic sensors architectures, designs and physical implementations on chip are presented. Several sensor versions were designed in 1.0 µm BiCMOS technology.
{"title":"Power devices current monitoring using horizontal and vertical magnetic force sensor","authors":"M. Donoval, M. Daricek, J. Marek, V. Stopjaková","doi":"10.1109/DDECS.2009.5012111","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012111","url":null,"abstract":"Power devices current sensors based on magnetic force of is presented. The proposed sensors are aimed to be used for switched current testing in power devices with high switched currents above amperes. The advantage of the proposed monitors is in elimination of the undesired voltage reduction and compatibility with the power device control electronics. Description of horizontal and novel vertical magnetic sensors architectures, designs and physical implementations on chip are presented. Several sensor versions were designed in 1.0 µm BiCMOS technology.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"58 1","pages":"124-127"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81752546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012088
T. Koal, Daniel Scheit, H. Vierhaus
Technology forecasts concerning the development of CMOS technologies predict a higher level of intermittent faults due to radiation effects, but also a higher density of permanent fault effects due to inevitable parameter shifts and higher stress factors. For high production yield and long-term dependable operation, mechanisms of built-in self repair that can be used after production test and in the field of application are becoming a must. The architecture introduced in this paper includes mechanisms for logic self repair that may also cover local interconnects.
{"title":"A scheme of logic self repair including local interconnects","authors":"T. Koal, Daniel Scheit, H. Vierhaus","doi":"10.1109/DDECS.2009.5012088","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012088","url":null,"abstract":"Technology forecasts concerning the development of CMOS technologies predict a higher level of intermittent faults due to radiation effects, but also a higher density of permanent fault effects due to inevitable parameter shifts and higher stress factors. For high production yield and long-term dependable operation, mechanisms of built-in self repair that can be used after production test and in the field of application are becoming a must. The architecture introduced in this paper includes mechanisms for logic self repair that may also cover local interconnects.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"29 1","pages":"8-11"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83732841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012095
S. Kolodzinski, E. Hrynkiewicz
The paper deals with the problems of input variables assigning to the free and bounded sets during logic function decomposition. The Ashenhurst decomposition is considered with respect to implementation of logic functions in LUT based FPGA. The method of finding profitable input variables partitioning is based on utilisation of Logic Differential Calculus. The elaborated method is very convenient especially if decomposition is carried out in Reed-Muller spectral domain because the Boolean differentials are easy calculated from Reed-Muller form of logic function which is simply calculated as reverse Reed-Muller transform. The obtained results are very promising.
{"title":"An utilisation of Boolean differential calculus in variables partition calculation for decomposition of logic functions","authors":"S. Kolodzinski, E. Hrynkiewicz","doi":"10.1109/DDECS.2009.5012095","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012095","url":null,"abstract":"The paper deals with the problems of input variables assigning to the free and bounded sets during logic function decomposition. The Ashenhurst decomposition is considered with respect to implementation of logic functions in LUT based FPGA. The method of finding profitable input variables partitioning is based on utilisation of Logic Differential Calculus. The elaborated method is very convenient especially if decomposition is carried out in Reed-Muller spectral domain because the Boolean differentials are easy calculated from Reed-Muller form of logic function which is simply calculated as reverse Reed-Muller transform. The obtained results are very promising.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"51 1","pages":"34-37"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89462027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012106
Petr Kobierský, J. Korenek, Libor Polcák
Packet header analysis and extraction of header fields needs to be performed in all network devices. As network speed is increasing quickly, high speed packet header processing is required. We propose a new architecture of packet header analysis and fields extraction intended for high-speed FPGA-based network applications. The architecture is able to process 20 Gbps network links with less than 12 percent of available resources of Virtex 5 110 FPGA. Moreover, the presented solution can balance between network throughput and consumed hardware resources to fit application needs. The architecture for packet header processing is generated from standard XML protocol scheme and is strongly optimised for resource consumption and speed by an automatic HDL code generator. Our solution also enables to change the set of extracted header fields on-line without FPGA reconfiguration.
{"title":"Packet header analysis and field extraction for multigigabit networks","authors":"Petr Kobierský, J. Korenek, Libor Polcák","doi":"10.1109/DDECS.2009.5012106","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012106","url":null,"abstract":"Packet header analysis and extraction of header fields needs to be performed in all network devices. As network speed is increasing quickly, high speed packet header processing is required. We propose a new architecture of packet header analysis and fields extraction intended for high-speed FPGA-based network applications. The architecture is able to process 20 Gbps network links with less than 12 percent of available resources of Virtex 5 110 FPGA. Moreover, the presented solution can balance between network throughput and consumed hardware resources to fit application needs. The architecture for packet header processing is generated from standard XML protocol scheme and is strongly optimised for resource consumption and speed by an automatic HDL code generator. Our solution also enables to change the set of extracted header fields on-line without FPGA reconfiguration.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"29 3 1","pages":"96-101"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87998767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012097
Davide Bresolin, G. D. Guglielmo, F. Fummi, G. Pravadelli, T. Villa
The effectiveness and the efficiency of functional ATPGs based on deterministic strategies is influenced by the computational model adopted to represent the design under test. In this context the extended finite state machine (EFSM) is a valuable model which reduces the risk of state explosion preserving relevant features of more traditional FSMs. This paper. defines a particular variant of EFSMs to manage properly both synchronous and asynchronous modules in a uniform way, and then it proposes theoretical basis to perform their composition by bounding state and transition growth. The aim of composition is to improve functional ATPG whose effectiveness and efficiency may be limited when separate EFSMs are used to model the design under test. Experimental results confirm this conjecture.
{"title":"The impact of EFSM composition on functional ATPG","authors":"Davide Bresolin, G. D. Guglielmo, F. Fummi, G. Pravadelli, T. Villa","doi":"10.1109/DDECS.2009.5012097","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012097","url":null,"abstract":"The effectiveness and the efficiency of functional ATPGs based on deterministic strategies is influenced by the computational model adopted to represent the design under test. In this context the extended finite state machine (EFSM) is a valuable model which reduces the risk of state explosion preserving relevant features of more traditional FSMs. This paper. defines a particular variant of EFSMs to manage properly both synchronous and asynchronous modules in a uniform way, and then it proposes theoretical basis to perform their composition by bounding state and transition growth. The aim of composition is to improve functional ATPG whose effectiveness and efficiency may be limited when separate EFSMs are used to model the design under test. Experimental results confirm this conjecture.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"21 1","pages":"44-49"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88539946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012142
Y. Benabboud, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, L. Bouzaida, I. Izaute
This paper presents a logic diagnosis approach targeting bridging faults. The proposed approach is performed in two phases, (i) a fault localization phase based on the Single-Location-at-A-Time (SLAT) paradigm determining a set of suspects, and (ii) a fault model allocation phase associating a set of fault models to each suspect identified during the first phase. The main advantages of this approach are that the fault localization phase is fault model independent, and that the fault model allocation phase is able to deal at the same time with several bridging fault models leading to either static or dynamic faulty behaviors. Experimental results on full scan circuits show the diagnosis accuracy of the proposed approach in terms of absolute number of suspects. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.
{"title":"Comprehensive bridging fault diagnosis based on the SLAT paradigm","authors":"Y. Benabboud, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, L. Bouzaida, I. Izaute","doi":"10.1109/DDECS.2009.5012142","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012142","url":null,"abstract":"This paper presents a logic diagnosis approach targeting bridging faults. The proposed approach is performed in two phases, (i) a fault localization phase based on the Single-Location-at-A-Time (SLAT) paradigm determining a set of suspects, and (ii) a fault model allocation phase associating a set of fault models to each suspect identified during the first phase. The main advantages of this approach are that the fault localization phase is fault model independent, and that the fault model allocation phase is able to deal at the same time with several bridging fault models leading to either static or dynamic faulty behaviors. Experimental results on full scan circuits show the diagnosis accuracy of the proposed approach in terms of absolute number of suspects. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"2028 1","pages":"264-269"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91318264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012099
Padmanabhan Balasubramanian, Doug Edwards, C. Brej
Self-timed full adder designs based on commercial synchronous resources (standard cells), constructed using a mix of complete delay-insensitive codes adopted for inputs are described in this paper. While one of the adder designs incorporates redundancy into the logic, the other design does not. Comparisons have been carried out with respect to various self-timed full adder designs which employ only a single widely used delay-insensitive input encoding for both the inputs and outputs. It has been found out from exhaustive simulations that incorporating redundancy into the logic actually benefits in terms of delay, but a non-redundant implementation proves to be beneficial with respect to power and area parameters.
{"title":"Self-timed full adder designs based on hybrid input encoding","authors":"Padmanabhan Balasubramanian, Doug Edwards, C. Brej","doi":"10.1109/DDECS.2009.5012099","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012099","url":null,"abstract":"Self-timed full adder designs based on commercial synchronous resources (standard cells), constructed using a mix of complete delay-insensitive codes adopted for inputs are described in this paper. While one of the adder designs incorporates redundancy into the logic, the other design does not. Comparisons have been carried out with respect to various self-timed full adder designs which employ only a single widely used delay-insensitive input encoding for both the inputs and outputs. It has been found out from exhaustive simulations that incorporating redundancy into the logic actually benefits in terms of delay, but a non-redundant implementation proves to be beneficial with respect to power and area parameters.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"25 1","pages":"56-61"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87305168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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