Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117258
Sheng-Ren Chiu, Chung-Yang Sue, Lu-Pu Liao, Li-Tao Teng, Y. Hsu, Y. Su
This paper presents an all-in-one fully integrated circuit solution for a vibrating micro-electromechanical gyroscope system using standard 0.25um 1P5M low voltage CMOS process. The analog parts of the system include a trans-impedance amplifier (TIA) with adaptive gain control (AGC) for the resonator driving loop, a sigma-delta modulator with gain/offset trimming function for the Coriolis signal read-out and a modified all PMOS charge pump for the high DC voltage. The digital signal processing parts include a trimming/control logic circuit and an I2C interface. SOG-bulk micromachining and deep reactive ion etching (DRIE) are adopted to fabricate the gyroscope sensor element with high aspect-ratio sensing structure and high yield. The experimental results indicate that the noise floor achieves 0.051° / s/ √Hz and the scale factor is 7mV/ °/s of the proposed two chip MEMS gyroscope system.
本文提出了一种采用标准0.25um 1P5M低压CMOS工艺的振动微机电陀螺仪系统的一体化全集成电路方案。该系统的模拟部分包括用于谐振器驱动回路的具有自适应增益控制(AGC)的反阻抗放大器(TIA)，用于科里奥利信号读出的具有增益/失调调节功能的sigma-delta调制器，以及用于高直流电压的改进的全PMOS电荷泵。数字信号处理部分包括微调/控制逻辑电路和I2C接口。采用SOG-bulk微加工和深度反应离子刻蚀(deep reactive ion etching, DRIE)技术制备了具有高宽高比传感结构和高成品率的陀螺仪传感器元件。实验结果表明，所设计的双芯片MEMS陀螺仪系统的本底噪声达到0.051°/s /√Hz，比例因子为7mV/°/s。
{"title":"A fully integrated circuit for MEMS vibrating gyroscope using standard 0.25um CMOS process","authors":"Sheng-Ren Chiu, Chung-Yang Sue, Lu-Pu Liao, Li-Tao Teng, Y. Hsu, Y. Su","doi":"10.1109/IMPACT.2011.6117258","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117258","url":null,"abstract":"This paper presents an all-in-one fully integrated circuit solution for a vibrating micro-electromechanical gyroscope system using standard 0.25um 1P5M low voltage CMOS process. The analog parts of the system include a trans-impedance amplifier (TIA) with adaptive gain control (AGC) for the resonator driving loop, a sigma-delta modulator with gain/offset trimming function for the Coriolis signal read-out and a modified all PMOS charge pump for the high DC voltage. The digital signal processing parts include a trimming/control logic circuit and an I2C interface. SOG-bulk micromachining and deep reactive ion etching (DRIE) are adopted to fabricate the gyroscope sensor element with high aspect-ratio sensing structure and high yield. The experimental results indicate that the noise floor achieves 0.051° / s/ √Hz and the scale factor is 7mV/ °/s of the proposed two chip MEMS gyroscope system.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"50 1","pages":"315-318"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91137848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117283
Pei-Chi Chen, Yen-Fu Su, Shin-Yueh Yang, K. Chiang
Three-dimensional chip stacking packaging has become increasingly popular in the electronic packaging industry because of the present market demand on high performance, high capacity and small form factor products. As a result, silicon wafers have to be ground through wafer-thinning processes to achieve greater packaging density. However, induction of cracks on the chips during stacking process or with the use of a device is possible. Therefore, the current research aims to determine the maximum allowable force on a (1 0 0) silicon die using ball-breaker test with an acoustic emission (AE) system. To compare with the experiment data, the finite element analysis was employed using commercial software ANSYS/LS-DYNA3D® to determine the silicon die strength. The results show that the maximum allowable force for a 30 mm × 30 mm × 0.2 mm (1 0 0) silicon is 14.42 N. The value was introduced to simulation to determine the strength of silicon die. The strength of silicon die is 618 MPa, which is lower than that obtained from a previous research that conducted the ball-breaker test without an AE system, the allowable strength is defined as when silicon is fully cracked. The advantage of the method developed in this research is the AE system could detect the failure instantly and obtain the event of initial cracking. The modified ball-breaker test could avoid an overestimation in determining the die strength.
由于目前市场对高性能、高容量和小尺寸产品的需求，三维芯片堆叠封装在电子封装行业越来越受欢迎。因此，硅片必须通过晶圆减薄工艺进行研磨，以实现更大的封装密度。然而，在堆叠过程中或使用设备时，芯片上可能会产生裂纹。因此，本研究的目的是利用声发射(AE)系统的破球试验来确定(1 0 0)硅模上的最大允许力。为了与实验数据进行比较，利用商业软件ANSYS/LS-DYNA3D®进行有限元分析，确定硅模强度。结果表明，30 mm × 30 mm × 0.2 mm(1 0 0)硅的最大许用力为14.42 n。硅模强度为618 MPa，低于前人在无声发射系统下进行破球试验所得强度，允许强度定义为硅完全开裂时的强度。该方法的优点是声发射系统可以即时检测到破坏并获得初始开裂事件。改进的破球试验可以避免在确定模具强度时高估。
{"title":"Determination of silicon die initial crack using acoustic emission technique","authors":"Pei-Chi Chen, Yen-Fu Su, Shin-Yueh Yang, K. Chiang","doi":"10.1109/IMPACT.2011.6117283","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117283","url":null,"abstract":"Three-dimensional chip stacking packaging has become increasingly popular in the electronic packaging industry because of the present market demand on high performance, high capacity and small form factor products. As a result, silicon wafers have to be ground through wafer-thinning processes to achieve greater packaging density. However, induction of cracks on the chips during stacking process or with the use of a device is possible. Therefore, the current research aims to determine the maximum allowable force on a (1 0 0) silicon die using ball-breaker test with an acoustic emission (AE) system. To compare with the experiment data, the finite element analysis was employed using commercial software ANSYS/LS-DYNA3D® to determine the silicon die strength. The results show that the maximum allowable force for a 30 mm × 30 mm × 0.2 mm (1 0 0) silicon is 14.42 N. The value was introduced to simulation to determine the strength of silicon die. The strength of silicon die is 618 MPa, which is lower than that obtained from a previous research that conducted the ball-breaker test without an AE system, the allowable strength is defined as when silicon is fully cracked. The advantage of the method developed in this research is the AE system could detect the failure instantly and obtain the event of initial cracking. The modified ball-breaker test could avoid an overestimation in determining the die strength.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"66 1","pages":"83-86"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90363368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117241
E. So, Albert Lan, C. Hsiao, Daniel Yu, Nistec Chang, F. Kao
As for mainstream portable application (Mobile Phone, Tablet, Handset Gamer), the higher density (array IO pitch <= 100um), higher thermal performance (better theta JA than overmold FCCSP) and lower profile (compare with overmold FCCSP) is necessary for package developing. As to satisfy the marketing needs, some suitable solution can be considered: Utilize Cu Pillar Bump to satisfy the fine pitch request; and also with the exposed die FCCSP to cover the lower profile & better thermal performance. As to come out an easy way to recognize the package type of this combination, the package type of “sFCCSP” (SPIL proposed FCCSP-Exposed Die Cu Pillar FCCSP) had be called for further discussion. In general, Cu Pillar was the fine pitch solution of FCCSP (<130um bump pitch), as the next generation of low IO(<200) application flip chip solution, Cu Pillar can provide a feasibility for better electrical performance but reasonable cost (design-in is necessary), and upcoming challenge is the ELK protection for 40nm / 28nm even finer IC technology. As regard the exposed die FC solution, it is obvious to realize the benefit of skipping overmold 60∼80um thickness for package total height reduction. Of course, the trade-off is either back side surface bleeding or package warpage. In this report, there is a test vehicle to show how we overcome the potential ELK crack & Die bleeding & package warpage issue to approach the mainstream technology for portable market.
对于主流便携式应用(手机、平板电脑、手机游戏)来说，更高的密度(阵列IO间距<= 100um)、更高的热性能(θ JA优于上模FCCSP)和更低的轮廓(与上模FCCSP相比)是开发封装所必需的。为了满足市场的需求，可以考虑一些合适的解决方案:利用铜柱凸点来满足细间距的要求;以及外露的FCCSP芯片，以覆盖更低的轮廓和更好的热性能。为了提出一种简单的方法来识别这种组合的封装类型，“sFCCSP”的封装类型(SPIL提议的FCCSP- exposed Die Cu Pillar FCCSP)被要求进一步讨论。总的来说，Cu柱是FCCSP (<130um凸距)的细间距解决方案，作为下一代低IO(<200)应用倒装芯片解决方案，Cu柱可以提供更好的电气性能的可行性，但成本合理(设计- In是必要的)，而即将到来的挑战是40nm / 28nm更细的IC技术的ELK保护。对于外露模FC解决方案，很明显可以实现跳过模具60 ~ 80um厚度以降低封装总高度的好处。当然，代价要么是背面表面出血，要么是包装翘曲。在本报告中，有一个测试车辆来展示我们如何克服潜在的ELK裂纹和模具出血和封装翘曲问题，以接近便携式市场的主流技术。
{"title":"A introduction of sFCCSP — Fine pitch low profile FCCSP solution","authors":"E. So, Albert Lan, C. Hsiao, Daniel Yu, Nistec Chang, F. Kao","doi":"10.1109/IMPACT.2011.6117241","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117241","url":null,"abstract":"As for mainstream portable application (Mobile Phone, Tablet, Handset Gamer), the higher density (array IO pitch <= 100um), higher thermal performance (better theta JA than overmold FCCSP) and lower profile (compare with overmold FCCSP) is necessary for package developing. As to satisfy the marketing needs, some suitable solution can be considered: Utilize Cu Pillar Bump to satisfy the fine pitch request; and also with the exposed die FCCSP to cover the lower profile & better thermal performance. As to come out an easy way to recognize the package type of this combination, the package type of “sFCCSP” (SPIL proposed FCCSP-Exposed Die Cu Pillar FCCSP) had be called for further discussion. In general, Cu Pillar was the fine pitch solution of FCCSP (<130um bump pitch), as the next generation of low IO(<200) application flip chip solution, Cu Pillar can provide a feasibility for better electrical performance but reasonable cost (design-in is necessary), and upcoming challenge is the ELK protection for 40nm / 28nm even finer IC technology. As regard the exposed die FC solution, it is obvious to realize the benefit of skipping overmold 60∼80um thickness for package total height reduction. Of course, the trade-off is either back side surface bleeding or package warpage. In this report, there is a test vehicle to show how we overcome the potential ELK crack & Die bleeding & package warpage issue to approach the mainstream technology for portable market.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"44 1","pages":"126-128"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90391613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117171
T. Tomimura, M. Ishizuka
Related to the thermal contact resistance, lots of studies have been done on the thermal constriction resistance, which is a measure of the additional temperature drop at the contact interface [1]. And almost all of those studies have been conducted based on the two-dimensional cylindrical coordinates system. In the same way, the additional thermal resistance associated with the geometrical constriction is often encountered in the electronic components like relay circuits, the printed circuit boards, and so on. In these cases, however, heat is frequently transferred through a thin and narrow passage, which should be treated by two-dimensional rectangular coordinates system.
{"title":"Estimation of thermal constriction resistance for simple thermal network analysis of electronic components","authors":"T. Tomimura, M. Ishizuka","doi":"10.1109/IMPACT.2011.6117171","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117171","url":null,"abstract":"Related to the thermal contact resistance, lots of studies have been done on the thermal constriction resistance, which is a measure of the additional temperature drop at the contact interface [1]. And almost all of those studies have been conducted based on the two-dimensional cylindrical coordinates system. In the same way, the additional thermal resistance associated with the geometrical constriction is often encountered in the electronic components like relay circuits, the printed circuit boards, and so on. In these cases, however, heat is frequently transferred through a thin and narrow passage, which should be treated by two-dimensional rectangular coordinates system.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"43 1","pages":"246-248"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88054503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117204
Jung-Chang Wang, Wei-Jui Chen
The vapor chamber has been verified the excellent heat transfer efficiency and heat spreading performance utilized particularly in many high-power and small area heat sources. This paper analyzes and compares the thermal performance of a vapor chamber-based thermal module with a traditional Cu metal based plate embedded three heat pipes of 6 mm diameter at high heat flux GPU above 165 Watt. They are estimated and simulated the optimum fin design of aluminum heat sink through computational numerical method and thermal resistance analysis at constant P-Q performance curve of a same commercial blower. These results show that the total thermal resistance value of vapor chamber-based thermal module are under 0.273 °C/W from simulation analytical data and that of heat-pipes and copper based plate thermal module are all over 0.273 °C/W. Therefore, the thermal performance of vapor chamber-based thermal module can be accurately simulated and analyzed by applying the method introduced in this paper. The vapor chamber-based thermal module can achieve the optimum thermal performance and the critical heat flux may exceed 100 Watt/cm2. Consequently, the vapor chamber-based thermal module introduced in this paper is able to cope with future GPU named RV 970 and GTX 590 with high heat flux of more than 60 Watt/cm2.
{"title":"Vapor chamber in high-end VGA card","authors":"Jung-Chang Wang, Wei-Jui Chen","doi":"10.1109/IMPACT.2011.6117204","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117204","url":null,"abstract":"The vapor chamber has been verified the excellent heat transfer efficiency and heat spreading performance utilized particularly in many high-power and small area heat sources. This paper analyzes and compares the thermal performance of a vapor chamber-based thermal module with a traditional Cu metal based plate embedded three heat pipes of 6 mm diameter at high heat flux GPU above 165 Watt. They are estimated and simulated the optimum fin design of aluminum heat sink through computational numerical method and thermal resistance analysis at constant P-Q performance curve of a same commercial blower. These results show that the total thermal resistance value of vapor chamber-based thermal module are under 0.273 °C/W from simulation analytical data and that of heat-pipes and copper based plate thermal module are all over 0.273 °C/W. Therefore, the thermal performance of vapor chamber-based thermal module can be accurately simulated and analyzed by applying the method introduced in this paper. The vapor chamber-based thermal module can achieve the optimum thermal performance and the critical heat flux may exceed 100 Watt/cm2. Consequently, the vapor chamber-based thermal module introduced in this paper is able to cope with future GPU named RV 970 and GTX 590 with high heat flux of more than 60 Watt/cm2.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"105 1","pages":"393-396"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86944061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117273
Ray-Hwa Wong, Mingfang Li, Ying T. Wang
In the vision based control system, the lower frame per second and the delay of image processes are main reasons to degrade the control performance. These factors have no significant influence in the low frequency material testing. In experiments, vision based electro-hydraulic material testing machine is developed by self-organizing sliding mode fuzzy controller and to carry out dynamic tracking control under 1Hz. Square, sinusoidal and triangular waveforms are applied to analyze the control performance of this electro hydraulic testing machine, and then it will discuss the feasibility of non-contacted CCD camera to replace contacted sensors.
{"title":"A vision based low-frequency electro-hydraulic fatigue testing machine","authors":"Ray-Hwa Wong, Mingfang Li, Ying T. Wang","doi":"10.1109/IMPACT.2011.6117273","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117273","url":null,"abstract":"In the vision based control system, the lower frame per second and the delay of image processes are main reasons to degrade the control performance. These factors have no significant influence in the low frequency material testing. In experiments, vision based electro-hydraulic material testing machine is developed by self-organizing sliding mode fuzzy controller and to carry out dynamic tracking control under 1Hz. Square, sinusoidal and triangular waveforms are applied to analyze the control performance of this electro hydraulic testing machine, and then it will discuss the feasibility of non-contacted CCD camera to replace contacted sensors.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"31 1","pages":"307-310"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78403623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117217
M. Hsieh, Chien-Chen Lee, Li Chiun Hung, V. Wang, Harry Perng
The pre-solder crack phenomenon after thermal cycling test is observed in 28nm extreme low-k (ELK) large die fcBGA (flip chip ball grid array), which may come from the resulted critical stresses in IMC (intermetallic compounds) on Cu pad layer. For the purpose of realizing the thermal-mechanical stress distributions in 28nm ELK large die fcBGA, a comprehensive study for the effects of package geometry is investigated by using three-dimensional finite element analyses (FEA) in this paper. The effects of under bump metallurgy (UBM) size, solder resistant opening (SRO) size, solder bump dimension, thermal interface material (TIM) thickness, Cu pad diameter, substrate thickness and its coefficient of thermal expansion (CTE) are discussed by Taguchi L16(27) methodology to figure out the most significant factors. Through the statistical results, it is found that the factors of UBM size, SRO size and Cu pad diameter had significant contributions to stress responses. The most important parameters of UBM and SRO size ratio (UBM/SRO) as well as Cu pad diameter and SRO size ratio (pad/SRO) that comprehend the corresponding stress responses are captured by using response surface methodology (RSM). To have further discussions of these significant factors, dissections for UBM, SRO and polyimide (PI) opening size are also illustrated. The simulated results can be good references and effectively served as design guidelines to avoid the critical stresses as well as enhance the reliability in 28nm ELK large die fcBGA.
{"title":"Thermo-mechanical stress analysis and optimization for 28nm extreme low-k large die fcBGA","authors":"M. Hsieh, Chien-Chen Lee, Li Chiun Hung, V. Wang, Harry Perng","doi":"10.1109/IMPACT.2011.6117217","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117217","url":null,"abstract":"The pre-solder crack phenomenon after thermal cycling test is observed in 28nm extreme low-k (ELK) large die fcBGA (flip chip ball grid array), which may come from the resulted critical stresses in IMC (intermetallic compounds) on Cu pad layer. For the purpose of realizing the thermal-mechanical stress distributions in 28nm ELK large die fcBGA, a comprehensive study for the effects of package geometry is investigated by using three-dimensional finite element analyses (FEA) in this paper. The effects of under bump metallurgy (UBM) size, solder resistant opening (SRO) size, solder bump dimension, thermal interface material (TIM) thickness, Cu pad diameter, substrate thickness and its coefficient of thermal expansion (CTE) are discussed by Taguchi L16(27) methodology to figure out the most significant factors. Through the statistical results, it is found that the factors of UBM size, SRO size and Cu pad diameter had significant contributions to stress responses. The most important parameters of UBM and SRO size ratio (UBM/SRO) as well as Cu pad diameter and SRO size ratio (pad/SRO) that comprehend the corresponding stress responses are captured by using response surface methodology (RSM). To have further discussions of these significant factors, dissections for UBM, SRO and polyimide (PI) opening size are also illustrated. The simulated results can be good references and effectively served as design guidelines to avoid the critical stresses as well as enhance the reliability in 28nm ELK large die fcBGA.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"108 1","pages":"411-414"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80719671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117183
C. Yuan, R. Kregting, H. Ye, W. V. van Driel, S. Gielen, G. Zhang
Power electronics, such as high power RF components and high power LEDs, requires the combination of robust and reliable package structures, materials, and processes to guarantee their functional performance and lifetime. We started with the thermal and thermal-mechanical modeling of such component performances. With robust validation. Afterwards, an online testing method, design rules, and new structures/modifications have been implemented to improve the performance and reliability of high power electronics. This paper reviews our efforts on the RF transistors and high power LED's developments.
{"title":"High power electronics package: From modeling to implementation","authors":"C. Yuan, R. Kregting, H. Ye, W. V. van Driel, S. Gielen, G. Zhang","doi":"10.1109/IMPACT.2011.6117183","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117183","url":null,"abstract":"Power electronics, such as high power RF components and high power LEDs, requires the combination of robust and reliable package structures, materials, and processes to guarantee their functional performance and lifetime. We started with the thermal and thermal-mechanical modeling of such component performances. With robust validation. Afterwards, an online testing method, design rules, and new structures/modifications have been implemented to improve the performance and reliability of high power electronics. This paper reviews our efforts on the RF transistors and high power LED's developments.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"446 1","pages":"249-252"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78192675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117256
Kuo-ying Tsai, Shih-chang Ku, W. Chang, H. Tsai
The thermal performance of a specific 3D IC structure — a wide I/O package is investigated with parameterized factors like TSV diameter, material of micro bumps, and TSV allocation strategy. TSV diameter and material of micro bump are found no significant effect on thermal performance of the illustrated wide I/O package. However, the hot spot location is changed by the TSV allocation. The results suggest the better locations for thermal diodes would be close to the TSV or die corners. Also this work concludes that the “TSV peripheral” allocation performs the better cooling than the others.
{"title":"Thermal characterization of a wide I/O 3DIC","authors":"Kuo-ying Tsai, Shih-chang Ku, W. Chang, H. Tsai","doi":"10.1109/IMPACT.2011.6117256","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117256","url":null,"abstract":"The thermal performance of a specific 3D IC structure — a wide I/O package is investigated with parameterized factors like TSV diameter, material of micro bumps, and TSV allocation strategy. TSV diameter and material of micro bump are found no significant effect on thermal performance of the illustrated wide I/O package. However, the hot spot location is changed by the TSV allocation. The results suggest the better locations for thermal diodes would be close to the TSV or die corners. Also this work concludes that the “TSV peripheral” allocation performs the better cooling than the others.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"26 1","pages":"261-264"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81051577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117223
R. Sung, K. Chiang, D. Lee, M. Ma
As the advance of the packaging technology for the electrical consuming demands, it requires for more functions or increasing the density of devices within a smaller space. By the capabilities of the 3D-IC technology, it could support a design included smaller size, high-speed and multi-functions. One of the 3D-IC techs, the stacking with Through-Silicon-Via (TSV), plays a very important role. It shortens the path, and hence, increases the bandwidth of the device. In this study, we evaluate the TSV effects in usual high-speed electrical designs. There are two issues, the impedance-control and isolation. By using the EM simulation solver, we estimate the performances of different designed models about these two issues. And, this result should have the benefits for the development on the designs in the interposer substrates used for 3D-IC technology.
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