Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117182
D. Rohde, C. Jager, Khatera Hazin, A. Uhlig
Filling through silicon via (TSV) with copper is one important process step in 3D-integration. Void free and reliable galvanic copper deposition is essential for yield and lifetime of microelectronic devices. Different TSV applications, as chip stacking and interposer, require different TSV dimensions. This demands high flexibility and applicability for small and large via sizes in the galvanic filling process. This paper compares two different acidic copper systems in respect of their TSV filling properties. Both systems mainly differ in the leveler compound. System A shows super-conformal filling behavior and System B bottom-up filling. The properties of copper being deposited using System A and B respectively vary further in respect of copper grain size homogeneity, stress of the copper deposits, recrystallization temperature and incorporation of additives. The influence of organic copper additives on the mechanical, thermal, and electrical properties of the copper deposits is discussed. Using the example of System B, filling aspects as well as process optimization will be outlined. For process optimization electrochemical potential characteristics (E vs. t) during the filling process are used to identify important filling steps. Filling examples for small as well as large TSV feature sizes will be discussed.
用铜填充硅孔(TSV)是3d集成的一个重要工艺步骤。无空隙可靠的电铜沉积对微电子器件的良率和寿命至关重要。不同的TSV应用，如芯片堆叠和中介，需要不同的TSV尺寸。这要求高灵活性和适用性的小和大通孔尺寸在电填充过程中。比较了两种不同酸性铜体系的TSV填充性能。这两种系统的主要区别在于矫直剂。体系A表现为超保形充填行为，体系B表现为自下而上充填行为。系统A和系统B沉积铜的性能在铜晶粒尺寸均匀性、镀层应力、再结晶温度和添加剂掺入等方面有进一步的差异。讨论了有机铜添加剂对铜镀层力学、热学和电学性能的影响。以系统B为例，概述填充方面以及流程优化。在工艺优化方面，利用填充过程中的电化学电位特性(E vs. t)来确定重要的填充步骤。将讨论小的和大的TSV特征尺寸的填充示例。
{"title":"Filling TSV of different dimension using galvanic copper deposition","authors":"D. Rohde, C. Jager, Khatera Hazin, A. Uhlig","doi":"10.1109/IMPACT.2011.6117182","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117182","url":null,"abstract":"Filling through silicon via (TSV) with copper is one important process step in 3D-integration. Void free and reliable galvanic copper deposition is essential for yield and lifetime of microelectronic devices. Different TSV applications, as chip stacking and interposer, require different TSV dimensions. This demands high flexibility and applicability for small and large via sizes in the galvanic filling process. This paper compares two different acidic copper systems in respect of their TSV filling properties. Both systems mainly differ in the leveler compound. System A shows super-conformal filling behavior and System B bottom-up filling. The properties of copper being deposited using System A and B respectively vary further in respect of copper grain size homogeneity, stress of the copper deposits, recrystallization temperature and incorporation of additives. The influence of organic copper additives on the mechanical, thermal, and electrical properties of the copper deposits is discussed. Using the example of System B, filling aspects as well as process optimization will be outlined. For process optimization electrochemical potential characteristics (E vs. t) during the filling process are used to identify important filling steps. Filling examples for small as well as large TSV feature sizes will be discussed.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"124 1","pages":"355-358"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88772712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117179
M. Ozkok, Bill Kao, H. Clauberg
During the past two years, fine pitch copper wire bonding has finally entered high volume production. It is estimated that nearly 15% of all wire bonders used in production are now equipped for copper wire bonding. Most of these are used exclusively for copper wire bonding. In terms of pitch, copper wire is only barely lagging behind the most advanced gold applications. The most commonly used copper wire is 20um in diameter and 18um copper wire is entering final qualification. Evaluations with even finer wire are underway. Although some technical challenges remain, many years of research have now resolved most of the problems associated with copper wire bonding and attention is beginning to shift from merely ensuring reliable manufacturing processes to optimizing processes for efficiency and throughput. The most advanced wire bonders now have pre-configured processes specifically designed for copper. In addition to throughput optimization, further cost reductions are being sought. Among these is the desire to eliminate the high-cost gold not just from the wire, but also from the substrate. On the substrate side the electronics packaging industry still works with electrolytic nickel / electrolytic (soft) gold (Ni/Au) for copper wire bond applications. This surface finish works with copper wire bonding but includes some disadvantages, such as: — Thick expensive Au layers of 0.1 to 0.4μm — Electrically connected pads (bussing for the plating) which require added space on the substrate. — Pd-coated copper wire often delivers better results on gold covered finishes, but is two to three times more expensive as pure copper wire. Furthermore electrolytic Ni/Au was not chosen as a result of in-depth investigations for the most effective surface finish. The selection was made because it was the surface finish with the highest distribution in the market for wire bond packages. This paper is offering the results of a two company joint work regarding an alternative copper wire bondable surface finish for substrates mainly with palladium as the final copper wire bondable layer. This offers further cost reduction possibilities. Furthermore, copper palladium intermetallics are regarded as very reliable.
{"title":"Palladium surface finishes for copper wire bonding (Part I: The selection of surface finishes)","authors":"M. Ozkok, Bill Kao, H. Clauberg","doi":"10.1109/IMPACT.2011.6117179","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117179","url":null,"abstract":"During the past two years, fine pitch copper wire bonding has finally entered high volume production. It is estimated that nearly 15% of all wire bonders used in production are now equipped for copper wire bonding. Most of these are used exclusively for copper wire bonding. In terms of pitch, copper wire is only barely lagging behind the most advanced gold applications. The most commonly used copper wire is 20um in diameter and 18um copper wire is entering final qualification. Evaluations with even finer wire are underway. Although some technical challenges remain, many years of research have now resolved most of the problems associated with copper wire bonding and attention is beginning to shift from merely ensuring reliable manufacturing processes to optimizing processes for efficiency and throughput. The most advanced wire bonders now have pre-configured processes specifically designed for copper. In addition to throughput optimization, further cost reductions are being sought. Among these is the desire to eliminate the high-cost gold not just from the wire, but also from the substrate. On the substrate side the electronics packaging industry still works with electrolytic nickel / electrolytic (soft) gold (Ni/Au) for copper wire bond applications. This surface finish works with copper wire bonding but includes some disadvantages, such as: — Thick expensive Au layers of 0.1 to 0.4μm — Electrically connected pads (bussing for the plating) which require added space on the substrate. — Pd-coated copper wire often delivers better results on gold covered finishes, but is two to three times more expensive as pure copper wire. Furthermore electrolytic Ni/Au was not chosen as a result of in-depth investigations for the most effective surface finish. The selection was made because it was the surface finish with the highest distribution in the market for wire bond packages. This paper is offering the results of a two company joint work regarding an alternative copper wire bondable surface finish for substrates mainly with palladium as the final copper wire bondable layer. This offers further cost reduction possibilities. Furthermore, copper palladium intermetallics are regarded as very reliable.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"1 1","pages":"37-41"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89629057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117274
Pen-Cheng Wang, W. Lin, Sz-Yuan Hung, Hsueh-Ju Lu
Pressure-dependent variable resistors were fabricated by coating conducting polymer thin films on the interior surfaces of porous polyurethane (PU) foams with thickness ranging from 1 mm to 5 mm. To coat conducting polymer thin films on the interior surfaces of the porous PU foams, the PU foams were first immersed in 1 M aqueous camphorsulfonic acid (HCSA) solution containing 0.44 M of aniline (monomer solution) and then transferred to another 1 M aqueous camphorsulfonic acid solution containing 0.1 M of ammonium peroxydisulfate (oxidant solution). After the polyaniline (PANI) deposition process by in situ oxidative chemical polymerization of aniline on the interior surfaces of the porous PU foams, the non-conductive PU foams became all-polymer conductive composites. The formation of PANI thin films on the interior surfaces of the porous PU foams was confirmed by optical microscopy and scanning election microscopy (SEM) studies, which showed that no bulk PANI was found to block the porous interstitial space of PU foams after the PANI deposition process. When a PANI-treated conductive PU foam was sandwiched between two pieces of plastic electrodes based on poly(ethyleneterephthalate) (PET) substrates coated with commercially available poly(3,4-ethylenedioxythiophene) doped with poly(styrenesulfonate) (PEDOT:PSS), the whole assembly could act as an all-polymer pressure sensor. By varying the size and thickness of the all-polymer PU-based pressure devices, the responsive ranges can be adjusted for different applications with different applied pressure ranges. With the incorporation of a polymeric cushion as the mechanical buffer layer around the conductive PU composite, the dynamic pressure-responsive range could be further increased. Compared to our previous work, the all-polymer pressure sensors described in the present work showed greater reproducibility when subject to repetitive cycling tests and exhibited greater continuous linear response range.
{"title":"Pressure-dependent variable resistors based on porous polymeric foams with conducting polymer thin films in situ coated on the interior surfaces","authors":"Pen-Cheng Wang, W. Lin, Sz-Yuan Hung, Hsueh-Ju Lu","doi":"10.1109/IMPACT.2011.6117274","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117274","url":null,"abstract":"Pressure-dependent variable resistors were fabricated by coating conducting polymer thin films on the interior surfaces of porous polyurethane (PU) foams with thickness ranging from 1 mm to 5 mm. To coat conducting polymer thin films on the interior surfaces of the porous PU foams, the PU foams were first immersed in 1 M aqueous camphorsulfonic acid (HCSA) solution containing 0.44 M of aniline (monomer solution) and then transferred to another 1 M aqueous camphorsulfonic acid solution containing 0.1 M of ammonium peroxydisulfate (oxidant solution). After the polyaniline (PANI) deposition process by in situ oxidative chemical polymerization of aniline on the interior surfaces of the porous PU foams, the non-conductive PU foams became all-polymer conductive composites. The formation of PANI thin films on the interior surfaces of the porous PU foams was confirmed by optical microscopy and scanning election microscopy (SEM) studies, which showed that no bulk PANI was found to block the porous interstitial space of PU foams after the PANI deposition process. When a PANI-treated conductive PU foam was sandwiched between two pieces of plastic electrodes based on poly(ethyleneterephthalate) (PET) substrates coated with commercially available poly(3,4-ethylenedioxythiophene) doped with poly(styrenesulfonate) (PEDOT:PSS), the whole assembly could act as an all-polymer pressure sensor. By varying the size and thickness of the all-polymer PU-based pressure devices, the responsive ranges can be adjusted for different applications with different applied pressure ranges. With the incorporation of a polymeric cushion as the mechanical buffer layer around the conductive PU composite, the dynamic pressure-responsive range could be further increased. Compared to our previous work, the all-polymer pressure sensors described in the present work showed greater reproducibility when subject to repetitive cycling tests and exhibited greater continuous linear response range.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"12 1","pages":"63-66"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89285247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117167
Norifumi Sasaoka, Takafumi Ochi, Y. Akiyama, K. Kono, C. Ueda, K. Otsuka
Power integrity (pi) for recent electronics circuits and systems is the most emergent technology in the GHz clock field and has been addressed in important papers through several approaches[1][2]. The latest concept of the best pi condition is recognized as maintaining lower impedance between power and ground lines or planes without any clock frequency dependency, even in the GHz region. We found this concept in a relatively old book [3] from the 1980s; thus, it is not the latest idea. However, it cannot be completely realized by the several previously proposed approaches, including many involving the use of low-inductance capacitances. We are aware that plane power and ground resonance are induced electromagnetic interference (emi) problems due to resonance caused by eddy currents or multiple reflections of voltage fluctuations. a novel technology was used in our previous study only using a conductive layer of dispersed metal particles [4]. The structure is consisted of a conventional fr-4 printed circuit board in which the copper ground plane was replaced with a metal particle conductive layer [4]. This structure improved the pi for any clock frequency especially in GHz region with an impedance of less than 1 Ω. This improvement is verified by an actual 16bit (two set) 3 Gbps/pin i/o interface board in this study. Even though the simultaneous switching of 32 drivers gave a fairly high current slew-rate of (8 mA × 32) / 60 ps = 4.27 × 109 A/s, the pi status was kept at an excellent value within 10% of the Vdd fluctuation.
当前电子电路和系统的功率完整性(pi)是GHz时钟领域中最新兴的技术，已经在一些重要的论文中通过几种方法进行了讨论。最佳pi条件的最新概念被认为是在没有任何时钟频率依赖的情况下保持电源和地线或平面之间的较低阻抗，即使在GHz区域。我们在20世纪80年代的一本相对较老的书b[3]中发现了这个概念;因此，这不是最新的想法。然而，它不能完全实现的几个先前提出的方法，包括许多涉及使用低电感电容。我们知道，平面电源和地面共振是由于涡流或电压波动的多重反射引起的共振而引起的感应电磁干扰(emi)问题。我们在之前的研究中使用了一种新技术，仅使用分散金属颗粒[4]的导电层。该结构由传统的fr-4印刷电路板组成，其中铜接地面被金属颗粒导电层[4]取代。这种结构改善了任何时钟频率的pi，特别是在GHz区域阻抗小于1 Ω。本研究通过实际的16位(两组)3 Gbps/pin i/o接口板验证了这一改进。尽管32个驱动器的同时开关产生了相当高的电流变化率(8 mA × 32) / 60 ps = 4.27 × 109 a /s，但pi状态在Vdd波动的10%以内保持在一个很好的值。
{"title":"New PC board structure for power supply technology over GHz frequency verificated with 32bit SSN driver system","authors":"Norifumi Sasaoka, Takafumi Ochi, Y. Akiyama, K. Kono, C. Ueda, K. Otsuka","doi":"10.1109/IMPACT.2011.6117167","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117167","url":null,"abstract":"Power integrity (pi) for recent electronics circuits and systems is the most emergent technology in the GHz clock field and has been addressed in important papers through several approaches[1][2]. The latest concept of the best pi condition is recognized as maintaining lower impedance between power and ground lines or planes without any clock frequency dependency, even in the GHz region. We found this concept in a relatively old book [3] from the 1980s; thus, it is not the latest idea. However, it cannot be completely realized by the several previously proposed approaches, including many involving the use of low-inductance capacitances. We are aware that plane power and ground resonance are induced electromagnetic interference (emi) problems due to resonance caused by eddy currents or multiple reflections of voltage fluctuations. a novel technology was used in our previous study only using a conductive layer of dispersed metal particles [4]. The structure is consisted of a conventional fr-4 printed circuit board in which the copper ground plane was replaced with a metal particle conductive layer [4]. This structure improved the pi for any clock frequency especially in GHz region with an impedance of less than 1 Ω. This improvement is verified by an actual 16bit (two set) 3 Gbps/pin i/o interface board in this study. Even though the simultaneous switching of 32 drivers gave a fairly high current slew-rate of (8 mA × 32) / 60 ps = 4.27 × 109 A/s, the pi status was kept at an excellent value within 10% of the Vdd fluctuation.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"2013 1","pages":"55-58"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87995363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117170
Y. Orii, K. Toriyama, S. Kohara, H. Noma, K. Okamoto, D. Toyoshima, K. Uenishi
The electromigration (EM) behavior of 80μm pitch C2 (Chip Connection) interconnection [1,2,3] is studied and discussed. C2 is a low cost, peripheral ultra fine pitch flip chip interconnection technology based on the solder capped Cu pillar bumps. The Cu pillar bumps are formed on Al pads that are commonly used in the wirebonding (WB) technique. It thus makes utmost use of the already existing infrastructure. Because C2 bumps are connected to OSP surface treated Cu pads on an organic substrate by reflow with no-clean process, it has a high throughput and is SMT (Surface Mount Technology) compatible. Since the space between dies and substrates is determined by the Cu pillar height, the collapse control of the solder bump is not required. Also, the pre-solder on substrates is also not required. It is an ideal technology for the systems requiring fine pitch structures. Various reliability tests including the thermal cycle tests and thermal humidity bias tests of C2 technology have already been performed. However, only few investigations have been done on the reliability against the EM failures for this technology. In this report, the EM tests were performed on 80μm pitch C2 flip chip interconnection. The interconnections with two different solder materials were tested: Sn/2.5Ag and Sn100%. The effects of Ni barrier layers on the Cu pillars and the pre-formed intermetallic compound (IMC) layers on the EM tests are studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height is 45μm and the solder height is 25μm. Aged process for pre-formed IMCs was 2,000 hrs at 150°C. The analysis on the samples after the tests showed that the Cu pillar dissociation occurs only in the electron flow direction. However the polarity dependence of IMC layer growths was not detected. C2 test vehicles with pre-formed IMC layers showed no significant electrical resistance increase during the test. Also the consumption of Cu atoms was not observed either from the Cu pillars on the dies or from the Cu pads on the substrates for these test vehicles. The Cu pillar dissociations into the solder were less for the pillars with Ni barrier layers than for those without. The results suggest that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in preventing the Cu atoms from dissociating into the solder. The present study showed a potential ways of forming the Cu pillar joints that are resistant to EM failures.
{"title":"Effect of preformed IMC layer on electromigration of peripheral ultra fine pitch C2 flip chip interconnection with solder capped Cu pillar bump","authors":"Y. Orii, K. Toriyama, S. Kohara, H. Noma, K. Okamoto, D. Toyoshima, K. Uenishi","doi":"10.1109/IMPACT.2011.6117170","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117170","url":null,"abstract":"The electromigration (EM) behavior of 80μm pitch C2 (Chip Connection) interconnection [1,2,3] is studied and discussed. C2 is a low cost, peripheral ultra fine pitch flip chip interconnection technology based on the solder capped Cu pillar bumps. The Cu pillar bumps are formed on Al pads that are commonly used in the wirebonding (WB) technique. It thus makes utmost use of the already existing infrastructure. Because C2 bumps are connected to OSP surface treated Cu pads on an organic substrate by reflow with no-clean process, it has a high throughput and is SMT (Surface Mount Technology) compatible. Since the space between dies and substrates is determined by the Cu pillar height, the collapse control of the solder bump is not required. Also, the pre-solder on substrates is also not required. It is an ideal technology for the systems requiring fine pitch structures. Various reliability tests including the thermal cycle tests and thermal humidity bias tests of C2 technology have already been performed. However, only few investigations have been done on the reliability against the EM failures for this technology. In this report, the EM tests were performed on 80μm pitch C2 flip chip interconnection. The interconnections with two different solder materials were tested: Sn/2.5Ag and Sn100%. The effects of Ni barrier layers on the Cu pillars and the pre-formed intermetallic compound (IMC) layers on the EM tests are studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height is 45μm and the solder height is 25μm. Aged process for pre-formed IMCs was 2,000 hrs at 150°C. The analysis on the samples after the tests showed that the Cu pillar dissociation occurs only in the electron flow direction. However the polarity dependence of IMC layer growths was not detected. C2 test vehicles with pre-formed IMC layers showed no significant electrical resistance increase during the test. Also the consumption of Cu atoms was not observed either from the Cu pillars on the dies or from the Cu pads on the substrates for these test vehicles. The Cu pillar dissociations into the solder were less for the pillars with Ni barrier layers than for those without. The results suggest that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in preventing the Cu atoms from dissociating into the solder. The present study showed a potential ways of forming the Cu pillar joints that are resistant to EM failures.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"3 1","pages":"206-209"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91260580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117175
S. Kawashima
Electronic equipment has changed to have higher performance with minimized in size. This trend required to electronic devices minimization also. Numerous packaging techniques have developed using metal flame, PWB material and plastic tape to mount semiconductor devices on PWB1). To achieve further high mounting density, the semiconductor device directly solder mounted on package after forming metal bumps on electrode of semiconductor devices. Aluminum alloy is common material for electrode of semiconductor devices, since it has relatively high conductivity, chemically stable and less reaction in semiconductor manufacturing process. However, it needs other meal layer for soldering to form bump on it. Sputtered Ti/Cu layer and electrolytic solder plating is widely used to form solder bump. However, this process requires longer and costly process such as multiple vacuum process, photo image process, etc.
{"title":"Electroless nickel/Immersion gold process on Aluminum alloy electrodes","authors":"S. Kawashima","doi":"10.1109/IMPACT.2011.6117175","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117175","url":null,"abstract":"Electronic equipment has changed to have higher performance with minimized in size. This trend required to electronic devices minimization also. Numerous packaging techniques have developed using metal flame, PWB material and plastic tape to mount semiconductor devices on PWB1). To achieve further high mounting density, the semiconductor device directly solder mounted on package after forming metal bumps on electrode of semiconductor devices. Aluminum alloy is common material for electrode of semiconductor devices, since it has relatively high conductivity, chemically stable and less reaction in semiconductor manufacturing process. However, it needs other meal layer for soldering to form bump on it. Sputtered Ti/Cu layer and electrolytic solder plating is widely used to form solder bump. However, this process requires longer and costly process such as multiple vacuum process, photo image process, etc.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"36 1","pages":"381-384"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85465008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117183
C. Yuan, R. Kregting, H. Ye, W. V. van Driel, S. Gielen, G. Zhang
Power electronics, such as high power RF components and high power LEDs, requires the combination of robust and reliable package structures, materials, and processes to guarantee their functional performance and lifetime. We started with the thermal and thermal-mechanical modeling of such component performances. With robust validation. Afterwards, an online testing method, design rules, and new structures/modifications have been implemented to improve the performance and reliability of high power electronics. This paper reviews our efforts on the RF transistors and high power LED's developments.
{"title":"High power electronics package: From modeling to implementation","authors":"C. Yuan, R. Kregting, H. Ye, W. V. van Driel, S. Gielen, G. Zhang","doi":"10.1109/IMPACT.2011.6117183","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117183","url":null,"abstract":"Power electronics, such as high power RF components and high power LEDs, requires the combination of robust and reliable package structures, materials, and processes to guarantee their functional performance and lifetime. We started with the thermal and thermal-mechanical modeling of such component performances. With robust validation. Afterwards, an online testing method, design rules, and new structures/modifications have been implemented to improve the performance and reliability of high power electronics. This paper reviews our efforts on the RF transistors and high power LED's developments.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"446 1","pages":"249-252"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78192675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117239
W. C. Huang, C. Ko, S. Hu, J. Leu, K. N. Chen
In this paper, the adhesion strength between Cu metal and Benzocyclobutene (BCB) polymer dielectric was investigated and reported. The relation between the adhesion strength and thickness of metal layer and the relation between the adhesion strength and stacking order of copper and BCB polymer layer are discussed as well. Finally, the concept of an extra layer between Cu metal and BCB polymer layer to improve the adhesion strength was evaluated. The results of this research can provide important guidelines of hybrid bonding and underfill for 3D integration applications.
{"title":"Investigations of adhesion between Cu and Benzocyclobutene (BCB) polymer dielectric for 3D integration applications","authors":"W. C. Huang, C. Ko, S. Hu, J. Leu, K. N. Chen","doi":"10.1109/IMPACT.2011.6117239","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117239","url":null,"abstract":"In this paper, the adhesion strength between Cu metal and Benzocyclobutene (BCB) polymer dielectric was investigated and reported. The relation between the adhesion strength and thickness of metal layer and the relation between the adhesion strength and stacking order of copper and BCB polymer layer are discussed as well. Finally, the concept of an extra layer between Cu metal and BCB polymer layer to improve the adhesion strength was evaluated. The results of this research can provide important guidelines of hybrid bonding and underfill for 3D integration applications.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"56 1","pages":"363-365"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83947748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117258
Sheng-Ren Chiu, Chung-Yang Sue, Lu-Pu Liao, Li-Tao Teng, Y. Hsu, Y. Su
This paper presents an all-in-one fully integrated circuit solution for a vibrating micro-electromechanical gyroscope system using standard 0.25um 1P5M low voltage CMOS process. The analog parts of the system include a trans-impedance amplifier (TIA) with adaptive gain control (AGC) for the resonator driving loop, a sigma-delta modulator with gain/offset trimming function for the Coriolis signal read-out and a modified all PMOS charge pump for the high DC voltage. The digital signal processing parts include a trimming/control logic circuit and an I2C interface. SOG-bulk micromachining and deep reactive ion etching (DRIE) are adopted to fabricate the gyroscope sensor element with high aspect-ratio sensing structure and high yield. The experimental results indicate that the noise floor achieves 0.051° / s/ √Hz and the scale factor is 7mV/ °/s of the proposed two chip MEMS gyroscope system.
本文提出了一种采用标准0.25um 1P5M低压CMOS工艺的振动微机电陀螺仪系统的一体化全集成电路方案。该系统的模拟部分包括用于谐振器驱动回路的具有自适应增益控制(AGC)的反阻抗放大器(TIA)，用于科里奥利信号读出的具有增益/失调调节功能的sigma-delta调制器，以及用于高直流电压的改进的全PMOS电荷泵。数字信号处理部分包括微调/控制逻辑电路和I2C接口。采用SOG-bulk微加工和深度反应离子刻蚀(deep reactive ion etching, DRIE)技术制备了具有高宽高比传感结构和高成品率的陀螺仪传感器元件。实验结果表明，所设计的双芯片MEMS陀螺仪系统的本底噪声达到0.051°/s /√Hz，比例因子为7mV/°/s。
{"title":"A fully integrated circuit for MEMS vibrating gyroscope using standard 0.25um CMOS process","authors":"Sheng-Ren Chiu, Chung-Yang Sue, Lu-Pu Liao, Li-Tao Teng, Y. Hsu, Y. Su","doi":"10.1109/IMPACT.2011.6117258","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117258","url":null,"abstract":"This paper presents an all-in-one fully integrated circuit solution for a vibrating micro-electromechanical gyroscope system using standard 0.25um 1P5M low voltage CMOS process. The analog parts of the system include a trans-impedance amplifier (TIA) with adaptive gain control (AGC) for the resonator driving loop, a sigma-delta modulator with gain/offset trimming function for the Coriolis signal read-out and a modified all PMOS charge pump for the high DC voltage. The digital signal processing parts include a trimming/control logic circuit and an I2C interface. SOG-bulk micromachining and deep reactive ion etching (DRIE) are adopted to fabricate the gyroscope sensor element with high aspect-ratio sensing structure and high yield. The experimental results indicate that the noise floor achieves 0.051° / s/ √Hz and the scale factor is 7mV/ °/s of the proposed two chip MEMS gyroscope system.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"50 1","pages":"315-318"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91137848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117223
R. Sung, K. Chiang, D. Lee, M. Ma
As the advance of the packaging technology for the electrical consuming demands, it requires for more functions or increasing the density of devices within a smaller space. By the capabilities of the 3D-IC technology, it could support a design included smaller size, high-speed and multi-functions. One of the 3D-IC techs, the stacking with Through-Silicon-Via (TSV), plays a very important role. It shortens the path, and hence, increases the bandwidth of the device. In this study, we evaluate the TSV effects in usual high-speed electrical designs. There are two issues, the impedance-control and isolation. By using the EM simulation solver, we estimate the performances of different designed models about these two issues. And, this result should have the benefits for the development on the designs in the interposer substrates used for 3D-IC technology.
{"title":"High-speed electrical design study for 3D-IC packaging technology","authors":"R. Sung, K. Chiang, D. Lee, M. Ma","doi":"10.1109/IMPACT.2011.6117223","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117223","url":null,"abstract":"As the advance of the packaging technology for the electrical consuming demands, it requires for more functions or increasing the density of devices within a smaller space. By the capabilities of the 3D-IC technology, it could support a design included smaller size, high-speed and multi-functions. One of the 3D-IC techs, the stacking with Through-Silicon-Via (TSV), plays a very important role. It shortens the path, and hence, increases the bandwidth of the device. In this study, we evaluate the TSV effects in usual high-speed electrical designs. There are two issues, the impedance-control and isolation. By using the EM simulation solver, we estimate the performances of different designed models about these two issues. And, this result should have the benefits for the development on the designs in the interposer substrates used for 3D-IC technology.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"59 1","pages":"144-146"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80835594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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