Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117175
S. Kawashima
Electronic equipment has changed to have higher performance with minimized in size. This trend required to electronic devices minimization also. Numerous packaging techniques have developed using metal flame, PWB material and plastic tape to mount semiconductor devices on PWB1). To achieve further high mounting density, the semiconductor device directly solder mounted on package after forming metal bumps on electrode of semiconductor devices. Aluminum alloy is common material for electrode of semiconductor devices, since it has relatively high conductivity, chemically stable and less reaction in semiconductor manufacturing process. However, it needs other meal layer for soldering to form bump on it. Sputtered Ti/Cu layer and electrolytic solder plating is widely used to form solder bump. However, this process requires longer and costly process such as multiple vacuum process, photo image process, etc.
{"title":"Electroless nickel/Immersion gold process on Aluminum alloy electrodes","authors":"S. Kawashima","doi":"10.1109/IMPACT.2011.6117175","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117175","url":null,"abstract":"Electronic equipment has changed to have higher performance with minimized in size. This trend required to electronic devices minimization also. Numerous packaging techniques have developed using metal flame, PWB material and plastic tape to mount semiconductor devices on PWB1). To achieve further high mounting density, the semiconductor device directly solder mounted on package after forming metal bumps on electrode of semiconductor devices. Aluminum alloy is common material for electrode of semiconductor devices, since it has relatively high conductivity, chemically stable and less reaction in semiconductor manufacturing process. However, it needs other meal layer for soldering to form bump on it. Sputtered Ti/Cu layer and electrolytic solder plating is widely used to form solder bump. However, this process requires longer and costly process such as multiple vacuum process, photo image process, etc.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"36 1","pages":"381-384"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85465008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117292
Kai-Yang Hsieh, Bo-Chuan Cheng, Ruei-Ting Gu, Katherine Shu-Min Li
3D Mesh NoCs (Network on Chips) are one of the best approaches to solve the complexity of interconnect structures in SoCs (System on Chips) which leads to lower yield. In this paper, we present a Mesh-based scheme for 3D NoCs with fault-tolerance that helps increasing chips' reliability and yield. There are several phases for this scheme. The phase I transforms a 2D NoC into an optimized 3D NoC under the constraints of area, routing length, temperature, performance and etc. Then, we optimize the I/O placement to get the best routing between I/O pads and all cores by clustering the placement of each core and reassign the tier sequence to minimize the number of TSVs. Finally, we build up the Mesh topology for each tier with squaring the maximum number of cores. For example, we need a 4×4 Mesh if the maximum cores in each tier are 15. Once the 3D Mesh topology is ready, we are going to set up the routing scheme that provides the minimum number of routers and the minimum routing latency in phase II. We also have a routing scheme to control the data flow and distribute the communication overhead. Phase III is to search the replacement routing paths. There will be at least 2 paths for each connection. The more replacement paths we found, the more faults can be tolerated and more computing time will be needed. We verify the fault-tolerant 3D Mesh NoC in phase IV. First, we randomly insert some faults to verify if the NoC is still working. We can get the maximum number of faults to be tolerated by increasing the number of faults until the system crash in the second step. The verification may need hundreds of times to get the approximate maximum faults. If the fault toleration is not good enough, we can go back to phase III to search more replacements. Experimental results show to this verified fault-tolerant 3D Mesh scheme to be effective and efficient. This scheme can efficiently transform a complex 2D NoC into 3D fault-tolerant Mesh NoC according to the user-defined constraints and also provides the tradeoff analysis between the tolerance and the search time of the effective replacement paths.
3D Mesh noc(片上网络)是解决片上系统互连结构复杂性导致成品率降低的最佳方法之一。在本文中，我们提出了一种基于网格的三维noc容错方案，有助于提高芯片的可靠性和良率。这个方案有几个阶段。在面积、布线长度、温度、性能等因素的约束下，将2D NoC转换为优化的3D NoC。然后，我们优化I/O布局，通过对每个内核的布局进行聚类，并重新分配层序列以最小化tsv的数量，从而获得I/O垫和所有内核之间的最佳路由。最后，我们为每个层构建网格拓扑，并将最大核数平方。例如，如果每层的最大核数是15，我们需要一个4×4 Mesh。一旦3D Mesh拓扑准备好了，我们将在第二阶段设置路由方案，提供最小数量的路由器和最小的路由延迟。我们还有一个路由方案来控制数据流和分配通信开销。第三阶段是搜索替换路由路径。每个连接至少有2条路径。我们发现的替换路径越多，可以容忍的故障就越多，所需的计算时间也就越多。我们在第四阶段验证了容错3D Mesh NoC。首先，我们随机插入一些故障来验证NoC是否仍在工作。在第二步中，我们可以通过增加故障数量，直到系统崩溃，从而获得可容忍的最大故障数量。验证可能需要数百次才能得到近似的最大故障。如果容错性不够好，我们可以回到第三阶段寻找更多的替代品。实验结果表明，该方案是有效的、高效的。该方案可以根据用户定义的约束条件，将复杂的二维网格NoC有效地转换为三维容错网格NoC，并提供容错度与有效替换路径搜索时间之间的权衡分析。
{"title":"Fault-tolerant mesh for 3D network on chip","authors":"Kai-Yang Hsieh, Bo-Chuan Cheng, Ruei-Ting Gu, Katherine Shu-Min Li","doi":"10.1109/IMPACT.2011.6117292","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117292","url":null,"abstract":"3D Mesh NoCs (Network on Chips) are one of the best approaches to solve the complexity of interconnect structures in SoCs (System on Chips) which leads to lower yield. In this paper, we present a Mesh-based scheme for 3D NoCs with fault-tolerance that helps increasing chips' reliability and yield. There are several phases for this scheme. The phase I transforms a 2D NoC into an optimized 3D NoC under the constraints of area, routing length, temperature, performance and etc. Then, we optimize the I/O placement to get the best routing between I/O pads and all cores by clustering the placement of each core and reassign the tier sequence to minimize the number of TSVs. Finally, we build up the Mesh topology for each tier with squaring the maximum number of cores. For example, we need a 4×4 Mesh if the maximum cores in each tier are 15. Once the 3D Mesh topology is ready, we are going to set up the routing scheme that provides the minimum number of routers and the minimum routing latency in phase II. We also have a routing scheme to control the data flow and distribute the communication overhead. Phase III is to search the replacement routing paths. There will be at least 2 paths for each connection. The more replacement paths we found, the more faults can be tolerated and more computing time will be needed. We verify the fault-tolerant 3D Mesh NoC in phase IV. First, we randomly insert some faults to verify if the NoC is still working. We can get the maximum number of faults to be tolerated by increasing the number of faults until the system crash in the second step. The verification may need hundreds of times to get the approximate maximum faults. If the fault toleration is not good enough, we can go back to phase III to search more replacements. Experimental results show to this verified fault-tolerant 3D Mesh scheme to be effective and efficient. This scheme can efficiently transform a complex 2D NoC into 3D fault-tolerant Mesh NoC according to the user-defined constraints and also provides the tradeoff analysis between the tolerance and the search time of the effective replacement paths.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"1 1","pages":"202-205"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82809550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117167
Norifumi Sasaoka, Takafumi Ochi, Y. Akiyama, K. Kono, C. Ueda, K. Otsuka
Power integrity (pi) for recent electronics circuits and systems is the most emergent technology in the GHz clock field and has been addressed in important papers through several approaches[1][2]. The latest concept of the best pi condition is recognized as maintaining lower impedance between power and ground lines or planes without any clock frequency dependency, even in the GHz region. We found this concept in a relatively old book [3] from the 1980s; thus, it is not the latest idea. However, it cannot be completely realized by the several previously proposed approaches, including many involving the use of low-inductance capacitances. We are aware that plane power and ground resonance are induced electromagnetic interference (emi) problems due to resonance caused by eddy currents or multiple reflections of voltage fluctuations. a novel technology was used in our previous study only using a conductive layer of dispersed metal particles [4]. The structure is consisted of a conventional fr-4 printed circuit board in which the copper ground plane was replaced with a metal particle conductive layer [4]. This structure improved the pi for any clock frequency especially in GHz region with an impedance of less than 1 Ω. This improvement is verified by an actual 16bit (two set) 3 Gbps/pin i/o interface board in this study. Even though the simultaneous switching of 32 drivers gave a fairly high current slew-rate of (8 mA × 32) / 60 ps = 4.27 × 109 A/s, the pi status was kept at an excellent value within 10% of the Vdd fluctuation.
当前电子电路和系统的功率完整性(pi)是GHz时钟领域中最新兴的技术，已经在一些重要的论文中通过几种方法进行了讨论。最佳pi条件的最新概念被认为是在没有任何时钟频率依赖的情况下保持电源和地线或平面之间的较低阻抗，即使在GHz区域。我们在20世纪80年代的一本相对较老的书b[3]中发现了这个概念;因此，这不是最新的想法。然而，它不能完全实现的几个先前提出的方法，包括许多涉及使用低电感电容。我们知道，平面电源和地面共振是由于涡流或电压波动的多重反射引起的共振而引起的感应电磁干扰(emi)问题。我们在之前的研究中使用了一种新技术，仅使用分散金属颗粒[4]的导电层。该结构由传统的fr-4印刷电路板组成，其中铜接地面被金属颗粒导电层[4]取代。这种结构改善了任何时钟频率的pi，特别是在GHz区域阻抗小于1 Ω。本研究通过实际的16位(两组)3 Gbps/pin i/o接口板验证了这一改进。尽管32个驱动器的同时开关产生了相当高的电流变化率(8 mA × 32) / 60 ps = 4.27 × 109 a /s，但pi状态在Vdd波动的10%以内保持在一个很好的值。
{"title":"New PC board structure for power supply technology over GHz frequency verificated with 32bit SSN driver system","authors":"Norifumi Sasaoka, Takafumi Ochi, Y. Akiyama, K. Kono, C. Ueda, K. Otsuka","doi":"10.1109/IMPACT.2011.6117167","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117167","url":null,"abstract":"Power integrity (pi) for recent electronics circuits and systems is the most emergent technology in the GHz clock field and has been addressed in important papers through several approaches[1][2]. The latest concept of the best pi condition is recognized as maintaining lower impedance between power and ground lines or planes without any clock frequency dependency, even in the GHz region. We found this concept in a relatively old book [3] from the 1980s; thus, it is not the latest idea. However, it cannot be completely realized by the several previously proposed approaches, including many involving the use of low-inductance capacitances. We are aware that plane power and ground resonance are induced electromagnetic interference (emi) problems due to resonance caused by eddy currents or multiple reflections of voltage fluctuations. a novel technology was used in our previous study only using a conductive layer of dispersed metal particles [4]. The structure is consisted of a conventional fr-4 printed circuit board in which the copper ground plane was replaced with a metal particle conductive layer [4]. This structure improved the pi for any clock frequency especially in GHz region with an impedance of less than 1 Ω. This improvement is verified by an actual 16bit (two set) 3 Gbps/pin i/o interface board in this study. Even though the simultaneous switching of 32 drivers gave a fairly high current slew-rate of (8 mA × 32) / 60 ps = 4.27 × 109 A/s, the pi status was kept at an excellent value within 10% of the Vdd fluctuation.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"2013 1","pages":"55-58"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87995363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117276
Li-Ying Hsieh, H. Yang, T. Chiu
To investigate the fatigue response of Pb-free Sn3.8Ag0.7Cu (SAC3807) solder, cyclic double lap shear tests consisting both loading ramp and dwell periods under isothermal conditions were performed on ball grid array (BGA) SAC3807 solder joints. Factors including test temperature, shear load amplitude and load dwell time were considered in the experiment for determining the damage acceleration effects. From the experiment it was observed that, during the cyclic shear load ramping stages, ratcheting still occurs even though the peak load is below the yielding point of solder. Transient and steady-state creep responses were also observed during the dwell stages of the cycling profile. Both ratcheting and creep responses become more significant as temperature and peak load increases. An important finding of the study is that the contribution of creep to the overall load-displacement hysteresis is more significant than the contribution of ratcheting. The corresponding inelastic energy dissipation under the cyclic double lap shear experiments were compared numerically to that of a typical wafer-level package under board-level temperature cycling (T/C). The comparison can be used for developing acceleration factors between the cyclic shear and board-level T/C tests.
{"title":"Ratcheting and creep responses of SAC solder joints under cyclic loading","authors":"Li-Ying Hsieh, H. Yang, T. Chiu","doi":"10.1109/IMPACT.2011.6117276","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117276","url":null,"abstract":"To investigate the fatigue response of Pb-free Sn3.8Ag0.7Cu (SAC3807) solder, cyclic double lap shear tests consisting both loading ramp and dwell periods under isothermal conditions were performed on ball grid array (BGA) SAC3807 solder joints. Factors including test temperature, shear load amplitude and load dwell time were considered in the experiment for determining the damage acceleration effects. From the experiment it was observed that, during the cyclic shear load ramping stages, ratcheting still occurs even though the peak load is below the yielding point of solder. Transient and steady-state creep responses were also observed during the dwell stages of the cycling profile. Both ratcheting and creep responses become more significant as temperature and peak load increases. An important finding of the study is that the contribution of creep to the overall load-displacement hysteresis is more significant than the contribution of ratcheting. The corresponding inelastic energy dissipation under the cyclic double lap shear experiments were compared numerically to that of a typical wafer-level package under board-level temperature cycling (T/C). The comparison can be used for developing acceleration factors between the cyclic shear and board-level T/C tests.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"56 1","pages":"96-99"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76050856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117237
C. Hong, Ming C. Lee
Two processes of components embedding, both active dies and passive components, have been demonstrated so far — one is the embedding of chip by ABF/RCC material, and the other is the embedding by multiple plies of prepreg with machined cavity of placing component. ABF/RCC materials appear to the most straight forward way to embed components into PCB. The drawback is that the components to be embedded have to be thinned to 50μm but this is not practical for all types of components, and also the cost is very high. Multiple-ply prepreg with machined cavity can accommodate die of various thickness and thus offer more choice of different component thickness. However they do not get wide acceptance because of the low throughput and the concerns over the yield. To address the problem component embedding and offer the solution, Atotech has developed a novel process of manufacturing FR-4 material. This novel process, named “Advanced Dielectric Epoxy Powder Technology (ADEPT)”, is a solvent-free production technology. The dielectric is made of powder and is later coated on the copper foil. The final form is a resin-coated copper foil (RCC.) Moreover, the glass fabric can be laminated into the RCC, making it a Reinforced Resin-Coated Copper foil (RRCC.) The materials have passed reliability tests required in PCB and assembly industry, which include lead-free assembly, MSL, HAST, CAF, and TCT. By ADEPT, a multi-layer material, in sheet form, can be produced for the embedded substrate. First, a reinforced dielectric layer with glass fabric will offer good dimension control. Second, an additional resin layer, with high filler content to reduce CTE, will be used for component embedding. With the multi-layer material, the process of component embedding can be done in one go, without having the drawbacks of the large warpage by ABF, or the step of the cavity formation required by multiple-ply prepreg. After component embedding, the reinforced layer effectively minimizes the warpage so the panel can be laser drilled and processed. Finally an ultra thin, low profile copper foil will be ideal for modified Semi-Additive Process (mSAP), a way of fine line structuring at relatively low cost. Since by ADEPT the dielectric is made of powder, it soon lends itself easily to the molding process in assembly. Its advantages over molding compounds are the capabilities of form small (50μm) laser vias due to the selection of sub-micron filler (Max./Mean filler size=1.0/0.3μm) and it is compatible with e'less copper deposition. As close partners, Atotech and ASE Global are exploring the applications of this dielectric powder as a molding compound for component embedding process.
{"title":"A novel FR-4 material for embedded substrate","authors":"C. Hong, Ming C. Lee","doi":"10.1109/IMPACT.2011.6117237","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117237","url":null,"abstract":"Two processes of components embedding, both active dies and passive components, have been demonstrated so far — one is the embedding of chip by ABF/RCC material, and the other is the embedding by multiple plies of prepreg with machined cavity of placing component. ABF/RCC materials appear to the most straight forward way to embed components into PCB. The drawback is that the components to be embedded have to be thinned to 50μm but this is not practical for all types of components, and also the cost is very high. Multiple-ply prepreg with machined cavity can accommodate die of various thickness and thus offer more choice of different component thickness. However they do not get wide acceptance because of the low throughput and the concerns over the yield. To address the problem component embedding and offer the solution, Atotech has developed a novel process of manufacturing FR-4 material. This novel process, named “Advanced Dielectric Epoxy Powder Technology (ADEPT)”, is a solvent-free production technology. The dielectric is made of powder and is later coated on the copper foil. The final form is a resin-coated copper foil (RCC.) Moreover, the glass fabric can be laminated into the RCC, making it a Reinforced Resin-Coated Copper foil (RRCC.) The materials have passed reliability tests required in PCB and assembly industry, which include lead-free assembly, MSL, HAST, CAF, and TCT. By ADEPT, a multi-layer material, in sheet form, can be produced for the embedded substrate. First, a reinforced dielectric layer with glass fabric will offer good dimension control. Second, an additional resin layer, with high filler content to reduce CTE, will be used for component embedding. With the multi-layer material, the process of component embedding can be done in one go, without having the drawbacks of the large warpage by ABF, or the step of the cavity formation required by multiple-ply prepreg. After component embedding, the reinforced layer effectively minimizes the warpage so the panel can be laser drilled and processed. Finally an ultra thin, low profile copper foil will be ideal for modified Semi-Additive Process (mSAP), a way of fine line structuring at relatively low cost. Since by ADEPT the dielectric is made of powder, it soon lends itself easily to the molding process in assembly. Its advantages over molding compounds are the capabilities of form small (50μm) laser vias due to the selection of sub-micron filler (Max./Mean filler size=1.0/0.3μm) and it is compatible with e'less copper deposition. As close partners, Atotech and ASE Global are exploring the applications of this dielectric powder as a molding compound for component embedding process.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"2 1","pages":"177-178"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74913773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117179
M. Ozkok, Bill Kao, H. Clauberg
During the past two years, fine pitch copper wire bonding has finally entered high volume production. It is estimated that nearly 15% of all wire bonders used in production are now equipped for copper wire bonding. Most of these are used exclusively for copper wire bonding. In terms of pitch, copper wire is only barely lagging behind the most advanced gold applications. The most commonly used copper wire is 20um in diameter and 18um copper wire is entering final qualification. Evaluations with even finer wire are underway. Although some technical challenges remain, many years of research have now resolved most of the problems associated with copper wire bonding and attention is beginning to shift from merely ensuring reliable manufacturing processes to optimizing processes for efficiency and throughput. The most advanced wire bonders now have pre-configured processes specifically designed for copper. In addition to throughput optimization, further cost reductions are being sought. Among these is the desire to eliminate the high-cost gold not just from the wire, but also from the substrate. On the substrate side the electronics packaging industry still works with electrolytic nickel / electrolytic (soft) gold (Ni/Au) for copper wire bond applications. This surface finish works with copper wire bonding but includes some disadvantages, such as: — Thick expensive Au layers of 0.1 to 0.4μm — Electrically connected pads (bussing for the plating) which require added space on the substrate. — Pd-coated copper wire often delivers better results on gold covered finishes, but is two to three times more expensive as pure copper wire. Furthermore electrolytic Ni/Au was not chosen as a result of in-depth investigations for the most effective surface finish. The selection was made because it was the surface finish with the highest distribution in the market for wire bond packages. This paper is offering the results of a two company joint work regarding an alternative copper wire bondable surface finish for substrates mainly with palladium as the final copper wire bondable layer. This offers further cost reduction possibilities. Furthermore, copper palladium intermetallics are regarded as very reliable.
{"title":"Palladium surface finishes for copper wire bonding (Part I: The selection of surface finishes)","authors":"M. Ozkok, Bill Kao, H. Clauberg","doi":"10.1109/IMPACT.2011.6117179","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117179","url":null,"abstract":"During the past two years, fine pitch copper wire bonding has finally entered high volume production. It is estimated that nearly 15% of all wire bonders used in production are now equipped for copper wire bonding. Most of these are used exclusively for copper wire bonding. In terms of pitch, copper wire is only barely lagging behind the most advanced gold applications. The most commonly used copper wire is 20um in diameter and 18um copper wire is entering final qualification. Evaluations with even finer wire are underway. Although some technical challenges remain, many years of research have now resolved most of the problems associated with copper wire bonding and attention is beginning to shift from merely ensuring reliable manufacturing processes to optimizing processes for efficiency and throughput. The most advanced wire bonders now have pre-configured processes specifically designed for copper. In addition to throughput optimization, further cost reductions are being sought. Among these is the desire to eliminate the high-cost gold not just from the wire, but also from the substrate. On the substrate side the electronics packaging industry still works with electrolytic nickel / electrolytic (soft) gold (Ni/Au) for copper wire bond applications. This surface finish works with copper wire bonding but includes some disadvantages, such as: — Thick expensive Au layers of 0.1 to 0.4μm — Electrically connected pads (bussing for the plating) which require added space on the substrate. — Pd-coated copper wire often delivers better results on gold covered finishes, but is two to three times more expensive as pure copper wire. Furthermore electrolytic Ni/Au was not chosen as a result of in-depth investigations for the most effective surface finish. The selection was made because it was the surface finish with the highest distribution in the market for wire bond packages. This paper is offering the results of a two company joint work regarding an alternative copper wire bondable surface finish for substrates mainly with palladium as the final copper wire bondable layer. This offers further cost reduction possibilities. Furthermore, copper palladium intermetallics are regarded as very reliable.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"1 1","pages":"37-41"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89629057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117291
H. Hsu, J. Chien, S. Fu
Electronic Submission Nano-mechanical properties of ultra-thin copper wire (ψ =0.6mil) and nano-tribology along the interfacial between free air ball (FAB) and aluminum bond pad were carefully investigated in this paper. For comparison, commercial product Pt-coated 99.99% (4N) Cu wire and pure 4N Cu wire are selected as test materials. Bonding temperature effects were taken into account for all case studies. Tensile mechanical properties were conducted through self-designed wire pull test fixture. Nono-indentation instrument was applied to obtained thin surface elastic modulus on FAB. Nanotribology and interfacial frictional behavior along smashed FAB and bond pad were measured by Atomic Force Microscopy (AFM). AFM force-displacement curve is utilized to determine the nanotribology properties. The interfacial coefficient of frictional force can be derived from a serial of calculations. A well-defined contact area is measured to study the frictional force and friction stress. The roughness of contact surface influences the contact between friction and surface forces. The study of roughness parameters corresponds to evaluate the friction and the interfacial strengths. Local variation in micro/nano tribology is also measured.
{"title":"A study on Nano-mechanical properties and nano-tribology for ultra-thin Pt-coated 4N copper wire","authors":"H. Hsu, J. Chien, S. Fu","doi":"10.1109/IMPACT.2011.6117291","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117291","url":null,"abstract":"Electronic Submission Nano-mechanical properties of ultra-thin copper wire (ψ =0.6mil) and nano-tribology along the interfacial between free air ball (FAB) and aluminum bond pad were carefully investigated in this paper. For comparison, commercial product Pt-coated 99.99% (4N) Cu wire and pure 4N Cu wire are selected as test materials. Bonding temperature effects were taken into account for all case studies. Tensile mechanical properties were conducted through self-designed wire pull test fixture. Nono-indentation instrument was applied to obtained thin surface elastic modulus on FAB. Nanotribology and interfacial frictional behavior along smashed FAB and bond pad were measured by Atomic Force Microscopy (AFM). AFM force-displacement curve is utilized to determine the nanotribology properties. The interfacial coefficient of frictional force can be derived from a serial of calculations. A well-defined contact area is measured to study the frictional force and friction stress. The roughness of contact surface influences the contact between friction and surface forces. The study of roughness parameters corresponds to evaluate the friction and the interfacial strengths. Local variation in micro/nano tribology is also measured.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"14 1","pages":"488-491"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80042549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117269
De-Shin Liu, I. Lin
The moisture diffusion phenomenon of UV-curable adhesive apply to the packaging of organic light-emitting devices (OLEDs) were investigated. Owing to the sensitivity of moisture ingress into OLEDs package, how to against the moisture permeation will be one of the key design issue. As regards to improve the moisture-resistant capability of the materials for encapsulating, one possible way is to add particles into UV-curable sealing adhesive. In this study, a numerical simulation model that contained randomly distributed particles into heterogeneous epoxy resin has been developed. The commercial software MATLAB is employed to generate the location of randomly distributed particles and the commercial software ANSYS based on the finite element method is employed to analyze moisture diffusion in containing multiple randomly distributed particles. Furthermore, this model is then employed to investigate the relationship between the volume fraction of the particles in the resin composite and the rate of moisture diffusion. The simulation results show that moisture diffusion is retarded significantly as the volume fraction of particles increases. Moreover, the adhesive with high volume fraction of particle exhibits superior moisture-resistant capability. However, excessively add particles makes inferior penetrability. Therefore, adding proper volume percentage of particle into UV-curable adhesive could be expected better using in engineering applications.
{"title":"Modeling of moisture diffusion in heterogeneous epoxy resin containing multiple randomly distributed particles using finite element method","authors":"De-Shin Liu, I. Lin","doi":"10.1109/IMPACT.2011.6117269","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117269","url":null,"abstract":"The moisture diffusion phenomenon of UV-curable adhesive apply to the packaging of organic light-emitting devices (OLEDs) were investigated. Owing to the sensitivity of moisture ingress into OLEDs package, how to against the moisture permeation will be one of the key design issue. As regards to improve the moisture-resistant capability of the materials for encapsulating, one possible way is to add particles into UV-curable sealing adhesive. In this study, a numerical simulation model that contained randomly distributed particles into heterogeneous epoxy resin has been developed. The commercial software MATLAB is employed to generate the location of randomly distributed particles and the commercial software ANSYS based on the finite element method is employed to analyze moisture diffusion in containing multiple randomly distributed particles. Furthermore, this model is then employed to investigate the relationship between the volume fraction of the particles in the resin composite and the rate of moisture diffusion. The simulation results show that moisture diffusion is retarded significantly as the volume fraction of particles increases. Moreover, the adhesive with high volume fraction of particle exhibits superior moisture-resistant capability. However, excessively add particles makes inferior penetrability. Therefore, adding proper volume percentage of particle into UV-curable adhesive could be expected better using in engineering applications.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"167 1","pages":"79-82"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87059826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117207
Christian Alvin, W. Chu, Ching-hung Cheng, J. Teng
Light Emitting Diode or LED now is becoming a popular lighting used at many types of applications. LED becomes more favorable to use than other types of lighting such as fluorescent or even light bulb. This is because LED can provide high lumens with low power electricity and does not contain any toxic material, such as fluorescent lights having mercury inside which is not good towards the environment. Advantages of using LED are high luminosity, more energy saving, high lifetime hours, and applicable in many applications. However, LED operating temperature should be considered. LEDs with high power, such as 10 Watts or more, can generate bright lighting, but also will have high operating temperature. This high operating temperature of LED should be lowered, since high operating temperature will lead to reductions of the luminosity and the lifetime of LED. Many cooling systems can be used to reduce the operating temperature of LED; a simple one is to use the extruded-fin heat sink. Heat sink is easy to manufacture, relatively low in cost, light in weight, and can become an adequate cooling means with good reliability. The choice of an optimal heat sink dimension depends on the power of heat source. In this work, 10-Watt LED with the 58 °C operating temperature was used. The aim for this study was to add extruded-fin heat sink to dissipate heat generated by the LED, with target temperature of LED decreased down to 50°C. Initial experiment was done to check the LED operating temperature and then ANSYS ICEPAK was used for numerical simulation; ANSYS ICEPAK is computational software for the study of thermal management of electronic devices and systems. For the present study, the numerical simulation of LED using extruded-fin as heat sink was performed. Through numerical simulation accounting for the variations in fin heights, fin thicknesses, fin pitches, and base heights, the optimal dimension of the heat sink was determined to achieve the target temperature of 50°C. Subsequently, prototype of aluminum fin heat sink was build to carry out the experiments for the purpose of validating the results obtained from numerical simulations. In the experiment, two kinds of thermal conductive pastes — a heat transfer compound and silver paste — were used to assemble the heat sink and LED. The effect of thermal conductive pastes on the overall thermal management of LED was investigated. Through the experiments, silver paste was proven to enhance the thermal conductivity, measured by the heat sink thermal resistance, reducing 0.02 °C/W compared with those using heat transfer compound. Both experimental tests and numerical simulations were done. Results obtained from the experiments and those obtained from the simulations were in good agreement, having percentage of differences less than 12%. From this study, it was shown that heat sinks with a good thermal conductive paste have proven to be an effective solution for the LED heat dissipation. Using ANSYS ICEPAK a
{"title":"Thermal analysis of extruded aluminum fin heat sink for LED cooling application","authors":"Christian Alvin, W. Chu, Ching-hung Cheng, J. Teng","doi":"10.1109/IMPACT.2011.6117207","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117207","url":null,"abstract":"Light Emitting Diode or LED now is becoming a popular lighting used at many types of applications. LED becomes more favorable to use than other types of lighting such as fluorescent or even light bulb. This is because LED can provide high lumens with low power electricity and does not contain any toxic material, such as fluorescent lights having mercury inside which is not good towards the environment. Advantages of using LED are high luminosity, more energy saving, high lifetime hours, and applicable in many applications. However, LED operating temperature should be considered. LEDs with high power, such as 10 Watts or more, can generate bright lighting, but also will have high operating temperature. This high operating temperature of LED should be lowered, since high operating temperature will lead to reductions of the luminosity and the lifetime of LED. Many cooling systems can be used to reduce the operating temperature of LED; a simple one is to use the extruded-fin heat sink. Heat sink is easy to manufacture, relatively low in cost, light in weight, and can become an adequate cooling means with good reliability. The choice of an optimal heat sink dimension depends on the power of heat source. In this work, 10-Watt LED with the 58 °C operating temperature was used. The aim for this study was to add extruded-fin heat sink to dissipate heat generated by the LED, with target temperature of LED decreased down to 50°C. Initial experiment was done to check the LED operating temperature and then ANSYS ICEPAK was used for numerical simulation; ANSYS ICEPAK is computational software for the study of thermal management of electronic devices and systems. For the present study, the numerical simulation of LED using extruded-fin as heat sink was performed. Through numerical simulation accounting for the variations in fin heights, fin thicknesses, fin pitches, and base heights, the optimal dimension of the heat sink was determined to achieve the target temperature of 50°C. Subsequently, prototype of aluminum fin heat sink was build to carry out the experiments for the purpose of validating the results obtained from numerical simulations. In the experiment, two kinds of thermal conductive pastes — a heat transfer compound and silver paste — were used to assemble the heat sink and LED. The effect of thermal conductive pastes on the overall thermal management of LED was investigated. Through the experiments, silver paste was proven to enhance the thermal conductivity, measured by the heat sink thermal resistance, reducing 0.02 °C/W compared with those using heat transfer compound. Both experimental tests and numerical simulations were done. Results obtained from the experiments and those obtained from the simulations were in good agreement, having percentage of differences less than 12%. From this study, it was shown that heat sinks with a good thermal conductive paste have proven to be an effective solution for the LED heat dissipation. Using ANSYS ICEPAK a","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"14 1","pages":"397-400"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87029916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117239
W. C. Huang, C. Ko, S. Hu, J. Leu, K. N. Chen
In this paper, the adhesion strength between Cu metal and Benzocyclobutene (BCB) polymer dielectric was investigated and reported. The relation between the adhesion strength and thickness of metal layer and the relation between the adhesion strength and stacking order of copper and BCB polymer layer are discussed as well. Finally, the concept of an extra layer between Cu metal and BCB polymer layer to improve the adhesion strength was evaluated. The results of this research can provide important guidelines of hybrid bonding and underfill for 3D integration applications.
{"title":"Investigations of adhesion between Cu and Benzocyclobutene (BCB) polymer dielectric for 3D integration applications","authors":"W. C. Huang, C. Ko, S. Hu, J. Leu, K. N. Chen","doi":"10.1109/IMPACT.2011.6117239","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117239","url":null,"abstract":"In this paper, the adhesion strength between Cu metal and Benzocyclobutene (BCB) polymer dielectric was investigated and reported. The relation between the adhesion strength and thickness of metal layer and the relation between the adhesion strength and stacking order of copper and BCB polymer layer are discussed as well. Finally, the concept of an extra layer between Cu metal and BCB polymer layer to improve the adhesion strength was evaluated. The results of this research can provide important guidelines of hybrid bonding and underfill for 3D integration applications.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"56 1","pages":"363-365"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83947748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：