Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117159
C. S. Tan, J. Fan
Metallic copper-copper (Cu-Cu) thermo-compression bonding is investigated for potential application as hermetic seal in 3D microsystem packaging. Cavities are etched to a volume of 1.4×10−3 cm3 in accordance with the MIL-STD-883E standard prescribed for microelectronics packaging. In the case of metal bonding, clean Cu layer with a thickness of 300 nm and an underlying 50 nm of Ti barrier layer are used. The wafer pair is bonded at 300 °C under the application of a bonding force of 5500 N for 1 hr. The bonded cavities are stored in a helium bomb chamber and leak rate is measured with a mass spectrometer. Excellent helium leak rate below 5 × 10−9 atm.cm3/s is detected for all cases and this is at least 10X better than the reject limit. Based on these results, Cu-Cu thermo-compression bonding is particularly attractive for wafer-level hermetic packaging of 3D microsystems (IC/IC, non-IC/IC, etc) as the same bonding medium can provide for hermetic seal, electrical connection, and mechanical bond. Since Cu-Cu bond is a single metal system, no inter-metallic compound (IMC) is formed hence resulting in excellent electrical, thermal, and mechanical properties of the bond compared with solder-based or eutectic bonding. Cu-Cu bonding is also a low cost solution in comparison with Au-Au bonding.
{"title":"Wafer level hermetic packaging with IMC-less Cu-Cu bonding for 3D microsystems (invited)","authors":"C. S. Tan, J. Fan","doi":"10.1109/IMPACT.2011.6117159","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117159","url":null,"abstract":"Metallic copper-copper (Cu-Cu) thermo-compression bonding is investigated for potential application as hermetic seal in 3D microsystem packaging. Cavities are etched to a volume of 1.4×10−3 cm3 in accordance with the MIL-STD-883E standard prescribed for microelectronics packaging. In the case of metal bonding, clean Cu layer with a thickness of 300 nm and an underlying 50 nm of Ti barrier layer are used. The wafer pair is bonded at 300 °C under the application of a bonding force of 5500 N for 1 hr. The bonded cavities are stored in a helium bomb chamber and leak rate is measured with a mass spectrometer. Excellent helium leak rate below 5 × 10−9 atm.cm3/s is detected for all cases and this is at least 10X better than the reject limit. Based on these results, Cu-Cu thermo-compression bonding is particularly attractive for wafer-level hermetic packaging of 3D microsystems (IC/IC, non-IC/IC, etc) as the same bonding medium can provide for hermetic seal, electrical connection, and mechanical bond. Since Cu-Cu bond is a single metal system, no inter-metallic compound (IMC) is formed hence resulting in excellent electrical, thermal, and mechanical properties of the bond compared with solder-based or eutectic bonding. Cu-Cu bonding is also a low cost solution in comparison with Au-Au bonding.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"38 1","pages":"339-342"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74946150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117229
Boxiang Fang, Ming-fan Tsai, Sam Lin, Min-Han Chuang, D. Lee
Stacked-coil inductor could be realized on multilevel thin-film structure with the configuration of two or more coils placed in different levels but shared the same magnetic flux. The configuration results mutual inductance to increase total inductance per unit area, it could make inductor compact to meet requirement of circuit on novel consumer electronic terminators. The metal coils of inductor on different levels are isolated by polymers which is an important component of IPD technology. Mechanical properties of polymers have strong influence on electric characteristic, which should be considered in model and will present in this paper. The scalable parameters of model are also extracted to implement process design kit (PDK) with parameterized inductors which could be used in system in package (SiP) or 3D IC interposer for RF applications.
{"title":"Modeling of stacked-coil inductor from silicon integrated passive device technology","authors":"Boxiang Fang, Ming-fan Tsai, Sam Lin, Min-Han Chuang, D. Lee","doi":"10.1109/IMPACT.2011.6117229","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117229","url":null,"abstract":"Stacked-coil inductor could be realized on multilevel thin-film structure with the configuration of two or more coils placed in different levels but shared the same magnetic flux. The configuration results mutual inductance to increase total inductance per unit area, it could make inductor compact to meet requirement of circuit on novel consumer electronic terminators. The metal coils of inductor on different levels are isolated by polymers which is an important component of IPD technology. Mechanical properties of polymers have strong influence on electric characteristic, which should be considered in model and will present in this paper. The scalable parameters of model are also extracted to implement process design kit (PDK) with parameterized inductors which could be used in system in package (SiP) or 3D IC interposer for RF applications.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"23 1","pages":"133-136"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77389033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117172
H. Nakajima
Automotive Electronics Revolutions in automotive technology have been driven by two motivations; maximizing comfort and fun, and “zeronizing” accidents and eco-hazards.[1] Recent resource-conservation move has promoted applications of electronic technology for better gas utilization. Many mechanical parts have been replaced by semiconductor devices, microelectromechanical systems (MEMS) and electric motors to make vehicles safer, more comfortable and eco-friendly. Numbers of electronic control units (ECUs), MEMS and electric motors used in a vehicle have reached 100 to 130 pieces now. Downward trend of MEMS costs has also boosted the adoption of MEMS for vehicles.
{"title":"Semiconductor packages for automotive applications","authors":"H. Nakajima","doi":"10.1109/IMPACT.2011.6117172","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117172","url":null,"abstract":"Automotive Electronics Revolutions in automotive technology have been driven by two motivations; maximizing comfort and fun, and “zeronizing” accidents and eco-hazards.[1] Recent resource-conservation move has promoted applications of electronic technology for better gas utilization. Many mechanical parts have been replaced by semiconductor devices, microelectromechanical systems (MEMS) and electric motors to make vehicles safer, more comfortable and eco-friendly. Numbers of electronic control units (ECUs), MEMS and electric motors used in a vehicle have reached 100 to 130 pieces now. Downward trend of MEMS costs has also boosted the adoption of MEMS for vehicles.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"24 1","pages":"287-290"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87205361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117222
Chien-Chen Lee, Li Chiun Hung, Pai-Yuan Li, M. Hsieh, Harry Perng, V. Wang
Cold-joint defect has been critically discussed in flip chip interconnections, especially for lead-free solder and Cu pillar bumps in fcFBGA (flip chip fine-pitch BGA). In the case of Cu pillar bump, the only known effective method for cold-joint detection is package Open/Short Test. This study introduces an effective alternative method of Cold-joint detection while during assembly setup stage, which employs the moderate filler segregation phenomenon among Cu pillar bumps, especially for Cu pillar bump without solder cap. For joint connections with Cu-pillar bumps, a voltage separates the underfill material's filler and resin due to the electrode potential difference between Cu and Sn. The filler migrates towards the Sn, and given this behavior of the underfill material, we can easily detect the cold-joint through SAT (Scanning Acoustic Tomography) because of the difference of color distribution reflected in the C-SAM (C-mode scanning acoustic microscopy) image. If the joint interconnection is good, there is filler segregation — a moderate level filler segregation, which can be reflected as grayish-colored area in C-SAM images. In the contrary, the whiter area signifies the absence of filler segregation, and further considered to be due to no contact of Cu pillar and the substrate's pre-solder; thus, signifying Cold-joint defect in this area. With the use of this method, the cold-joint defect can now be detected by SAT during assembly process. However, the separation of resin and filler potentially affects the local properties of the underfill material and may cause the uneven stress distribution. Therefore, temperature cycling test was also performed to confirm that the moderate filler segregation does not have any concern during reliability test.
{"title":"Detection of cold joint defect in copper pillar bumps aided by underfill filler segregation phenomenon","authors":"Chien-Chen Lee, Li Chiun Hung, Pai-Yuan Li, M. Hsieh, Harry Perng, V. Wang","doi":"10.1109/IMPACT.2011.6117222","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117222","url":null,"abstract":"Cold-joint defect has been critically discussed in flip chip interconnections, especially for lead-free solder and Cu pillar bumps in fcFBGA (flip chip fine-pitch BGA). In the case of Cu pillar bump, the only known effective method for cold-joint detection is package Open/Short Test. This study introduces an effective alternative method of Cold-joint detection while during assembly setup stage, which employs the moderate filler segregation phenomenon among Cu pillar bumps, especially for Cu pillar bump without solder cap. For joint connections with Cu-pillar bumps, a voltage separates the underfill material's filler and resin due to the electrode potential difference between Cu and Sn. The filler migrates towards the Sn, and given this behavior of the underfill material, we can easily detect the cold-joint through SAT (Scanning Acoustic Tomography) because of the difference of color distribution reflected in the C-SAM (C-mode scanning acoustic microscopy) image. If the joint interconnection is good, there is filler segregation — a moderate level filler segregation, which can be reflected as grayish-colored area in C-SAM images. In the contrary, the whiter area signifies the absence of filler segregation, and further considered to be due to no contact of Cu pillar and the substrate's pre-solder; thus, signifying Cold-joint defect in this area. With the use of this method, the cold-joint defect can now be detected by SAT during assembly process. However, the separation of resin and filler potentially affects the local properties of the underfill material and may cause the uneven stress distribution. Therefore, temperature cycling test was also performed to confirm that the moderate filler segregation does not have any concern during reliability test.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"16 1","pages":"415-418"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86220942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117247
Tien-Tsorng Shih, Binghua Chen, Win-Der Lee, Mu-Chun Wang
Using polymer core solder ball in ball-grid-array (BGA) package instead of solid solder ball in cost consideration is a feasible choice. Besides the consideration for inter-metallic compound (IMC) between solder ball and carrier substrate, the reliability test for drop test is necessary. Following the commercial specification test conditions, this candidate demonstrates an impressive performance. The uniformity for the test results is also better than that with the control group. The slope value and scale parameter of Weibull distribution adopted in this statistic calculation illustrated the polymer core solder ball in BGA package owned the wonderful bombardment endurance capability, incorporated with the ENEPIG processing recipe for substrate metal finish.
{"title":"Drop test for Sn96.7-Ag3.7 polymer core solder ball in BGA package","authors":"Tien-Tsorng Shih, Binghua Chen, Win-Der Lee, Mu-Chun Wang","doi":"10.1109/IMPACT.2011.6117247","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117247","url":null,"abstract":"Using polymer core solder ball in ball-grid-array (BGA) package instead of solid solder ball in cost consideration is a feasible choice. Besides the consideration for inter-metallic compound (IMC) between solder ball and carrier substrate, the reliability test for drop test is necessary. Following the commercial specification test conditions, this candidate demonstrates an impressive performance. The uniformity for the test results is also better than that with the control group. The slope value and scale parameter of Weibull distribution adopted in this statistic calculation illustrated the polymer core solder ball in BGA package owned the wonderful bombardment endurance capability, incorporated with the ENEPIG processing recipe for substrate metal finish.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"49 1","pages":"184-187"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91183882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117153
Y. Tsai, C. Hsu, K. F. Lin, Y. Chang, H. Hu, T. Chen, C. Chu, M. Chu
We report a brand new technique which is merged thin film fabrication process and packaging technology together to form the shortest thermal dissipation path of LED structure. The effective thermal resistance of the proposed LED was 3.54K/W, which is much better than that of the conventional one 10.8K/W and the operating current can be driven from original 230mA up to 800mA. These results indicate that the LED structure based on our work is useful in improving the performance by enabling great heat dissipation and have higher application potential than conventional one.
{"title":"High thermal dissipation of light emitting diodes by integrating thin film process and packaging technology","authors":"Y. Tsai, C. Hsu, K. F. Lin, Y. Chang, H. Hu, T. Chen, C. Chu, M. Chu","doi":"10.1109/IMPACT.2011.6117153","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117153","url":null,"abstract":"We report a brand new technique which is merged thin film fabrication process and packaging technology together to form the shortest thermal dissipation path of LED structure. The effective thermal resistance of the proposed LED was 3.54K/W, which is much better than that of the conventional one 10.8K/W and the operating current can be driven from original 230mA up to 800mA. These results indicate that the LED structure based on our work is useful in improving the performance by enabling great heat dissipation and have higher application potential than conventional one.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"235 1","pages":"492-494"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89151894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117282
Jan L. Yang, Mei-Ling Wu
This paper summarizes the force calculation at each pitch position for the structure, where a component (overmold, die, and BT) is attached to a PCB (printed circuit board) through an array of solder joints with an external bending moment applied at the ends of PCB. In this paper, the results from the model proposed by E. Suhir [1] are summarized with corrections in the derivation of the equations. Details of the new model will be described including the methodology, the formulation and the simulated results. Comparisons between the two models will be made with discussions. In this new model, each solder joint between the component and the PCB is replaced by a spring with spring constant. Benefiting from the symmetry of the structure, only half of the structure needs to be considered which simplifies the formulation of the problem and saves the computation time dramatically. The variables (unknowns) to be solved are the forces exerted on each spring due to applied external bending moment. In the subsections to come, detailed derivations will be given followed by numerical results. The setup of the new model and it is essentially the same as the Cantilever-intermediate load problem. The forces exerted on each spring will be solved through a system of linearly independent equations governed by the following conditions. All the listed formulas above are for the case when the number of leads is odd. Basically, similar formulas will be used for the case when the number of leads is even. The goal in this paper will be as follows: (a) Suhir's model deals with continuous case. It is clearly seen from the simulation results of Suhir's model that all the curves are smooth no matter how many number of solder joints are involved. The only parameter that is related to the number of joints as defined by Suhir is the spring constant of the elastic attachment. In the new model, we will solve for the force at each position in a discrete sense. That is why the curves are not that smooth when the number of solder joints is small. As the number of the solder joints becomes large (or in other words, the pitch size is small), the two models yield exactly the same results. (b) Mathematically, the new model is simpler and straightforward. The only math involved is solving the linearly independent system of equations. In Suhir's model, however, the solution process starts from solving the 4th order differential equations. Although analytical solutions can be obtained, special attention has to be paid in imposing proper boundary conditions, which might not be trivial.
{"title":"Models for physics of failures analysis during printed circuit board bending","authors":"Jan L. Yang, Mei-Ling Wu","doi":"10.1109/IMPACT.2011.6117282","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117282","url":null,"abstract":"This paper summarizes the force calculation at each pitch position for the structure, where a component (overmold, die, and BT) is attached to a PCB (printed circuit board) through an array of solder joints with an external bending moment applied at the ends of PCB. In this paper, the results from the model proposed by E. Suhir [1] are summarized with corrections in the derivation of the equations. Details of the new model will be described including the methodology, the formulation and the simulated results. Comparisons between the two models will be made with discussions. In this new model, each solder joint between the component and the PCB is replaced by a spring with spring constant. Benefiting from the symmetry of the structure, only half of the structure needs to be considered which simplifies the formulation of the problem and saves the computation time dramatically. The variables (unknowns) to be solved are the forces exerted on each spring due to applied external bending moment. In the subsections to come, detailed derivations will be given followed by numerical results. The setup of the new model and it is essentially the same as the Cantilever-intermediate load problem. The forces exerted on each spring will be solved through a system of linearly independent equations governed by the following conditions. All the listed formulas above are for the case when the number of leads is odd. Basically, similar formulas will be used for the case when the number of leads is even. The goal in this paper will be as follows: (a) Suhir's model deals with continuous case. It is clearly seen from the simulation results of Suhir's model that all the curves are smooth no matter how many number of solder joints are involved. The only parameter that is related to the number of joints as defined by Suhir is the spring constant of the elastic attachment. In the new model, we will solve for the force at each position in a discrete sense. That is why the curves are not that smooth when the number of solder joints is small. As the number of the solder joints becomes large (or in other words, the pitch size is small), the two models yield exactly the same results. (b) Mathematically, the new model is simpler and straightforward. The only math involved is solving the linearly independent system of equations. In Suhir's model, however, the solution process starts from solving the 4th order differential equations. Although analytical solutions can be obtained, special attention has to be paid in imposing proper boundary conditions, which might not be trivial.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"99 1","pages":"474-477"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89274291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117174
S. W. R. Lee
Currently most LED components are made with individual chip packaging technology. The main manufacturing processes follow conventional chip-based IC packaging. In the past several years, there is an uprising trend in the IC industry to migrate from chip-based packaging to wafer level packaging. Therefore, there is a need for LEDs to catch up. This presentation will introduce advanced LED wafer level packaging technologies. The contents will cover key enabling processes such as preparation of silicon sub-mount wafer, implementation of interconnection, deposition of phosphor, wafer level encapsulation, and their integration. The emphasis will be placed on how to achieve high throughput, low cost manufacturing through wafer level packaging.
{"title":"Advanced LED wafer level packaging technologies","authors":"S. W. R. Lee","doi":"10.1109/IMPACT.2011.6117174","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117174","url":null,"abstract":"Currently most LED components are made with individual chip packaging technology. The main manufacturing processes follow conventional chip-based IC packaging. In the past several years, there is an uprising trend in the IC industry to migrate from chip-based packaging to wafer level packaging. Therefore, there is a need for LEDs to catch up. This presentation will introduce advanced LED wafer level packaging technologies. The contents will cover key enabling processes such as preparation of silicon sub-mount wafer, implementation of interconnection, deposition of phosphor, wafer level encapsulation, and their integration. The emphasis will be placed on how to achieve high throughput, low cost manufacturing through wafer level packaging.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"62 1","pages":"71-74"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88679712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117160
H. Okayama, K. Nanbu, T. Kurokawa, Takashi Koushiro
Terminal units such as mobile phones, portable game systems and electronic books, have spread all over the world and advanced to be smaller, more lightweight and thinner every moment. Simultaneously, the inner electronic parts such as batteries, IC packages and connectors were also smaller and thinner. For example, in order to reduce the occupied area and space on the printed circuit board (PCB), some lead flame type IC packages such as SOP(Small Outline Package) and QFP(Quad Flat Package) have changed to leadless type ones such as SON(Small Outline Non-lead), QFN(Quad Flat Non-lead) and LGA. (Land Grid Array) The substrates of such leadless IC packages are usually made of a single metal plate such as a copper, a copper alloy and a nickel and conventionally produced through etching process or plating process. So the designs for the package like the size, the number of terminal and the total thickness are limited. In order to solve such problems, we developed a new manufacturing method, using clad materials which rolled copper (Cu) foil and nickel (Ni) plating layer on electrolysis Cu foil were laminated. In detail, the components were consisting of 18μm to 35μm thickness Cu foil with about 1 um thickness Ni plating layer and around 100μm thickness rolled Cu sheet (Cu/Ni/Cu material). These materials are characterized by the cladding interface between the rolled Cu foil and the Ni plating layer on the electrolysis Cu foil, which is bonded by the surface activated bonding (SAB) method [1, 2, 3]. Namely, the interface is so flat that it is suitable to use for selective etching work [4, 5]. In this paper, we would like to introduce the new IC package manufacturing process with the Cu/Ni/Cu material. This method makes some new package designs possible and achieves high productivity when comparing to the conventional method. We produced various leadless IC packages with the total thickness of 0.25mm to 0.5mm, with the number of 3 to 460 terminals at 1 row to 4 rows for terminals by means of this new method. In addition, in order to evaluate the package performance, we made the package with the total thickness of 0.43mm, with 164 terminals of diameter of 0.25mm at 3 rows and the terminal pitch of 0.5mm. In this sample, heat-tolerance by the solder reflow test with the pre-condition of JEDEC (Joint Electron Device Engineering Council) standard of level 3 was estimated and the package warpage in the range of 25 to 260 degrees Celsius was measured. As the results, the package sample could pass the reflow test of the JEDEC level 3 and the warp of the package was less than 50μm.
{"title":"Leadless IC package with a substrate produced by copper/nickel/copper-3-layer-clad material","authors":"H. Okayama, K. Nanbu, T. Kurokawa, Takashi Koushiro","doi":"10.1109/IMPACT.2011.6117160","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117160","url":null,"abstract":"Terminal units such as mobile phones, portable game systems and electronic books, have spread all over the world and advanced to be smaller, more lightweight and thinner every moment. Simultaneously, the inner electronic parts such as batteries, IC packages and connectors were also smaller and thinner. For example, in order to reduce the occupied area and space on the printed circuit board (PCB), some lead flame type IC packages such as SOP(Small Outline Package) and QFP(Quad Flat Package) have changed to leadless type ones such as SON(Small Outline Non-lead), QFN(Quad Flat Non-lead) and LGA. (Land Grid Array) The substrates of such leadless IC packages are usually made of a single metal plate such as a copper, a copper alloy and a nickel and conventionally produced through etching process or plating process. So the designs for the package like the size, the number of terminal and the total thickness are limited. In order to solve such problems, we developed a new manufacturing method, using clad materials which rolled copper (Cu) foil and nickel (Ni) plating layer on electrolysis Cu foil were laminated. In detail, the components were consisting of 18μm to 35μm thickness Cu foil with about 1 um thickness Ni plating layer and around 100μm thickness rolled Cu sheet (Cu/Ni/Cu material). These materials are characterized by the cladding interface between the rolled Cu foil and the Ni plating layer on the electrolysis Cu foil, which is bonded by the surface activated bonding (SAB) method [1, 2, 3]. Namely, the interface is so flat that it is suitable to use for selective etching work [4, 5]. In this paper, we would like to introduce the new IC package manufacturing process with the Cu/Ni/Cu material. This method makes some new package designs possible and achieves high productivity when comparing to the conventional method. We produced various leadless IC packages with the total thickness of 0.25mm to 0.5mm, with the number of 3 to 460 terminals at 1 row to 4 rows for terminals by means of this new method. In addition, in order to evaluate the package performance, we made the package with the total thickness of 0.43mm, with 164 terminals of diameter of 0.25mm at 3 rows and the terminal pitch of 0.5mm. In this sample, heat-tolerance by the solder reflow test with the pre-condition of JEDEC (Joint Electron Device Engineering Council) standard of level 3 was estimated and the package warpage in the range of 25 to 260 degrees Celsius was measured. As the results, the package sample could pass the reflow test of the JEDEC level 3 and the warp of the package was less than 50μm.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"5 1","pages":"33-36"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81292813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117281
Yung-Wen Wang, Mei-Ling Wu
Microelectronic devices are often subjected to environmental and power cycling thermal loads. Thermal cycling and the shear forces lead to many failures in microelectronic devices. The most common failure is an open in one or more of the input/output (I/O). The open is the result of a cracked or damaged interconnects, whether it is a lead-free solder joint. Thermal cycling can occur for a device being turned on and off, a system containing the device being turned on and off, an environmental load, and so on. The most important issue that must be addressed in order to the critical issue is the magnitude of the shear force on the lead-free solder joint under thermal loading, in other words, how many cycles can a microelectronic device survive before a failure occurs. The shear forces are often caused by the global coefficient of thermal expansion (CTE) mismatch between the component and the printed circuit board (PCB). This can be a cyclic load when the microelectronic device is repeatedly subjected to a range of temperatures. Shear forces in the lead-free solder joints are an important aspect of the microelectronic package failure problem because the shear force is directly related to the microelectronic device life. A failure model can be used to predict the fatigue life of a microelectronic device in terms of cycles to failure. The Vandevelde analytic model [1] for determining shear forces in the lead-free solder joints of electronic devices, which is based on elastic strength of materials principles, is critiqued in this paper. This analytic model is then used to gain insightful information regarding interconnect shear force behavior. The results from this new model were compared to finite element model results to assure the analytic model was accurately capturing the behavior of the forces in the lead-free solder joints. The results from the investigations must be qualified by stating that the assumptions of constant pitch, homogeneous component, and linear elastic materials were utilized. The completion of this new model leads to a more comprehensive solution to the problem of accurately and efficiently characterizing shear forces in the lead-free solder joint of microelectronic packages and ultimately predicting the life of the packages. Conclusions are made concerning the influence of the number of the lead-free solder joints, device geometry, and material properties on the resulting shear forces. Rapid assessment methodologies for efficiently designing a successful microelectronic package are presented in this paper, which can save both time and money in the design process.
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