Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117270
Jin‐Cherng Shyu, Ying-Hui Lai
In order to investigate the heat transfer of different types of heat sinks under non-uniform heating condition, both plate-fin heat sinks and pin-fin heat sinks were tested with a square heat source having length of 45 mm, 10 mm and 4 mm at various frontal air velocities in this study. The results showed that heat sinks with larger heater size yielded higher heat transfer coefficient for both heat sinks. Besides, the increase of heat transfer coefficient was more rapid for heat sink with a larger heater size as the frontal velocity increased.
{"title":"Performance of shrouded pin-fin and plate-fin heat sinks with a concentrated heat source","authors":"Jin‐Cherng Shyu, Ying-Hui Lai","doi":"10.1109/IMPACT.2011.6117270","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117270","url":null,"abstract":"In order to investigate the heat transfer of different types of heat sinks under non-uniform heating condition, both plate-fin heat sinks and pin-fin heat sinks were tested with a square heat source having length of 45 mm, 10 mm and 4 mm at various frontal air velocities in this study. The results showed that heat sinks with larger heater size yielded higher heat transfer coefficient for both heat sinks. Besides, the increase of heat transfer coefficient was more rapid for heat sink with a larger heater size as the frontal velocity increased.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"1 1","pages":"462-465"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90233646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117293
Ching-Feng Yu, Hsien-Chie Cheng, Y. Tsai, Su-Tsai Lu, Wen-Hwa Chen
This study aims at investigating the growth reaction of the Ni3Sn4 IMC during thermocompression bonding process, the anisotropic elastic constants of the IMC, and the effects of the material properties and surface geometry or morphology on the interconnect reliability of a three-dimensional (3D) Chip-on-Chip (CoC) interconnect technology with Cu/Ni/SnAg micro-bumps subject to accelerated thermal cycling (ATC) loading. The research starts from the investigation of the growth reaction of the Ni3Sn4 IMC during thermocompression bonding process through experiment and classical diffusion theory. The relationship between the Ni3Sn4 IMC thickness and bonding temperature/time is derived based on the predicted activation energy of the chemical reaction of the IMC layer by experiment. Next, the elastic stiffness coefficients of single crystal monoclinic Ni3Sn4 are calculated through molecular dynamics (MD) simulation using the polymer consistent force field (PCFF). The degree of anisotropy in the Ni3Sn4 crystal system is also confirmed by the electronic structure of single crystal Ni3Sn4 using first-principles calculation based on density function theory (DFT). For comparison with the published experimental data and also use in the subsequent reliability analysis, the effective elastic properties of polycrystalline Ni3Sn4 are derived using the Voigt-Reuss bound and Voigt-Reuss Hill average based on the calculated elastic stiffness coefficients. At last, 2D plane strain finite element (FE) analysis together with an empirical Coffin-Manson fatigue life prediction model are performed to predict the interconnect reliability of the 3D CoC interconnect technology. The computed results are compared with the ATC experimental data to demonstrate the effectiveness of these two FE models. The dependence of the interconnect reliability on the thickness, material properties and surface geometry or morphology of the Ni3Sn4 IMC is addressed.
{"title":"Influence of IMC surface geometry and material properties on micro-bump reliability of 3D Chip-on-Chip interconnect technology","authors":"Ching-Feng Yu, Hsien-Chie Cheng, Y. Tsai, Su-Tsai Lu, Wen-Hwa Chen","doi":"10.1109/IMPACT.2011.6117293","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117293","url":null,"abstract":"This study aims at investigating the growth reaction of the Ni3Sn4 IMC during thermocompression bonding process, the anisotropic elastic constants of the IMC, and the effects of the material properties and surface geometry or morphology on the interconnect reliability of a three-dimensional (3D) Chip-on-Chip (CoC) interconnect technology with Cu/Ni/SnAg micro-bumps subject to accelerated thermal cycling (ATC) loading. The research starts from the investigation of the growth reaction of the Ni3Sn4 IMC during thermocompression bonding process through experiment and classical diffusion theory. The relationship between the Ni3Sn4 IMC thickness and bonding temperature/time is derived based on the predicted activation energy of the chemical reaction of the IMC layer by experiment. Next, the elastic stiffness coefficients of single crystal monoclinic Ni3Sn4 are calculated through molecular dynamics (MD) simulation using the polymer consistent force field (PCFF). The degree of anisotropy in the Ni3Sn4 crystal system is also confirmed by the electronic structure of single crystal Ni3Sn4 using first-principles calculation based on density function theory (DFT). For comparison with the published experimental data and also use in the subsequent reliability analysis, the effective elastic properties of polycrystalline Ni3Sn4 are derived using the Voigt-Reuss bound and Voigt-Reuss Hill average based on the calculated elastic stiffness coefficients. At last, 2D plane strain finite element (FE) analysis together with an empirical Coffin-Manson fatigue life prediction model are performed to predict the interconnect reliability of the 3D CoC interconnect technology. The computed results are compared with the ATC experimental data to demonstrate the effectiveness of these two FE models. The dependence of the interconnect reliability on the thickness, material properties and surface geometry or morphology of the Ni3Sn4 IMC is addressed.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"32 1","pages":"210-213"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87913553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117278
P. Huang, M. Tsai
While the semiconductor packages are evolving toward smaller package size and higher performance, the 3D IC or stacked-die packages are gaining popular. For these applications, IC wafers have to be ground to be relatively thin and the dies cut from these wafers have to possess sufficient strength against high stresses resulting from process handling, reliability testing, and operation. Hence, the strength of the dies, especially for the thin dies, has to be determined to ensure good reliability of the packages. Three-point bending test is widely used for measuring die strength; however the feasibility of the test is still questionable for determining strength of relatively thin dies. Meanwhile, the pin-on-elastic-foundation (PoEF) test [1] with special feature of bi-axial stress mode and elimination of the die edge effect has been proved more simple and reliable, but not for thin dies. In this study, the three-point bending test (under un-axial stress state) and the PoEF test (under bi-axial stress state) are evaluated for aiming at the thin-die strength determination which may features geometrical and contact nonlinearities. The feasibility of both test methods with their linear theories is evaluated by a nonlinear finite element method (NFEM) with taking into account geometrical and contact nonlinearities. The results show that these nonlinearities would cause an error of strength prediction by the linear beam theory for thin dies. For three-point bending test, the concept of moment equilibrium associated with the fitting equation for Fx extracted from the NFEM simulation is proposed and proved workable with good accuracy. The similar problem is faced in the PoEF test. The fitting equations based on the NFEM results are also proposed for calculating the strength of thin dies with better accuracy than theoretical formulation. Therefore, the nonlinearities has to be taken into account for both tests when the thin silicon dies are tested for strength.
{"title":"Nonlinearities in thin-silicon die strength tests","authors":"P. Huang, M. Tsai","doi":"10.1109/IMPACT.2011.6117278","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117278","url":null,"abstract":"While the semiconductor packages are evolving toward smaller package size and higher performance, the 3D IC or stacked-die packages are gaining popular. For these applications, IC wafers have to be ground to be relatively thin and the dies cut from these wafers have to possess sufficient strength against high stresses resulting from process handling, reliability testing, and operation. Hence, the strength of the dies, especially for the thin dies, has to be determined to ensure good reliability of the packages. Three-point bending test is widely used for measuring die strength; however the feasibility of the test is still questionable for determining strength of relatively thin dies. Meanwhile, the pin-on-elastic-foundation (PoEF) test [1] with special feature of bi-axial stress mode and elimination of the die edge effect has been proved more simple and reliable, but not for thin dies. In this study, the three-point bending test (under un-axial stress state) and the PoEF test (under bi-axial stress state) are evaluated for aiming at the thin-die strength determination which may features geometrical and contact nonlinearities. The feasibility of both test methods with their linear theories is evaluated by a nonlinear finite element method (NFEM) with taking into account geometrical and contact nonlinearities. The results show that these nonlinearities would cause an error of strength prediction by the linear beam theory for thin dies. For three-point bending test, the concept of moment equilibrium associated with the fitting equation for Fx extracted from the NFEM simulation is proposed and proved workable with good accuracy. The similar problem is faced in the PoEF test. The fitting equations based on the NFEM results are also proposed for calculating the strength of thin dies with better accuracy than theoretical formulation. Therefore, the nonlinearities has to be taken into account for both tests when the thin silicon dies are tested for strength.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"39 1","pages":"91-95"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76159098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117268
H. Tseng, Wen-Young Li, Tze-Wei Chen
A variety of complex configurations have been attempted to enhance the thermal stability of modern heterojunction bipolar transistors (HBTs). Existing structures for improving thermal management of power HBTs, nevertheless, are not small enough to realize miniaturized power amplifiers in high-efficiency cellular phones. A highly compact heat-spreading structure (HSS) simulated by the genetic algorithm (GA) is proposed, and the demonstration on multi-finger InGaP/GaAs collector-up HBTs, which show noticeable power performance, is presented. Comparatively, the improved results indicate that the thermal resistance can be substantially decreased by 50%, and a power-added efficiency (PAE) more than 55% is achieved from this novel design
{"title":"Improving thermal management of multi-finger InGaP collector-up HBTs with a highly compact heat-spreading structure by GA","authors":"H. Tseng, Wen-Young Li, Tze-Wei Chen","doi":"10.1109/IMPACT.2011.6117268","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117268","url":null,"abstract":"A variety of complex configurations have been attempted to enhance the thermal stability of modern heterojunction bipolar transistors (HBTs). Existing structures for improving thermal management of power HBTs, nevertheless, are not small enough to realize miniaturized power amplifiers in high-efficiency cellular phones. A highly compact heat-spreading structure (HSS) simulated by the genetic algorithm (GA) is proposed, and the demonstration on multi-finger InGaP/GaAs collector-up HBTs, which show noticeable power performance, is presented. Comparatively, the improved results indicate that the thermal resistance can be substantially decreased by 50%, and a power-added efficiency (PAE) more than 55% is achieved from this novel design","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"14 1","pages":"100-102"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87284339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117219
H. Ru, V. Wei, T. Jiang, M. Chiu
Direct Plated Copper (DPC) on ceramic substrate is a patented process by Tong Hsing that has been utilized as an outstanding solution for high brightness LED (HBLED) assembly for over ten years. DPC substrate offers several key attributes such as good TCE match to semiconductor materials, high thermal conductivity, low electrical resistance conductor traces, good reliable at high temperatures (>340°C), precise features, and ease of large format assembly. In additions, this ceramic solution also achieves fine line resolution allowing high density of devices and circuitry, proven reliability, mechanically rugged ceramic construction, and reasonable cost. DPC is implanted with seed layers on aluminum nitride (AlN) or alumina (Al2O3) by sputtering. Then photolithographic procedures are utilized to develop the circuit pattern. Then Cu and Ni layers are plated on top of seed layers to form a solid structure for circuitry. Based on ceramic and thick copper construction, the DPC substrate provides outstanding thermal and electrical performance for applications in high power or high current devices.
{"title":"Direct plated copper technology for high brightness LED packaging","authors":"H. Ru, V. Wei, T. Jiang, M. Chiu","doi":"10.1109/IMPACT.2011.6117219","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117219","url":null,"abstract":"Direct Plated Copper (DPC) on ceramic substrate is a patented process by Tong Hsing that has been utilized as an outstanding solution for high brightness LED (HBLED) assembly for over ten years. DPC substrate offers several key attributes such as good TCE match to semiconductor materials, high thermal conductivity, low electrical resistance conductor traces, good reliable at high temperatures (>340°C), precise features, and ease of large format assembly. In additions, this ceramic solution also achieves fine line resolution allowing high density of devices and circuitry, proven reliability, mechanically rugged ceramic construction, and reasonable cost. DPC is implanted with seed layers on aluminum nitride (AlN) or alumina (Al2O3) by sputtering. Then photolithographic procedures are utilized to develop the circuit pattern. Then Cu and Ni layers are plated on top of seed layers to form a solid structure for circuitry. Based on ceramic and thick copper construction, the DPC substrate provides outstanding thermal and electrical performance for applications in high power or high current devices.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"18 1","pages":"311-314"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85740454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117220
Bor-Tsuen Wang, Yau-Chang Lee, Y. Lai, Chang-Lin Yeh, Ying-Chih Lee
Coupling effects of both thermal and vibration loadings on printed circuit board (PCB) are of interest. This paper aims to study the random vibration excitation of PCB with four heating ICs that are used to emulate the temperature elevation during operations. Two levels of heating conditions as well as without heating are considered in this work. The vibration tests according to JESD22-B103-B are carried out to measure the random vibration response of PCB under the conditions of both with and without heating. The finite element (FE) model of PCB with heating ICs is constructed and performed spectrum response analysis with and without thermal effects. The temperature distributions on PCB are first verified and shown good agreement between finite element analysis (FEA) and experiments. The power spectral density (PSD) functions of the acceleration on the PCB in heating are also obtained and compared for both FEA and experiments. The RMS accelerations on the PCB can be calculated and matched well between the analytical and experimental results. The fatigue evaluation due to coupling loadings from thermal and vibration effects on the PCB is also addressed. This work presents the systematic approaches in studying spectrum response analysis of PCB with both thermal and vibration coupling loads and shows a very good agreement results between FEA and experiments.
{"title":"Spectrum response analysis for PCB with heating ICs in different heating conditions","authors":"Bor-Tsuen Wang, Yau-Chang Lee, Y. Lai, Chang-Lin Yeh, Ying-Chih Lee","doi":"10.1109/IMPACT.2011.6117220","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117220","url":null,"abstract":"Coupling effects of both thermal and vibration loadings on printed circuit board (PCB) are of interest. This paper aims to study the random vibration excitation of PCB with four heating ICs that are used to emulate the temperature elevation during operations. Two levels of heating conditions as well as without heating are considered in this work. The vibration tests according to JESD22-B103-B are carried out to measure the random vibration response of PCB under the conditions of both with and without heating. The finite element (FE) model of PCB with heating ICs is constructed and performed spectrum response analysis with and without thermal effects. The temperature distributions on PCB are first verified and shown good agreement between finite element analysis (FEA) and experiments. The power spectral density (PSD) functions of the acceleration on the PCB in heating are also obtained and compared for both FEA and experiments. The RMS accelerations on the PCB can be calculated and matched well between the analytical and experimental results. The fatigue evaluation due to coupling loadings from thermal and vibration effects on the PCB is also addressed. This work presents the systematic approaches in studying spectrum response analysis of PCB with both thermal and vibration coupling loads and shows a very good agreement results between FEA and experiments.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"5 1","pages":"198-201"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85057100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117265
De-Shin Liu, Zi-Hau Chen, Chung-Yu Lee
Through Silicon Via Multi-Chip Packaging (TSV MCP) is the current important direction for advance packaging technique. TSV/MCP need to support with thin wafer so that the stacking dies could maintain the spacing limitation, however one failure die could cause whole packaging failure that could lead to lower the yield rate and increasing the manufacturing cost. To realize the relationship between the manufacturing condition and the thin wafer strength, specialized experimental methods and tools must be developed to carry out thin wafer breaking strain/stress. In this paper, newly developed Ball-On-Ring test were set up and carried out to measure the force-displacement relation of various wafer thickness. The results from the testing then coupled with finite element analysis to reverse finding the breaking stress/strain as a function of wafer thickness. The die strength limit from this research can further support the engineer to evaluate reliability performance of the TSV MCP.
{"title":"Evaluate breaking strength of thin silicon die by ball-on-ring microforce tests and finite element analysis","authors":"De-Shin Liu, Zi-Hau Chen, Chung-Yu Lee","doi":"10.1109/IMPACT.2011.6117265","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117265","url":null,"abstract":"Through Silicon Via Multi-Chip Packaging (TSV MCP) is the current important direction for advance packaging technique. TSV/MCP need to support with thin wafer so that the stacking dies could maintain the spacing limitation, however one failure die could cause whole packaging failure that could lead to lower the yield rate and increasing the manufacturing cost. To realize the relationship between the manufacturing condition and the thin wafer strength, specialized experimental methods and tools must be developed to carry out thin wafer breaking strain/stress. In this paper, newly developed Ball-On-Ring test were set up and carried out to measure the force-displacement relation of various wafer thickness. The results from the testing then coupled with finite element analysis to reverse finding the breaking stress/strain as a function of wafer thickness. The die strength limit from this research can further support the engineer to evaluate reliability performance of the TSV MCP.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"92 1","pages":"188-190"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87994920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117227
L. Hung, Y. Pai, Men Yeh Chiang, K. Hung, D. Jiang, C. Huang
In semiconductor packaging, wire bonding is the main technology for electrical connections between chip and leadframe or substrate. Gold wire bonding has the advantages of a fast bonding process, excellent electrical property, and stable chemical property. It has been widely used in various electronic packages, such as chip scale package (CSP) and ball grid array (BGA). Gold prices have risen significantly over the last few years. Many manufactures have been investigating ways to replace the conventional gold wire various new material. Copper wire bonding is an alternative interconnection technology. Compared with gold wire, Cu wire is better than gold with respect to electrical conductivity. The inherent stiffness of the copper wire also makes long wire with small diameters more resistant to wire sweep during molding. There are also some problems with Cu bonding process: (1) Copper easily oxidizes in air. The application of copper wire coated with palladium is a solution to prevent copper oxidation during the bonding process. (2) The higher hardness of wire generally requires higher ultrasonic power and bond force to bond on metal. It also lead to high risk of cratering for ball bonding and tearing for wedge bond. This paper reports a study on the influence wire material, surface finish hardness and bonding machine parameter. In this study, 0.7mil Pd coated Cu wire was bonded on two kinds of surface finish, as electro-plating Nickel and Gold, and Electroless Nickel, Electroless Palladium and Immersion Gold (ENEPIG). Its purity is 4N. The thickness of Pd coating was less than 0.2um. The surface finish characteristics were examined using a scanning electron microscope (SEM). The noncontact optical profiler was used to measure surface finish roughness. Hardness was measured, using microhardness test. Thermosonic Pd coated Cu wire wedge bonding was preformed on a wedge bonder equipped with a kit to forming gas. The wire bonding process window for each surface finish was established using various combination of bond force and power. Bonder machine alarm rate, wire pull test and wedge bonding appearance were performed to measure the quality for Pd coated Cu wire bonded on three kinds of surface finish. Cross section sample was prepared Focused Ion Beam (FIB). Then, it was observed using scanning electron microscope to discuss wedge bonding mechanism.
{"title":"Investigation of ultrasonic palladium coated copper wire wedge bonding on different surface finish","authors":"L. Hung, Y. Pai, Men Yeh Chiang, K. Hung, D. Jiang, C. Huang","doi":"10.1109/IMPACT.2011.6117227","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117227","url":null,"abstract":"In semiconductor packaging, wire bonding is the main technology for electrical connections between chip and leadframe or substrate. Gold wire bonding has the advantages of a fast bonding process, excellent electrical property, and stable chemical property. It has been widely used in various electronic packages, such as chip scale package (CSP) and ball grid array (BGA). Gold prices have risen significantly over the last few years. Many manufactures have been investigating ways to replace the conventional gold wire various new material. Copper wire bonding is an alternative interconnection technology. Compared with gold wire, Cu wire is better than gold with respect to electrical conductivity. The inherent stiffness of the copper wire also makes long wire with small diameters more resistant to wire sweep during molding. There are also some problems with Cu bonding process: (1) Copper easily oxidizes in air. The application of copper wire coated with palladium is a solution to prevent copper oxidation during the bonding process. (2) The higher hardness of wire generally requires higher ultrasonic power and bond force to bond on metal. It also lead to high risk of cratering for ball bonding and tearing for wedge bond. This paper reports a study on the influence wire material, surface finish hardness and bonding machine parameter. In this study, 0.7mil Pd coated Cu wire was bonded on two kinds of surface finish, as electro-plating Nickel and Gold, and Electroless Nickel, Electroless Palladium and Immersion Gold (ENEPIG). Its purity is 4N. The thickness of Pd coating was less than 0.2um. The surface finish characteristics were examined using a scanning electron microscope (SEM). The noncontact optical profiler was used to measure surface finish roughness. Hardness was measured, using microhardness test. Thermosonic Pd coated Cu wire wedge bonding was preformed on a wedge bonder equipped with a kit to forming gas. The wire bonding process window for each surface finish was established using various combination of bond force and power. Bonder machine alarm rate, wire pull test and wedge bonding appearance were performed to measure the quality for Pd coated Cu wire bonded on three kinds of surface finish. Cross section sample was prepared Focused Ion Beam (FIB). Then, it was observed using scanning electron microscope to discuss wedge bonding mechanism.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"36 1","pages":"122-125"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83000889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117264
J. Chyi, William Wang, Vivi Chung, G. Shen
As the trend in electronic devices keeps striding towards minimization, high speed, high resolution, and multi-functions, the electromigration problem in chip packages becomes unavoidable, which creates an unintended electrical connection between terminals and causes electrical short, especially for high voltage products with COF package application. The aim of this study is to find a solution to prevent the phenomena from occurring. Therefore, we introduce the methodology of “PI under fill” in the gold bumped wafers to prevent the Au-migration-induced short-circuit failure in the COF packages since the defect mode of “Au migration” is now seriously affecting the advance of the consumer product development. However, it is difficult to detect the defect mode during the whole packaging process line since only an extremely low content of the migrating ions exists in the meanwhile. Currently, some fine pitch cases have redesigned the bonding pads/bumps from linear to stagger layout in order to enlarge the bump spaces. However, this kind of design has its limitation due to higher pin count and reduced chip size requirements for the next generation devices. In this study, two lots of bumped wafers were taken for experiment by coating PI in the bump spaces to form electrical insulation between bumps. The results show that the PI appearance meets our expectation and with the application of the PI under fill in the bump spaces the COF packages can still maintain normal performance.
{"title":"PI under fill effect study for gold migration improvement in the high voltage COF assembly application","authors":"J. Chyi, William Wang, Vivi Chung, G. Shen","doi":"10.1109/IMPACT.2011.6117264","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117264","url":null,"abstract":"As the trend in electronic devices keeps striding towards minimization, high speed, high resolution, and multi-functions, the electromigration problem in chip packages becomes unavoidable, which creates an unintended electrical connection between terminals and causes electrical short, especially for high voltage products with COF package application. The aim of this study is to find a solution to prevent the phenomena from occurring. Therefore, we introduce the methodology of “PI under fill” in the gold bumped wafers to prevent the Au-migration-induced short-circuit failure in the COF packages since the defect mode of “Au migration” is now seriously affecting the advance of the consumer product development. However, it is difficult to detect the defect mode during the whole packaging process line since only an extremely low content of the migrating ions exists in the meanwhile. Currently, some fine pitch cases have redesigned the bonding pads/bumps from linear to stagger layout in order to enlarge the bump spaces. However, this kind of design has its limitation due to higher pin count and reduced chip size requirements for the next generation devices. In this study, two lots of bumped wafers were taken for experiment by coating PI in the bump spaces to form electrical insulation between bumps. The results show that the PI appearance meets our expectation and with the application of the PI under fill in the bump spaces the COF packages can still maintain normal performance.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"187 ","pages":"276-279"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91447007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117161
Shao Song, F. Zhu, Wei Zhang, Sheng Liu
In this paper, warpage of various substrates are measured with a noncontact shadow moiré technology. Meanwhile, phase-shifting technology is applied to the analysis of fringe pattern images of substrates obtained by shadow moiré. Sensitivity of the fringe pattern analysis is demonstrated to be significantly increased. Two types of samples, QFN (Quad Flat No-lead Package) metal substrates, BGA (Ball Grid Array) substrates are measured by the system. This paper will show that the presented system is a powerful tool for measuring the warpage of various substrates.
{"title":"Warpage measurement of various substrates based on white light shadow moiré technology","authors":"Shao Song, F. Zhu, Wei Zhang, Sheng Liu","doi":"10.1109/IMPACT.2011.6117161","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117161","url":null,"abstract":"In this paper, warpage of various substrates are measured with a noncontact shadow moiré technology. Meanwhile, phase-shifting technology is applied to the analysis of fringe pattern images of substrates obtained by shadow moiré. Sensitivity of the fringe pattern analysis is demonstrated to be significantly increased. Two types of samples, QFN (Quad Flat No-lead Package) metal substrates, BGA (Ball Grid Array) substrates are measured by the system. This paper will show that the presented system is a powerful tool for measuring the warpage of various substrates.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"129 1","pages":"389-392"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77081874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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