Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117224
Pei-Lun Hsieh, Kwang-Lung Lin
Electroless NiP deposit has been frequently mentioned as the barrier laer for Cu substrate or metallization for the soldering process. The NiP deposit is solderable with many solders at appropriate temperature and operation condition. The present study attempted to investigate the wetting behavior of the Sn3Ag solder on the electroless NiP with wetting balance at 250°C and 270°C. The cross section of the wetting specimen was further investigated for the interaction and the interfacial microstructure between the solder and the NiP/Cu substrate. The interface was composed of Ni3Sn4 and Ni3P compound layers. A Ni-Sn-P layer was detected between these two compound layers. The thickness of these layers was analyzed for the growth kinetics. The growth of these layers were found to follow an empirical power law log h(thickness) = log k(constant) + n log t(time). The variation in n values was discussed in relating to the growth mechanism of these two layers.
化学NiP镀层作为铜衬底的阻挡层或焊接过程中的金属化层经常被提及。在适当的温度和操作条件下，可与多个焊料进行焊接。在250°C和270°C条件下，研究了Sn3Ag钎料在化学NiP上的润湿行为。进一步研究了润湿试样的横截面，以研究焊料与NiP/Cu衬底之间的相互作用和界面微观结构。界面由Ni3Sn4和Ni3P复合层组成。在这两个复合层之间检测到Ni-Sn-P层。对这些层的厚度进行了生长动力学分析。发现这些层的生长遵循经验幂律log h(厚度)= log k(常数)+ n log t(时间)。讨论了n值的变化与这两层生长机制的关系。
{"title":"The wetting interaction between electroless NiP deposit/Cu substrate and SnAg solder","authors":"Pei-Lun Hsieh, Kwang-Lung Lin","doi":"10.1109/IMPACT.2011.6117224","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117224","url":null,"abstract":"Electroless NiP deposit has been frequently mentioned as the barrier laer for Cu substrate or metallization for the soldering process. The NiP deposit is solderable with many solders at appropriate temperature and operation condition. The present study attempted to investigate the wetting behavior of the Sn3Ag solder on the electroless NiP with wetting balance at 250°C and 270°C. The cross section of the wetting specimen was further investigated for the interaction and the interfacial microstructure between the solder and the NiP/Cu substrate. The interface was composed of Ni3Sn4 and Ni3P compound layers. A Ni-Sn-P layer was detected between these two compound layers. The thickness of these layers was analyzed for the growth kinetics. The growth of these layers were found to follow an empirical power law log h(thickness) = log k(constant) + n log t(time). The variation in n values was discussed in relating to the growth mechanism of these two layers.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"84 1","pages":"29-32"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89887588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117232
Chun‐Fu Chen, I-Wei Li
The nonlinear geometrical responses in large deflection of an un-symmetrically piezo-electric layered plate under initial tension are studied. von Karman plate theory for large deflection is utilized and extended to an un-symmetrically layered plate including a piezoelectric layer. The nonlinear governing equations are derived, first, in a non-dimensional form in terms of lateral slope and radial force resultant. These equations are solved u sin g a numerical finite difference method with the aid of the clamped-ended boundary conditions of the problem and an iteration procedure, by taking the associated linear analytical solution of lateral slope as the initial guess. For an early monolithic plate under a very low applied voltage, the results agree well with available solutions for a single-layered case due to uniform lateral load in literature and thus the present approach is validated. For a two-layered un-symmetric plate made of typical silicon-based materials, the results show that piezoelectric effect seems to be apparent only up to a moderate initial tension and a moderate lateral pressure. Under this circumstance, the higher the applied voltage, the greater the central deflection; and hence the plate may transit to a membrane in a relatively low pretension condition. For a relatively high pretension or a severe lateral load, however, the piezoelectric effect becomes insignificant. Moreover, the effects of initial tension and lateral load may merge to become dominant, yielding nearly the same responses, regardless of the magnitude of the applied voltage.
{"title":"Nonlinear geometrical responses in large deflection of un-symmetrically layered piezo-electric plate under initial tension","authors":"Chun‐Fu Chen, I-Wei Li","doi":"10.1109/IMPACT.2011.6117232","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117232","url":null,"abstract":"The nonlinear geometrical responses in large deflection of an un-symmetrically piezo-electric layered plate under initial tension are studied. von Karman plate theory for large deflection is utilized and extended to an un-symmetrically layered plate including a piezoelectric layer. The nonlinear governing equations are derived, first, in a non-dimensional form in terms of lateral slope and radial force resultant. These equations are solved u sin g a numerical finite difference method with the aid of the clamped-ended boundary conditions of the problem and an iteration procedure, by taking the associated linear analytical solution of lateral slope as the initial guess. For an early monolithic plate under a very low applied voltage, the results agree well with available solutions for a single-layered case due to uniform lateral load in literature and thus the present approach is validated. For a two-layered un-symmetric plate made of typical silicon-based materials, the results show that piezoelectric effect seems to be apparent only up to a moderate initial tension and a moderate lateral pressure. Under this circumstance, the higher the applied voltage, the greater the central deflection; and hence the plate may transit to a membrane in a relatively low pretension condition. For a relatively high pretension or a severe lateral load, however, the piezoelectric effect becomes insignificant. Moreover, the effects of initial tension and lateral load may merge to become dominant, yielding nearly the same responses, regardless of the magnitude of the applied voltage.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"14 1","pages":"157-160"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78129503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117233
Jingyang Wu, Liao Meng-Chieh, Luo Tzeng-Cherng, Huang Te-Chun
As the demand grows for multiple functionality and high density, the reliability of plated-through hole becomes a concern because of the difficulty in small window plating. The reliability of PTH was affected by many factors, for instance, drilled diameter and plated thickness. In this study, we mainly concentrate on the impact of PTH diameter on it. The diameter of PTHs engaged in this experiment ranges from 10 mil to 60 mil on the multilayer printed circuit boards with 96 mil thickness. All the test boards are subjected to thermal cycle test for 6000 cycles: from 0°C to 100°C with 10°C per minute ramp rate. The failure data was analyzed by using two-parameter Weibull distribution. The experimental results show that diameter of PTH affect the reliability much more at small PTH size. In order to understand the failure modes, cross section was applied to failed PTHs, which show the PTH failures under thermal stress in this study were due to cracks at the middle of PTH barrel.
随着多功能性和高密度化需求的增长，小窗口电镀难度大，电镀通孔的可靠性成为人们关注的问题。PTH的可靠性受钻孔直径、镀层厚度等因素的影响。在本研究中，我们主要关注PTH直径对其的影响。在厚度为96 mil的多层印刷电路板上，实验所采用的PTHs直径范围为10 mil ~ 60 mil。所有测试板都经过6000个循环的热循环测试:从0°C到100°C，斜坡速率为每分钟10°C。采用双参数威布尔分布对失效数据进行分析。实验结果表明，当PTH尺寸较小时，PTH直径对可靠性的影响更大。为了了解PTH的破坏模式，我们对破坏的PTH进行了截面分析，结果表明，本研究中PTH在热应力作用下的破坏是由于PTH筒体中部的裂纹造成的。
{"title":"Comparison the reliability of small plated-through hole with different diameters under thermal stress","authors":"Jingyang Wu, Liao Meng-Chieh, Luo Tzeng-Cherng, Huang Te-Chun","doi":"10.1109/IMPACT.2011.6117233","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117233","url":null,"abstract":"As the demand grows for multiple functionality and high density, the reliability of plated-through hole becomes a concern because of the difficulty in small window plating. The reliability of PTH was affected by many factors, for instance, drilled diameter and plated thickness. In this study, we mainly concentrate on the impact of PTH diameter on it. The diameter of PTHs engaged in this experiment ranges from 10 mil to 60 mil on the multilayer printed circuit boards with 96 mil thickness. All the test boards are subjected to thermal cycle test for 6000 cycles: from 0°C to 100°C with 10°C per minute ramp rate. The failure data was analyzed by using two-parameter Weibull distribution. The experimental results show that diameter of PTH affect the reliability much more at small PTH size. In order to understand the failure modes, cross section was applied to failed PTHs, which show the PTH failures under thermal stress in this study were due to cracks at the middle of PTH barrel.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"21 1","pages":"161-164"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72644780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117165
M. Hoshiyama, M. Hasegawa, T. Sato, H. Yoshii, O. Suzuki, K. Kotaka, T. Nagasaka, A. Horibe, Marie-Claude Paquet, M. Gaynes, C. Feger, K. Sakuma, J. Knickerbocker, Y. Orii, K. Terada, K. Ishikawa, Y. Hirayama
We developed vacuum underfill (VCUF) technology for large die (>18 × 18 mm) with fine pitch area array bumps (< 150 μm pitch) to solve a critical underfill void issue. Material development and process optimization are the keys to realize a stable process for future package. It was also confirmed that the newly developed underfill materials have good reliability on the large die package with vacuum assisted underfill process.
{"title":"Vacuum underfill technology for advanced packaging (IMPACT 2011)","authors":"M. Hoshiyama, M. Hasegawa, T. Sato, H. Yoshii, O. Suzuki, K. Kotaka, T. Nagasaka, A. Horibe, Marie-Claude Paquet, M. Gaynes, C. Feger, K. Sakuma, J. Knickerbocker, Y. Orii, K. Terada, K. Ishikawa, Y. Hirayama","doi":"10.1109/IMPACT.2011.6117165","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117165","url":null,"abstract":"We developed vacuum underfill (VCUF) technology for large die (>18 × 18 mm) with fine pitch area array bumps (< 150 μm pitch) to solve a critical underfill void issue. Material development and process optimization are the keys to realize a stable process for future package. It was also confirmed that the newly developed underfill materials have good reliability on the large die package with vacuum assisted underfill process.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"17 1","pages":"42-46"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85110412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117234
C. H. Chen, Y. F. Chen, T. Lin, Jerry Lee, Y. H. Lin, S. Chiu
The trend of semiconductor advance packaging development is toward fine pitch and high I/O density. Wafer level package is good way to resolve fine pitch and high I/O density IC productions, especially package tape of Wafer Level Chip Scale Package (WLCSP). In traditional bumping process, such as printing [1], electric-plating [2] and ball mount [3–5], it is done by producing bumps on wafers. The paste printing technologies are very versatile with respect to the alloy composition that can be use, but is limited to pitches around 200um for 100um tall bumps. The electric-plating technique is somewhat limited for use in smaller facilities due to the high capital and operation costs. In addition, ternary alloys, like SnAgCu are difficult to plate with consistent results. There is also a practical upper limit to the size of the bump that can be produced, and most applications rare for fine pitch bumping. Ball mount technology uses performed solder spheres dropping through a metal template onto wafer at once. This technology is directly producing bumps on wafer which with high throughput and consistent bump results. Ball mounts process without using electric-plating electrolyte decrease cost and chemical pollution. This technique is applicable for many applications but there are several issues are associated with this technology that limits its widespread use in high volume and high yield applications. These limitations include of there is a practical lower limit to the size of sphere that can be dropped, the stencil between the performed solder spheres and the wafer can fail, causing a release of all the spheres into the tool (often referred to as bursts or escapes), and the yields are statistically low. To get high I/O density IC request, the trend of WLCSP I/O pad distributed design is toward to reduce I/O pitch and increase I/O density, and therefore impact solder ball size application of ball mount process, WLCSP Micro-ball mount technology is requested. There are several issues are associated with this technology that certain ball dropping position and escape issue. The most important factors associated with performance of Micro-ball mount technology are accurate dropping parameter, stencil quality and reflow condition. In this paper, we successfully produced WLCSP Micro-ball which diameter lower than 100um with bump pitch 130um onto 300mm wafers. Yield more than 99.99% without missing bump and bridge bump were realized for placing 70um spheres onto wafers with ∼2KK I/Os.
{"title":"Development of Micro-ball placement technology for WLCSP","authors":"C. H. Chen, Y. F. Chen, T. Lin, Jerry Lee, Y. H. Lin, S. Chiu","doi":"10.1109/IMPACT.2011.6117234","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117234","url":null,"abstract":"The trend of semiconductor advance packaging development is toward fine pitch and high I/O density. Wafer level package is good way to resolve fine pitch and high I/O density IC productions, especially package tape of Wafer Level Chip Scale Package (WLCSP). In traditional bumping process, such as printing [1], electric-plating [2] and ball mount [3–5], it is done by producing bumps on wafers. The paste printing technologies are very versatile with respect to the alloy composition that can be use, but is limited to pitches around 200um for 100um tall bumps. The electric-plating technique is somewhat limited for use in smaller facilities due to the high capital and operation costs. In addition, ternary alloys, like SnAgCu are difficult to plate with consistent results. There is also a practical upper limit to the size of the bump that can be produced, and most applications rare for fine pitch bumping. Ball mount technology uses performed solder spheres dropping through a metal template onto wafer at once. This technology is directly producing bumps on wafer which with high throughput and consistent bump results. Ball mounts process without using electric-plating electrolyte decrease cost and chemical pollution. This technique is applicable for many applications but there are several issues are associated with this technology that limits its widespread use in high volume and high yield applications. These limitations include of there is a practical lower limit to the size of sphere that can be dropped, the stencil between the performed solder spheres and the wafer can fail, causing a release of all the spheres into the tool (often referred to as bursts or escapes), and the yields are statistically low. To get high I/O density IC request, the trend of WLCSP I/O pad distributed design is toward to reduce I/O pitch and increase I/O density, and therefore impact solder ball size application of ball mount process, WLCSP Micro-ball mount technology is requested. There are several issues are associated with this technology that certain ball dropping position and escape issue. The most important factors associated with performance of Micro-ball mount technology are accurate dropping parameter, stencil quality and reflow condition. In this paper, we successfully produced WLCSP Micro-ball which diameter lower than 100um with bump pitch 130um onto 300mm wafers. Yield more than 99.99% without missing bump and bridge bump were realized for placing 70um spheres onto wafers with ∼2KK I/Os.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"9 1","pages":"140-143"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85154596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117272
W. Lin, Chen-I Chao, Y. Tzou, H. Chang, Paul W. Wang
A multipurpose of the performance measuring system for the phase change heat transport device such as heat pipe, vapor chamber and defrost plate was designed in this study. The characteristic of this measuring system was using thermal electrical chip (T.E.C.) as the condenser. This paper also present experimental measurement of performance of a vapor chamber (VC), heat pipe and defrost plate. The vapor chamber, with square sides of 50 × 50mm and thickness of 3.5mm and 6mm, was sandwiched between a heater block and a cooling plate located on the evaporator and the condenser surface respectively. The performance of the vapor chamber was investigated by determining the thermal resistance over a heat input range of 1 to 5W in natural convection test with the condenser opens at ambient environment and up to 40W in force convection with the condenser held at constant temperature. The experimental results show that the Maximum heat dissipated ability was the same compare with the new design measuring system and the traditional heat pipe performance measuring system with a water jacket as the cooling condenser. The thermal resistance in natural convection condition for the axial direction was around 0.1°C/W, while the spray thermal resistance was 0.12°C/W. For the defrost plate, the axial thermal resistance was 0.17°C/W and 0.18°C/W for the spray thermal resistance.
{"title":"The development of the performance measuring system for the phase change heat transport device-heat pipe, vapor chamber and defrost plate","authors":"W. Lin, Chen-I Chao, Y. Tzou, H. Chang, Paul W. Wang","doi":"10.1109/IMPACT.2011.6117272","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117272","url":null,"abstract":"A multipurpose of the performance measuring system for the phase change heat transport device such as heat pipe, vapor chamber and defrost plate was designed in this study. The characteristic of this measuring system was using thermal electrical chip (T.E.C.) as the condenser. This paper also present experimental measurement of performance of a vapor chamber (VC), heat pipe and defrost plate. The vapor chamber, with square sides of 50 × 50mm and thickness of 3.5mm and 6mm, was sandwiched between a heater block and a cooling plate located on the evaporator and the condenser surface respectively. The performance of the vapor chamber was investigated by determining the thermal resistance over a heat input range of 1 to 5W in natural convection test with the condenser opens at ambient environment and up to 40W in force convection with the condenser held at constant temperature. The experimental results show that the Maximum heat dissipated ability was the same compare with the new design measuring system and the traditional heat pipe performance measuring system with a water jacket as the cooling condenser. The thermal resistance in natural convection condition for the axial direction was around 0.1°C/W, while the spray thermal resistance was 0.12°C/W. For the defrost plate, the axial thermal resistance was 0.17°C/W and 0.18°C/W for the spray thermal resistance.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"8 1","pages":"253-256"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85366723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117235
Chao-Chyun An, Ming-Hsien Wu, Yu-wei Huang, Tai-Hong Chen, C. Chao, W. Yeh
Flip chip assembly technology is an attractive solution for high I/O density and fine-pitch microelectronics packaging. Recently, high efficient GaN-based light-emitting diodes (LEDs) have undergone a rapid development and flip chip bonding has been widely applied to fabricate high-brightness GaN micro-LED arrays [1]. The flip chip GaN LED has some advantages over the traditional top-emission LED, including improved current spreading, higher light extraction efficiency, better thermal dissipation capability and the potential of further optical component integration [2, 3]. With the advantages of flip chip assembly, micro-LED (μLED) arrays with high I/O density can be performed with improved luminous efficiency than conventional p-side-up micro-LED arrays and are suitable for many potential applications, such as micro-displays, bio-photonics and visible light communications (VLC), etc. In particular, μLED array based selif-emissive micro-display has the promising to achieve high brightness and contrast, reliability, long-life and compactness, which conventional micro-displays like LCD, OLED, etc, cannot compete with. In this study, GaN micro-LED array device with flip chip assembly package process was presented. The bonding quality of flip chip high density micro-LED array is tested by daisy chain test. The p-n junction tests of the devices are measured for electrical characteristics. The illumination condition of each micro-diode pixel was examined under a forward bias. Failure mode analysis was performed using cross sectioning and scanning electron microscopy (SEM). Finally, the fully packaged micro-LED array device is demonstrated as a prototype of dice projector system.
{"title":"Study on flip chip assembly of high density micro-LED array","authors":"Chao-Chyun An, Ming-Hsien Wu, Yu-wei Huang, Tai-Hong Chen, C. Chao, W. Yeh","doi":"10.1109/IMPACT.2011.6117235","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117235","url":null,"abstract":"Flip chip assembly technology is an attractive solution for high I/O density and fine-pitch microelectronics packaging. Recently, high efficient GaN-based light-emitting diodes (LEDs) have undergone a rapid development and flip chip bonding has been widely applied to fabricate high-brightness GaN micro-LED arrays [1]. The flip chip GaN LED has some advantages over the traditional top-emission LED, including improved current spreading, higher light extraction efficiency, better thermal dissipation capability and the potential of further optical component integration [2, 3]. With the advantages of flip chip assembly, micro-LED (μLED) arrays with high I/O density can be performed with improved luminous efficiency than conventional p-side-up micro-LED arrays and are suitable for many potential applications, such as micro-displays, bio-photonics and visible light communications (VLC), etc. In particular, μLED array based selif-emissive micro-display has the promising to achieve high brightness and contrast, reliability, long-life and compactness, which conventional micro-displays like LCD, OLED, etc, cannot compete with. In this study, GaN micro-LED array device with flip chip assembly package process was presented. The bonding quality of flip chip high density micro-LED array is tested by daisy chain test. The p-n junction tests of the devices are measured for electrical characteristics. The illumination condition of each micro-diode pixel was examined under a forward bias. Failure mode analysis was performed using cross sectioning and scanning electron microscopy (SEM). Finally, the fully packaged micro-LED array device is demonstrated as a prototype of dice projector system.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"27 1","pages":"336-338"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82301858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117261
A. Liu, David W. Wang, Hsiang-Ming Huang, Ming Sun, Muh-ren Lin, Chonghua Zhong, Sheng-Jye Hwang, Hsuan-Heng Lu, H. Bui, Shang-Shiuan Deng
Although the reliability of chip-substrate interconnect joint has been well recognized by using leaded or lead-free solder bumps and Cu pillar, the relative displacement induced by package warpage between the bump and bump pad received significantly increasing interest, especially for those devices with low K materials and fine-pitch interconnects as the pitch becomes smaller and the package body size becomes larger in flip chip technology. In order to study the physical relationship between micron-level warpage of the package and nano-level displacement of the solder bumps, 1112-ball flip-chip BGA with and without a heat spreader was measured by using Shadow Moiré technique and Micro Moiré interferometry in this study. Shadow Moiré technique was used to characterize the overall warpage of the package between room temperature and solder ball reflow temperature of 230°C and Micro Moiré interferometry was used at room temperature and 114°C. From the results by Shadow Moiré, a heat spreader could alter the warpage pattern of the package from convex (w/o) to concave (w/o) and the amount of warpage was well-controlled under 16um. Furthermore, the correlations between Shadow Moiré and Micro Moiré were also described in this study. This study developed a useful approach and made direct estimations for the displacement of solder bumps to the possibility that could be contributive to the evaluation of the reliabilities of chip-level interconnects and packaging design.
{"title":"Correlation between Shadow Moiré and Micro Moiré techniques through characterization of flip-chip BGA","authors":"A. Liu, David W. Wang, Hsiang-Ming Huang, Ming Sun, Muh-ren Lin, Chonghua Zhong, Sheng-Jye Hwang, Hsuan-Heng Lu, H. Bui, Shang-Shiuan Deng","doi":"10.1109/IMPACT.2011.6117261","DOIUrl":"https://doi.org/10.1109/IMPACT.2011.6117261","url":null,"abstract":"Although the reliability of chip-substrate interconnect joint has been well recognized by using leaded or lead-free solder bumps and Cu pillar, the relative displacement induced by package warpage between the bump and bump pad received significantly increasing interest, especially for those devices with low K materials and fine-pitch interconnects as the pitch becomes smaller and the package body size becomes larger in flip chip technology. In order to study the physical relationship between micron-level warpage of the package and nano-level displacement of the solder bumps, 1112-ball flip-chip BGA with and without a heat spreader was measured by using Shadow Moiré technique and Micro Moiré interferometry in this study. Shadow Moiré technique was used to characterize the overall warpage of the package between room temperature and solder ball reflow temperature of 230°C and Micro Moiré interferometry was used at room temperature and 114°C. From the results by Shadow Moiré, a heat spreader could alter the warpage pattern of the package from convex (w/o) to concave (w/o) and the amount of warpage was well-controlled under 16um. Furthermore, the correlations between Shadow Moiré and Micro Moiré were also described in this study. This study developed a useful approach and made direct estimations for the displacement of solder bumps to the possibility that could be contributive to the evaluation of the reliabilities of chip-level interconnects and packaging design.","PeriodicalId":6360,"journal":{"name":"2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)","volume":"10 1","pages":"269-272"},"PeriodicalIF":0.0,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82627200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117206
T. H. Wu, P. Wei
The effects of the Curie temperature on transport variables and nugget growth during resistance spot welding are investigated. The Curie temperature is the temperature, indicating that magnetic transformation below which a metal or alloy is ferromagnetic with high magnetic permeability, and above which it is paramagnetic with small magnetic permeability. The model accounts for electromagnetic force, heat generations and contact resistances at the faying surface and electrode-workpiece interfaces and bulk resistance in workpieces. Contact resistance includes constriction and film resistances, which are functions of hardness, temperature, electrode force and surface condition. The computed results show that the molten nugget on the faying surface initiates earlier with a high Curie temperature. High Curie temperature readily melts through the workpiece surface near the electrode edge. The present work can also be applied to interpret the contact problems encountered in various electronics and packaging technologies, etc.
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Pub Date : 2011-12-29DOI: 10.1109/IMPACT.2011.6117243
Tao-Chih Chang, Ren-Shin Cheng, K. Kao, Wei Li, Ching-Kuan Lee, Jing-Yao Chang, Shin-Yi Huang, Chia-Wen Fan, Yin-Po Hung, Yu-wei Huang, Yu-Min Lin, Tai-Hong Chen, F. Leu, S. Fun, W. Lo
In this research, thousands of 20 μm pitch microbumps with a diameter of 10 μm and a structure of pure Sn cap on Cu pillar were electroplated on 8 inch wafers, and those wafers were then respectively singularized to be top chip (5 mm × 5 mm) and bottom Si interposer (10 mm × 10 mm) for stacking. Two methods including conventional reflow and solid-liquid interdiffusion (SLID) bonding were chosen to interconnect the microbumps on the chip and on the interposer. In the former case, the as-plated Sn caps were fluxed with Senju Metal's WF-6400 paste, and the chip was then placed on a Si interposer using a SÜSS FC-150 bonder at room temperature. Afterwards, the Sn caps on the chip and on the Si interposer were melted and interconnected at a peak temperature of 250°C in an ERSA's reflow oven (Hotflow 7). The flux residues were cleaned after reflow, and the microgap between the chip and the Si interposer were fully sealed by a Namics' capillary underfill with an average filler size of 0.3 um. Regarding the SLID bonding, the oxides on the as-plated Sn caps were removed by a plasma etcher first, and then the chip was placed on the interposer by the SÜSS FC-150 bonder as well, subsequently, the Sn caps were heated up to 260°C to react with Cu to form Cu6Sn5 completely. In the final, the intermetallic microjoints were also protected by the same capillary underfill. After assembling, the JEDEC preconditioning test was used to screen the test vehicles for reliability assessment, and then a temperature cycling test was performed to predict the lifespan of the microjoints. The test results showed that the microjoints formed by SLID bonding provided a superior reliability performance to those assembled by reflow. According to the images of focus ion beam (FIB), the intermetallic phases of Cu6Sn5 and Cu3Sn coexisted at the interface between the Sn cap and the Cu pillar after reflow once, and some Kirkendall voids were found at the Cu3Sn / Cu pillar interface concurrently. When the microjoints undergone 3 times more reflow in the preconditioning test, the Kirkendall voids accumulated and was going to speed up the failure of microjoints as experienced just hundreds of temperature cycles. On the other hand, the microjoints produced by SLID bonding have not failed when thousands of temperature cycles passed. Based on those evidences, it is claimed here that SLID is an efficient bonding method to form reliable intermetallic microjoints for chip stacking.
在8英寸硅片上电镀了数千个直径为10 μm、间距为20 μm的微凸点和纯锡盖覆铜柱结构，并分别将其奇点化为顶部芯片(5 mm × 5 mm)和底部硅中间层(10 mm × 10 mm)进行堆叠。采用常规回流焊和固液互扩散焊两种方法对芯片和中间层上的微凸点进行互连。在前一种情况下，镀锡帽用Senju Metal的WF-6400浆料焊剂，然后在室温下使用SÜSS FC-150粘结剂将芯片放置在Si中间体上。然后，在ERSA的回流炉(Hotflow 7)中，将芯片上的锡帽和硅中间层上的锡帽熔化并在250°C的峰值温度下互连。回流后清洗焊剂残留物，芯片和硅中间层之间的微间隙被Namics的毛细管下填料完全密封，填料的平均尺寸为0.3 um。对于滑动键合，首先用等离子蚀刻机除去镀锡帽上的氧化物，然后用SÜSS FC-150键合器将芯片置于中间层上，然后将锡帽加热至260℃与Cu完全反应生成Cu6Sn5。最后，金属间微节理也同样受到毛细充填物的保护。装配完成后，采用JEDEC预调节试验对试验车辆进行可靠性评估，然后进行温度循环试验对微关节寿命进行预测。试验结果表明，与回流焊相比，滑动焊形成的微接头具有更好的可靠性。从聚焦离子束(FIB)图像可以看出，回流一次后，在Sn帽与Cu柱界面处存在Cu6Sn5和Cu3Sn的金属间相共存，并且在Cu3Sn / Cu柱界面处同时存在Kirkendall空洞。预处理试验中，当微关节经历3倍以上的回流时，Kirkendall空洞的积累将加速微关节的破坏，而温度循环仅为数百次。另一方面，通过滑动键合产生的微接头在经过数千个温度循环后仍未失效。基于这些证据，本文认为，滑移是一种有效的键合方法，可以形成可靠的金属间微接头进行芯片堆积。
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