Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857039
Fu-Yen Kuo, Chung-Wei Ku
In this paper, a re-configurable architecture for both chip-rate de-spreading and FIR filtering is proposed. The proposed architecture can be configured as a chip matched filter, multi-code RAKE receiver, or an FIR filter. Since these modules are essential for CDMA/TDMA systems, we believe the proposed architecture is quite useful for CDMA/TDMA dual-mode receiver design.
{"title":"Software radio based re-configurable correlator/FIR filter for CDMA/TDMA receiver","authors":"Fu-Yen Kuo, Chung-Wei Ku","doi":"10.1109/ISCAS.2000.857039","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857039","url":null,"abstract":"In this paper, a re-configurable architecture for both chip-rate de-spreading and FIR filtering is proposed. The proposed architecture can be configured as a chip matched filter, multi-code RAKE receiver, or an FIR filter. Since these modules are essential for CDMA/TDMA systems, we believe the proposed architecture is quite useful for CDMA/TDMA dual-mode receiver design.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82396352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857160
R. Matei
Resistive networks have attracted the interest of researchers for their potential applications especially in parallel signal processing. At present they are essential components in analog VLSI circuit implementation of many image processing systems. Resistive grids, as well as their dynamic and more complex counterpart-the cellular neural networks-can perform various spatial filtering operations. One of the most important applications of the resistive grid is the silicon retina, proposed by Mahowald and Mead [1989], whose structure has a well-established neurobiological basis. The data to be processed (an image in the 2-D case) is sampled by a rectangular grid, so that each node of the network is associated with a pixel in the image that is to be filtered. In this paper we propose a different structure for a resistive network with a pyramidal topology which may prove to find some useful applications in parallel signal processing. We will show that the proposed network performs a nonlinear spatial filtering of the input 1D image, implementing in fact a Haar filter.
{"title":"Haar filtering with pyramidal resistive networks","authors":"R. Matei","doi":"10.1109/ISCAS.2000.857160","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857160","url":null,"abstract":"Resistive networks have attracted the interest of researchers for their potential applications especially in parallel signal processing. At present they are essential components in analog VLSI circuit implementation of many image processing systems. Resistive grids, as well as their dynamic and more complex counterpart-the cellular neural networks-can perform various spatial filtering operations. One of the most important applications of the resistive grid is the silicon retina, proposed by Mahowald and Mead [1989], whose structure has a well-established neurobiological basis. The data to be processed (an image in the 2-D case) is sampled by a rectangular grid, so that each node of the network is associated with a pixel in the image that is to be filtered. In this paper we propose a different structure for a resistive network with a pyramidal topology which may prove to find some useful applications in parallel signal processing. We will show that the proposed network performs a nonlinear spatial filtering of the input 1D image, implementing in fact a Haar filter.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82506503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857387
B. Maundy, I. Finvers, P. B. Aronhime
A novel variation of the cross-coupled operational transconductance cell is presented in this paper. The conventional cross-coupled cell has a differential input linearity range that is dependent on the control voltage. The proposed design removes that restriction while allowing the same tunability using the control voltage. Its input may also be single or fully differential unlike the conventional cross-coupled cell, which requires a fully differential input. Results were confirmed using HSPICE simulations.
{"title":"Cross coupled transconductance cell with improved linearity range","authors":"B. Maundy, I. Finvers, P. B. Aronhime","doi":"10.1109/ISCAS.2000.857387","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857387","url":null,"abstract":"A novel variation of the cross-coupled operational transconductance cell is presented in this paper. The conventional cross-coupled cell has a differential input linearity range that is dependent on the control voltage. The proposed design removes that restriction while allowing the same tunability using the control voltage. Its input may also be single or fully differential unlike the conventional cross-coupled cell, which requires a fully differential input. Results were confirmed using HSPICE simulations.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78863518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.858747
Chin-Hwa Kuo, Tay-Shen Wang
Reports on the design and implementation of a networked visual monitoring system for surveillance. Instead of the usual periodic monitoring, the system has an auto-tracking feature which captures the important characteristics of intruders. We integrate two schemes, namely, image segmentation and histogram comparison, to accomplish the auto-tracking feature. The developed tracking scheme is able to segment and track moving objects from the background in real time. The tracked object information is used to guide the motion of the tracking camera to track the intruders and then to take a series of photographs. In multiple object tracking, we have developed a multiple objects tracking scheme, based on object color histogram comparison, to overcome object occlusion and disocclusion issues. To achieve efficient transmission and storage, the captured video is compressed in H.263 format. Query based on time as well as events are provided. Users can access the system from web browsers to view the monitoring site or manipulate the tracking camera on the Internet. These features are of importance and value to surveillance.
{"title":"Design of networked visual monitoring systems","authors":"Chin-Hwa Kuo, Tay-Shen Wang","doi":"10.1109/ISCAS.2000.858747","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.858747","url":null,"abstract":"Reports on the design and implementation of a networked visual monitoring system for surveillance. Instead of the usual periodic monitoring, the system has an auto-tracking feature which captures the important characteristics of intruders. We integrate two schemes, namely, image segmentation and histogram comparison, to accomplish the auto-tracking feature. The developed tracking scheme is able to segment and track moving objects from the background in real time. The tracked object information is used to guide the motion of the tracking camera to track the intruders and then to take a series of photographs. In multiple object tracking, we have developed a multiple objects tracking scheme, based on object color histogram comparison, to overcome object occlusion and disocclusion issues. To achieve efficient transmission and storage, the captured video is compressed in H.263 format. Query based on time as well as events are provided. Users can access the system from web browsers to view the monitoring site or manipulate the tracking camera on the Internet. These features are of importance and value to surveillance.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78888971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856039
M. Shashkov
A class of codimension two dynamical systems with very simple dynamics is considered. In spite of simplicity of the dynamical behavior, the structure of the bifurcation set is rather complicated. It is shown that there is no versal two-parameter family of dynamical systems which could describe completely the structure of the bifurcational set.
{"title":"On complexity of bifurcations for some classes of systems with simple dynamics","authors":"M. Shashkov","doi":"10.1109/ISCAS.2000.856039","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856039","url":null,"abstract":"A class of codimension two dynamical systems with very simple dynamics is considered. In spite of simplicity of the dynamical behavior, the structure of the bifurcation set is rather complicated. It is shown that there is no versal two-parameter family of dynamical systems which could describe completely the structure of the bifurcational set.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78948545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.855983
T. Olsson, P. Nilsson, T. Meincke, A. Hemami, M. Torkelson
Partitioning large high-speed globally synchronous ASICs into locally clocked blocks reduces clock skew problems and if handled correctly it also reduces the power consumption. However, to achieve these positive effects, the blocks need on-chip clock generators having properties such as small area and low power consumption. Therefore, a low power, high frequency, small area digitally controlled on-chip clock generator is designed and fabricated using a 0.35 /spl mu/m process. The clock generator delivers up to 1.15 GHz at 3.3 V supply voltage. At 1 V supply voltage, it delivers up to 92 MHz while consuming 0.16 mW.
{"title":"A digitally controlled low-power clock multiplier for globally asynchronous locally synchronous designs","authors":"T. Olsson, P. Nilsson, T. Meincke, A. Hemami, M. Torkelson","doi":"10.1109/ISCAS.2000.855983","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.855983","url":null,"abstract":"Partitioning large high-speed globally synchronous ASICs into locally clocked blocks reduces clock skew problems and if handled correctly it also reduces the power consumption. However, to achieve these positive effects, the blocks need on-chip clock generators having properties such as small area and low power consumption. Therefore, a low power, high frequency, small area digitally controlled on-chip clock generator is designed and fabricated using a 0.35 /spl mu/m process. The clock generator delivers up to 1.15 GHz at 3.3 V supply voltage. At 1 V supply voltage, it delivers up to 92 MHz while consuming 0.16 mW.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78954175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856262
J. Yli-Kaakinen, T. Saramäki
This paper describes an efficient algorithm for the design of multiplierless approximately linear-phase lattice wave digital (LWD) filters (parallel connection of two all-pass filters). The coefficient optimization is performed in two basic steps. First, a nonlinear optimization algorithm is used for determining a parameter space of the finite-precision coefficients including the feasible space where the filter meets the given amplitude and phase specifications. The second step involves finding the filter parameters in this space such that the resulting filter meets the given criteria with the simplest coefficient representation forms. The proposed algorithm guarantees that the optimum multiplierless finite-wordlength solution can be found. This is illustrated by means of an example.
{"title":"An algorithm for the design of multiplierless approximately linear-phase lattice-wave digital filters","authors":"J. Yli-Kaakinen, T. Saramäki","doi":"10.1109/ISCAS.2000.856262","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856262","url":null,"abstract":"This paper describes an efficient algorithm for the design of multiplierless approximately linear-phase lattice wave digital (LWD) filters (parallel connection of two all-pass filters). The coefficient optimization is performed in two basic steps. First, a nonlinear optimization algorithm is used for determining a parameter space of the finite-precision coefficients including the feasible space where the filter meets the given amplitude and phase specifications. The second step involves finding the filter parameters in this space such that the resulting filter meets the given criteria with the simplest coefficient representation forms. The proposed algorithm guarantees that the optimum multiplierless finite-wordlength solution can be found. This is illustrated by means of an example.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87711945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857092
I. Sodagar, Hung-ju Lee, P. Hatrack, Bing-Bing Chai
This paper describes the visual texture compression scheme adopted for MPEG-4 international standard. The scheme is based on the concept of multiscale zerotree wavelet entropy coding (MZTE) technique that provides different levels of scalability layer in terms of either spatial resolutions or picture quality. MZTE provides much improved compression efficiency and fine-gradual scalabilities. The MZTE scheme is adopted as the baseline technique for the visual texture coding profile in both MPEG4 video group and SNHC group.
{"title":"Multi-scale zerotree entropy coding","authors":"I. Sodagar, Hung-ju Lee, P. Hatrack, Bing-Bing Chai","doi":"10.1109/ISCAS.2000.857092","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857092","url":null,"abstract":"This paper describes the visual texture compression scheme adopted for MPEG-4 international standard. The scheme is based on the concept of multiscale zerotree wavelet entropy coding (MZTE) technique that provides different levels of scalability layer in terms of either spatial resolutions or picture quality. MZTE provides much improved compression efficiency and fine-gradual scalabilities. The MZTE scheme is adopted as the baseline technique for the visual texture coding profile in both MPEG4 video group and SNHC group.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87797667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857145
A. M. Sodagar, G. R. Lahiji
A new approach in sine amplitude approximation for sine-output direct digital frequency synthesizers "parabolic approximation" is presented. The proposed approximation provides an initial guess, which is much closer to the target sine amplitude than previous approximations and can be simply implemented using full-digital circuitry.
{"title":"Parabolic approximation: a new method for phase to amplitude conversion in sine-output direct digital frequency synthesizers","authors":"A. M. Sodagar, G. R. Lahiji","doi":"10.1109/ISCAS.2000.857145","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857145","url":null,"abstract":"A new approach in sine amplitude approximation for sine-output direct digital frequency synthesizers \"parabolic approximation\" is presented. The proposed approximation provides an initial guess, which is much closer to the target sine amplitude than previous approximations and can be simply implemented using full-digital circuitry.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87940984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.858742
R. Secareanu, S. Warner, S. Seabridge, C. Burke, T. E. Watrobski, C. Morton, W. Staub, T. Tellier, E. Friedman
Theoretical, simulation and experimental analysis and data are presented, discussing physical design techniques which influence the noise behavior of digital circuits in a mixed-signal smart-power system. Several physical design strategies are presented to improve the noise immunity of digital circuits in smart-power systems.
{"title":"Physical design to improve the noise immunity of digital circuits in a mixed-signal smart-power system","authors":"R. Secareanu, S. Warner, S. Seabridge, C. Burke, T. E. Watrobski, C. Morton, W. Staub, T. Tellier, E. Friedman","doi":"10.1109/ISCAS.2000.858742","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.858742","url":null,"abstract":"Theoretical, simulation and experimental analysis and data are presented, discussing physical design techniques which influence the noise behavior of digital circuits in a mixed-signal smart-power system. Several physical design strategies are presented to improve the noise immunity of digital circuits in smart-power systems.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86839283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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