This paper presents the implementation of developed stacked piezoelectric actuators (PZT) via a novel developed direct current digital battery charger device (DBCD). Battery charger system is developed for powering PZT and utilized for micro precision motion actuation. This power system without conventional transformer is constructed without the use of conventional coil and the use of high-frequency switching power design. Emphasis placed here is on controlling and data acquisitioning the characteristics of PZT via the developed technique of high speed, voltage-feedback-loop power amplifier. Voltage is digitally controlled to PZT in real time compensation by circuit design. Because precise displacement of PZT is useful in micro positioning under the consideration of external load, the motion of PZT is controlled by supplied voltage in parallel with an additional capacitance in this study. The developed integrated PZT system is illustrated to be very attractive and practical for future advanced piezoelectric motion control technique.
{"title":"Application of a novel battery charger system to new developed piezoelectric actuator for high speed micropositioning motion","authors":"Yi-Cheng Huang, Wen-Yung Liang, Chao Lu, Chih-Wen Hsieh","doi":"10.1109/ISCAS.2000.856375","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856375","url":null,"abstract":"This paper presents the implementation of developed stacked piezoelectric actuators (PZT) via a novel developed direct current digital battery charger device (DBCD). Battery charger system is developed for powering PZT and utilized for micro precision motion actuation. This power system without conventional transformer is constructed without the use of conventional coil and the use of high-frequency switching power design. Emphasis placed here is on controlling and data acquisitioning the characteristics of PZT via the developed technique of high speed, voltage-feedback-loop power amplifier. Voltage is digitally controlled to PZT in real time compensation by circuit design. Because precise displacement of PZT is useful in micro positioning under the consideration of external load, the motion of PZT is controlled by supplied voltage in parallel with an additional capacitance in this study. The developed integrated PZT system is illustrated to be very attractive and practical for future advanced piezoelectric motion control technique.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"30 1","pages":"501-504 vol.2"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88285930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856314
M. Domański, A. Luczak, S. Mackowiak
Recently, there is a great interest in video codecs that implement the functionality of spatial scalability. Unfortunately, those MPEG-2 and MPEG-4 coders which exhibit such a functionality produce much more bits than corresponding single layer coders. This bitrate overhead can be reduced by application of spatio-temporal scalability as proposed by the authors. The base layer bitstream corresponds to pictures with reduced both spatial and temporal resolution while the enhancement layer bitstream is used to transmit the information needed to retrieve images with full spatial and temporal resolution. Full compatibility with the MPEG standards is ensured in the base layer where temporal resolution reduction is obtained by B-frame data partitioning, i.e. by placing each second frame (B-frame) in the enhancement layer only. Improved prediction of B-frames in the enhancement layer is proposed in this paper. The idea is to combine temporal forward and backward prediction with spatial interpolation. Experimental results prove a clear improvement of the MPEG-2-compatible scalable coding efficiency for the scheme proposed.
{"title":"Scalable MPEG video coding with improved B-frame prediction","authors":"M. Domański, A. Luczak, S. Mackowiak","doi":"10.1109/ISCAS.2000.856314","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856314","url":null,"abstract":"Recently, there is a great interest in video codecs that implement the functionality of spatial scalability. Unfortunately, those MPEG-2 and MPEG-4 coders which exhibit such a functionality produce much more bits than corresponding single layer coders. This bitrate overhead can be reduced by application of spatio-temporal scalability as proposed by the authors. The base layer bitstream corresponds to pictures with reduced both spatial and temporal resolution while the enhancement layer bitstream is used to transmit the information needed to retrieve images with full spatial and temporal resolution. Full compatibility with the MPEG standards is ensured in the base layer where temporal resolution reduction is obtained by B-frame data partitioning, i.e. by placing each second frame (B-frame) in the enhancement layer only. Improved prediction of B-frames in the enhancement layer is proposed in this paper. The idea is to combine temporal forward and backward prediction with spatial interpolation. Experimental results prove a clear improvement of the MPEG-2-compatible scalable coding efficiency for the scheme proposed.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"22 1","pages":"273-276 vol.2"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86498222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856413
T. Hinamoto, T. Inoue
In this paper, a set of the optimal state-space descriptions with minimum L/sub 2/-sensitivity is synthesized for continuous-time linear systems. First, an L/sub 2/-sensitivity measure is defined for continuous-time linear systems by using a pure L/sub 2/-norm. An expression is then developed for evaluating the L/sub 2/-sensitivity in continuous-time linear systems. Next, an iterative method is applied for obtaining the optimal coordinate transformation that minimizes the L/sub 2/-sensitivity measure. Finally, a numerical example is given to illustrate the utility of the proposed technique.
{"title":"Synthesis of continuous-time linear systems with minimum L/sub 2/-sensitivity","authors":"T. Hinamoto, T. Inoue","doi":"10.1109/ISCAS.2000.856413","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856413","url":null,"abstract":"In this paper, a set of the optimal state-space descriptions with minimum L/sub 2/-sensitivity is synthesized for continuous-time linear systems. First, an L/sub 2/-sensitivity measure is defined for continuous-time linear systems by using a pure L/sub 2/-norm. An expression is then developed for evaluating the L/sub 2/-sensitivity in continuous-time linear systems. Next, an iterative method is applied for obtaining the optimal coordinate transformation that minimizes the L/sub 2/-sensitivity measure. Finally, a numerical example is given to illustrate the utility of the proposed technique.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"43 1","pages":"653-656 vol.2"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86428487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856147
Shih-Ta Hsiang, J. Woods
With fast computation and excellent compression efficiency, two embedded coding techniques, zero-tree/-block coding and context modeling of the subband/wavelet coefficients, have been widely utilized for image coding applications. In this research, we present a new embedded wavelet image coding algorithm with an attempt to combine advantages of these two successful coding schemes. The experimental results show that the proposed algorithm outperforms the respected zero-tree/-block coders, SPIHT and SPECK, in compression efficiency. It is also comparable to the state-of-art JPEG 2000 test coder in PSNR performance while retaining the attractive low-complexity feature of the zeroblock coders.
{"title":"Embedded image coding using zeroblocks of subband/wavelet coefficients and context modeling","authors":"Shih-Ta Hsiang, J. Woods","doi":"10.1109/ISCAS.2000.856147","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856147","url":null,"abstract":"With fast computation and excellent compression efficiency, two embedded coding techniques, zero-tree/-block coding and context modeling of the subband/wavelet coefficients, have been widely utilized for image coding applications. In this research, we present a new embedded wavelet image coding algorithm with an attempt to combine advantages of these two successful coding schemes. The experimental results show that the proposed algorithm outperforms the respected zero-tree/-block coders, SPIHT and SPECK, in compression efficiency. It is also comparable to the state-of-art JPEG 2000 test coder in PSNR performance while retaining the attractive low-complexity feature of the zeroblock coders.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"86 1","pages":"662-665 vol.3"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86517766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857020
Jinhui Pan, Shipeng Li, Ya-Qin Zhang
This paper introduces a novel automatic video object extraction algorithm based on combination of color and motion segmentation results. The algorithm includes five parts: preprocessing, color segmentation, motion segmentation, combination of color and motion segmentation of multiple frames, post-processing. The performance of this algorithm is very promising, resulting in pixel-wise accuracy of extracted objects. Since it is an automatic extraction algorithm, it can be very useful in some real time video processing system based on video objects.
{"title":"Automatic extraction of moving objects using multiple features and multiple frames","authors":"Jinhui Pan, Shipeng Li, Ya-Qin Zhang","doi":"10.1109/ISCAS.2000.857020","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857020","url":null,"abstract":"This paper introduces a novel automatic video object extraction algorithm based on combination of color and motion segmentation results. The algorithm includes five parts: preprocessing, color segmentation, motion segmentation, combination of color and motion segmentation of multiple frames, post-processing. The performance of this algorithm is very promising, resulting in pixel-wise accuracy of extracted objects. Since it is an automatic extraction algorithm, it can be very useful in some real time video processing system based on video objects.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"2 1","pages":"36-39 vol.1"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82685318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856163
O. Arellano-Cárdenas, H. Molina-Lozano, J. Moreno-Cadenas, F. Gómez-Castañeda, L. M. Flores-Nava
The architecture called ANFIS (Adaptive Neuro-Fuzzy Inference System) proposed by J.R. Jang (1993) is divided in five layers. Layers 1 and 2 in ANFIS were built by using a double-differential amplifier and a winner takes all circuit; to implement layers 3, 4 and 5, CMOS translinear blocks are used. The complete ANFIS architecture is implemented on a circuit board, using two CMOS circuits (N-well and 2 /spl mu/m minimum dimensions). The total system has two inputs with three membership functions each one, which generate a fuzzy space with nine subspaces and one single output. The system is used for classification of electrical signals.
{"title":"CMOS analog neurofuzzy prototype based on ANFIS","authors":"O. Arellano-Cárdenas, H. Molina-Lozano, J. Moreno-Cadenas, F. Gómez-Castañeda, L. M. Flores-Nava","doi":"10.1109/ISCAS.2000.856163","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856163","url":null,"abstract":"The architecture called ANFIS (Adaptive Neuro-Fuzzy Inference System) proposed by J.R. Jang (1993) is divided in five layers. Layers 1 and 2 in ANFIS were built by using a double-differential amplifier and a winner takes all circuit; to implement layers 3, 4 and 5, CMOS translinear blocks are used. The complete ANFIS architecture is implemented on a circuit board, using two CMOS circuits (N-well and 2 /spl mu/m minimum dimensions). The total system has two inputs with three membership functions each one, which generate a fuzzy space with nine subspaces and one single output. The system is used for classification of electrical signals.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"40 1","pages":"726-729 vol.3"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82770739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856102
I. Belykh, V. Belykh
The effects of global, partial and anti-phase synchronization of diffusively coupled dynamical systems are investigated via the linear invariant manifolds of the corresponding differential and difference equations. A selfsimilar behavior and a hierarchy of the manifolds are discovered. Stability of invariant manifolds is proved via the method of Lyapunov functions. Theoretical results are illustrated by examples of coupled Rossler systems.
{"title":"On partial synchronization of continuous and discrete-time coupled dynamical systems","authors":"I. Belykh, V. Belykh","doi":"10.1109/ISCAS.2000.856102","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856102","url":null,"abstract":"The effects of global, partial and anti-phase synchronization of diffusively coupled dynamical systems are investigated via the linear invariant manifolds of the corresponding differential and difference equations. A selfsimilar behavior and a hierarchy of the manifolds are discovered. Stability of invariant manifolds is proved via the method of Lyapunov functions. Theoretical results are illustrated by examples of coupled Rossler systems.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"14 1","pages":"483-486 vol.3"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90235805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857462
N. Haralabidis, G. Halkias
A CMOS laser diode driver (LDD) has been designed and tested, which offers the capability of independent DC and modulation current adjustments. The DC component used to pre-bias the laser diode is adjustable at a range of 0-40 mA. The modulation current can also be adjusted within a range of 0-30 mA. According to experimental results it can efficiently accommodate data rates up to 2.5 Gb/s while maintaining the full range of DC pre-bias component. Special issues regarding performance degradation have been addressed during circuit design which led to at least 25% performance enhancement compared to a conventional solution. The circuit has been fabricated in AMS 0.8 /spl mu/m CMOS process.
设计并测试了一种具有独立直流和调制电流调节能力的CMOS激光二极管驱动器。用于预偏置激光二极管的直流元件可在0-40 mA范围内调节。调制电流也可以在0-30 mA的范围内调节。实验结果表明，在保持全范围直流预偏分量的情况下，该方案可以有效地适应高达2.5 Gb/s的数据速率。在电路设计过程中解决了有关性能下降的特殊问题，与传统解决方案相比，性能提高了至少25%。该电路采用ams0.8 /spl μ m CMOS工艺制作。
{"title":"A CMOS laser driver with independently adjustable DC and modulation currents for data rates up to 2.5 Gb/s","authors":"N. Haralabidis, G. Halkias","doi":"10.1109/ISCAS.2000.857462","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857462","url":null,"abstract":"A CMOS laser diode driver (LDD) has been designed and tested, which offers the capability of independent DC and modulation current adjustments. The DC component used to pre-bias the laser diode is adjustable at a range of 0-40 mA. The modulation current can also be adjusted within a range of 0-30 mA. According to experimental results it can efficiently accommodate data rates up to 2.5 Gb/s while maintaining the full range of DC pre-bias component. Special issues regarding performance degradation have been addressed during circuit design which led to at least 25% performance enhancement compared to a conventional solution. The circuit has been fabricated in AMS 0.8 /spl mu/m CMOS process.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"7 1","pages":"425-428 vol.5"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88813728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856024
A. Baschirotto, D. Bijno, R. Castello, F. Montecchi
A 4th-order bandpass switched-capacitor (SC) filter to be used as a part of an implantable device has been designed. The power consumption reduction is a key feature of such a system. This has been achieved by using a 1 V supply (SC operation are guaranteed by using the switched-opamp technique). In addition the active devices operate in the subthreshold region. The filter uses a fully differential topology to reduce the clock feedthrough noise and increase the dynamic range. The filter has been designed in a 0.35 /spl mu/m CMOS technology. It operates at 1 kHz sampling frequency and it consumes about 1.2 /spl mu/W.
设计了一种用于可植入器件的四阶带通开关电容滤波器。功耗降低是这种系统的一个关键特征。这是通过使用1v电源实现的(使用开关运放技术保证SC操作)。此外，有源设备在阈下区域中工作。该滤波器采用全差分拓扑结构，降低了时钟馈通噪声，增加了动态范围。该滤波器采用0.35 /spl μ m CMOS工艺设计。它以1khz采样频率工作，功耗约为1.2 /spl mu/W。
{"title":"A 1 V 1.2 /spl mu/W 4th order bandpass switched-opamp SC filter for a cardiac pacer sensing stage","authors":"A. Baschirotto, D. Bijno, R. Castello, F. Montecchi","doi":"10.1109/ISCAS.2000.856024","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856024","url":null,"abstract":"A 4th-order bandpass switched-capacitor (SC) filter to be used as a part of an implantable device has been designed. The power consumption reduction is a key feature of such a system. This has been achieved by using a 1 V supply (SC operation are guaranteed by using the switched-opamp technique). In addition the active devices operate in the subthreshold region. The filter uses a fully differential topology to reduce the clock feedthrough noise and increase the dynamic range. The filter has been designed in a 0.35 /spl mu/m CMOS technology. It operates at 1 kHz sampling frequency and it consumes about 1.2 /spl mu/W.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"23 1","pages":"173-176 vol.3"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80692574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856025
U. Seng-Pan, R. Martins, J. Franca
This paper proposes a 4-fold multistage Switched-Capacitor (SC) interpolation filter with 5 MHz passband and 54 MHz output sampling rate for NTSC/PAL digital video signal processing systems. The circuit implements an impulse sampled halfband interpolation with 23- and 7-tap FIR filtering in 1stand 2nd-stage respectively for achieving a linear-phase response. A novel area-efficient technique including symmetrical-coefficient-sharing and spread-reduction is proposed in this transversal SC circuit embedding minimized mismatch-free analog delay lines with accurate, wideband gain- and offset-compensation. This filter is designed with optimized speed of the analog components in 0.35 /spl mu/m CMOS technology and expected to consume about 2 mm/sup 2/ active area and 90 mW at 3.0 V supply.
{"title":"A linear-phase halfband SC video interpolation filter with coefficient-sharing and spread-reduction","authors":"U. Seng-Pan, R. Martins, J. Franca","doi":"10.1109/ISCAS.2000.856025","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856025","url":null,"abstract":"This paper proposes a 4-fold multistage Switched-Capacitor (SC) interpolation filter with 5 MHz passband and 54 MHz output sampling rate for NTSC/PAL digital video signal processing systems. The circuit implements an impulse sampled halfband interpolation with 23- and 7-tap FIR filtering in 1stand 2nd-stage respectively for achieving a linear-phase response. A novel area-efficient technique including symmetrical-coefficient-sharing and spread-reduction is proposed in this transversal SC circuit embedding minimized mismatch-free analog delay lines with accurate, wideband gain- and offset-compensation. This filter is designed with optimized speed of the analog components in 0.35 /spl mu/m CMOS technology and expected to consume about 2 mm/sup 2/ active area and 90 mW at 3.0 V supply.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":"79 1","pages":"177-180 vol.3"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79276205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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