Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325633
S. Sung, J. Chawla, C. Carver, R. Chebiam, J. Clarke, C. Jezewski, T. Tronic, B. Turkot, H. Yoo
Assessing metal gap fill capability and electrical behavior in patterned features ahead of full integration is valuable in interconnect process development as feature sizes scale beyond the 14 nm technology node. In this work a simple device is fabricated with existing silicon patterning recipes to achieve an electrical test vehicle that can test a range of metal candidates for interconnects. The vehicle is characterized using electron microscopy and electrical measurements.
{"title":"Simple test vehicle for metal fill and resistance of sub-8nm nanowire","authors":"S. Sung, J. Chawla, C. Carver, R. Chebiam, J. Clarke, C. Jezewski, T. Tronic, B. Turkot, H. Yoo","doi":"10.1109/IITC-MAM.2015.7325633","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325633","url":null,"abstract":"Assessing metal gap fill capability and electrical behavior in patterned features ahead of full integration is valuable in interconnect process development as feature sizes scale beyond the 14 nm technology node. In this work a simple device is fabricated with existing silicon patterning recipes to achieve an electrical test vehicle that can test a range of metal candidates for interconnects. The vehicle is characterized using electron microscopy and electrical measurements.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"78 1","pages":"87-90"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83194951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325615
F. Geenen, K. van Stiphout, J. Jordan-Sweef, A. Vantomme, C. Lavoie, C. Detavernier
The influence of Ni thickness on the formation of Nickel suicides was systematically investigated between 0 and 15nm. Annealing thickness gradients distinguishes Alms that agglomerate (>5nm) and films that are morphologically stable (<;5nm). Alloying the initial Ni layer influences this critical thickness to higher (Al, Co) and lower (Ge, Pd, Pt) values. Pole figures and in situ XRD provides information to understand this observed shift in critical thickness.
{"title":"Influence of alloying elements on the phase formation of ultrathin Ni (<10nm) on Si(001) substrates","authors":"F. Geenen, K. van Stiphout, J. Jordan-Sweef, A. Vantomme, C. Lavoie, C. Detavernier","doi":"10.1109/IITC-MAM.2015.7325615","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325615","url":null,"abstract":"The influence of Ni thickness on the formation of Nickel suicides was systematically investigated between 0 and 15nm. Annealing thickness gradients distinguishes Alms that agglomerate (>5nm) and films that are morphologically stable (<;5nm). Alloying the initial Ni layer influences this critical thickness to higher (Al, Co) and lower (Ge, Pd, Pt) values. Pole figures and in situ XRD provides information to understand this observed shift in critical thickness.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"21 1","pages":"183-186"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91057757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325614
E. Gusarova, B. Viala, A. Plihon, B. Gusarov, L. Gimeno, O. Cugat
Screen-printed piezoelectric flexible microgenerators are presented. The features of this work are the deposition of multilayers of P(VDF-TrFE) thin films and organic electrode of PEDOT:PSS. Dielectric, ferroelectric and direct piezoelectric constants are reported as a function of film thickness. Direct voltage coefficient g31, measured for the first time, is shown to reach 0.118 V.m/N. In open-circuit conditions, the microgenerators submitted to four-point bending experiments can produce strain-induced voltage of 10 V with an energy density of 275 μJ/chi3.
{"title":"Fabrication and characterization of piezoelectric microgenerators for flexible energy harvesting using P(VDF-TrFE) screen-formulated inks","authors":"E. Gusarova, B. Viala, A. Plihon, B. Gusarov, L. Gimeno, O. Cugat","doi":"10.1109/IITC-MAM.2015.7325614","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325614","url":null,"abstract":"Screen-printed piezoelectric flexible microgenerators are presented. The features of this work are the deposition of multilayers of P(VDF-TrFE) thin films and organic electrode of PEDOT:PSS. Dielectric, ferroelectric and direct piezoelectric constants are reported as a function of film thickness. Direct voltage coefficient g31, measured for the first time, is shown to reach 0.118 V.m/N. In open-circuit conditions, the microgenerators submitted to four-point bending experiments can produce strain-induced voltage of 10 V with an energy density of 275 μJ/chi3.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"8 1","pages":"177-180"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89361548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325663
Jun-Fei Zheng, Philip Chen, Tomas H. Baum, R. Lieten, W. Hunks, S. Lippy, A. Frye, Weimin Li, James O'Neill, Jeff Xu, John Zhu, Jerry Bao, V. Machkaoutsan, M. Badaroglu, G. Yeap, G. Murdoch, J. Bommels, Z. Tokei
We report for the first time a highly selective CVD Co deposition on Cu to fill a 45nm diameter 3:1 aspect ratio via in a Cu dual damascene structure. We have achieved void-free Co fill of the via, demonstrating that a selective bottom-up via fill with Co is a potentially viable approach. Defect formation and control in the process and device integration are discussed. This selective process provides an opportunity to reduce via resistance and shrink the minimum metal 1 (M1) area for aggressive standard cell size scaling as needed for 7nm technology.
{"title":"Selective co growth on Cu for void-free via fill","authors":"Jun-Fei Zheng, Philip Chen, Tomas H. Baum, R. Lieten, W. Hunks, S. Lippy, A. Frye, Weimin Li, James O'Neill, Jeff Xu, John Zhu, Jerry Bao, V. Machkaoutsan, M. Badaroglu, G. Yeap, G. Murdoch, J. Bommels, Z. Tokei","doi":"10.1109/IITC-MAM.2015.7325663","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325663","url":null,"abstract":"We report for the first time a highly selective CVD Co deposition on Cu to fill a 45nm diameter 3:1 aspect ratio via in a Cu dual damascene structure. We have achieved void-free Co fill of the via, demonstrating that a selective bottom-up via fill with Co is a potentially viable approach. Defect formation and control in the process and device integration are discussed. This selective process provides an opportunity to reduce via resistance and shrink the minimum metal 1 (M1) area for aggressive standard cell size scaling as needed for 7nm technology.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"1 1","pages":"265-268"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89848100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325644
C. Byrne, A. McCoy, J. Bogan, A. Brady, G. Hughes
A copper-aluminium alloy (90:10wt%) has been investigated as a possible candidate for future interconnect applications. The tendency of the Al to segregate at the surface of the Cu following thermal anneal makes this alloy potentially suitable to function as a self-forming Cu diffusion barrier layer. X-ray photoelectron spectroscopy (XPS) and electrical characterisation measurements were used to study the segregation of Al from the alloy bulk during annealing treatments. Four point probe measurements were used to gain additional information as to the electrical resistance of the CuAl alloy when annealed at various temperatures in vacuum using pure Cu as a reference. Capacitance-voltage (CV), current-voltage (IV) and bias thermal stress (BTS) test measurements were made on metal-oxide-semiconductor (MOS) structures fabricated with the CuAl alloy and compared to identical structures with pure Cu and Al contacts.
{"title":"Characterisation of CuAl alloy for future interconnect technologies","authors":"C. Byrne, A. McCoy, J. Bogan, A. Brady, G. Hughes","doi":"10.1109/IITC-MAM.2015.7325644","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325644","url":null,"abstract":"A copper-aluminium alloy (90:10wt%) has been investigated as a possible candidate for future interconnect applications. The tendency of the Al to segregate at the surface of the Cu following thermal anneal makes this alloy potentially suitable to function as a self-forming Cu diffusion barrier layer. X-ray photoelectron spectroscopy (XPS) and electrical characterisation measurements were used to study the segregation of Al from the alloy bulk during annealing treatments. Four point probe measurements were used to gain additional information as to the electrical resistance of the CuAl alloy when annealed at various temperatures in vacuum using pure Cu as a reference. Capacitance-voltage (CV), current-voltage (IV) and bias thermal stress (BTS) test measurements were made on metal-oxide-semiconductor (MOS) structures fabricated with the CuAl alloy and compared to identical structures with pure Cu and Al contacts.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"143 1","pages":"111-114"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89958526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325591
T. Ishikura, A. Isobayashi, D. Nishide, B. Ito, Tatsuro Saito, Takashi Matsumoto, Y. Yamazaki, H. Miyazaki, Masahito Watanabe, N. Sakuma, A. Kajita, T. Sakai
We have fabricated the stacked interconnects of multi-layer graphene (MLG) and nickel (Ni) at the line width from 30 to 1000 nm in 300 mm wafer. MLG, which was grown by CVD process, was selectively deposited on Ni damascene interconnects by the catalytic reaction of Ni. MLG grown from C2H2 was composed of approximately 20 layers of graphene sheets and covered the overall surface of Ni interconnects. Two processes, one with the gas mixture of C2H2/Ar and the other with only Ar gas, were compared and short failure was observed at the comb structure specifically by the usage of C2H2 gas. Along with the failure analysis, this short failure was suggested to be caused by the unintended growth of carbon material from the Ni nanoparticle on the interconnects. An addition of ashing process improved the electrical performance with the minimum damage to MLG. At last, crystalline analysis of MLG suggests a necessity of a continuous process optimization of CVD process for positive influence on resistivity of the interconnects.
{"title":"Electrical properties of 30 nm width bi-layer interconnects of multi layer graphene and Ni","authors":"T. Ishikura, A. Isobayashi, D. Nishide, B. Ito, Tatsuro Saito, Takashi Matsumoto, Y. Yamazaki, H. Miyazaki, Masahito Watanabe, N. Sakuma, A. Kajita, T. Sakai","doi":"10.1109/IITC-MAM.2015.7325591","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325591","url":null,"abstract":"We have fabricated the stacked interconnects of multi-layer graphene (MLG) and nickel (Ni) at the line width from 30 to 1000 nm in 300 mm wafer. MLG, which was grown by CVD process, was selectively deposited on Ni damascene interconnects by the catalytic reaction of Ni. MLG grown from C2H2 was composed of approximately 20 layers of graphene sheets and covered the overall surface of Ni interconnects. Two processes, one with the gas mixture of C2H2/Ar and the other with only Ar gas, were compared and short failure was observed at the comb structure specifically by the usage of C2H2 gas. Along with the failure analysis, this short failure was suggested to be caused by the unintended growth of carbon material from the Ni nanoparticle on the interconnects. An addition of ashing process improved the electrical performance with the minimum damage to MLG. At last, crystalline analysis of MLG suggests a necessity of a continuous process optimization of CVD process for positive influence on resistivity of the interconnects.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"65 1","pages":"321-324"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79917600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325645
R. Baert, I. Ciofi, Christopher J. Wilson, V. V. Gonzalez, J. Bommels, Z. Tokei, J. Ryckaert, P. Raghavan, A. Mercha, D. Verkest
This paper compares different patterning options for back-end of line interconnects by analyzing the impact of process variations on the line resistance and capacitance. Multiple sources of variation, such as overlay, CD, etch and CMP, are taken into account in the model. The model and variability parameters are validated using test chip measurements. Several quadruple patterning options for the 7nm process node are considered. Using 3D interconnect models and Monte-Carlo analysis, statistical metrics for the different patterning options are obtained. The analysis shows that the anti-spacer patterning approach has lowest variability and best uniformity.
{"title":"Variability of quadruple-patterning interconnect processes","authors":"R. Baert, I. Ciofi, Christopher J. Wilson, V. V. Gonzalez, J. Bommels, Z. Tokei, J. Ryckaert, P. Raghavan, A. Mercha, D. Verkest","doi":"10.1109/IITC-MAM.2015.7325645","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325645","url":null,"abstract":"This paper compares different patterning options for back-end of line interconnects by analyzing the impact of process variations on the line resistance and capacitance. Multiple sources of variation, such as overlay, CD, etch and CMP, are taken into account in the model. The model and variability parameters are validated using test chip measurements. Several quadruple patterning options for the 7nm process node are considered. Using 3D interconnect models and Monte-Carlo analysis, statistical metrics for the different patterning options are obtained. The analysis shows that the anti-spacer patterning approach has lowest variability and best uniformity.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"3 1","pages":"135-138"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90873063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325648
Shaoning Yao, L. Clevenger, N. Zamdmer
Matched circuit components are widely used in logic circuits including resistors, capacitors and transistors. Any variations in those components could cause mismatch in circuit performance. In advanced technology nodes, double patterning (litho/etch/litho/etch) process has been introduced to pattern BEOL metal and via levels. Two patterning steps (litho/etch/litho/etch) with two sets of masks for litho printing and with two independent etch processes, could result in pattern dimension difference which leads to resistance and capacitance (RC) mismatch. In wire or via heavily dominated logic circuits, this RC mismatch may be sensitive to design-matched circuit components. In this paper, we studied resistance mismatch in 14nm BEOL metal level where the double patterning process is used. The mismatch of metal resistance between two locations with same-mask design and two-mask design are studied. The mismatch systematic mean offset and random variability have been discussed. The methodology of determining whether the mismatch is dominated by systematic mean offset or random variability and how to quantify the mismatch variability has been introduced and discussed in this paper.
{"title":"A study of BEOL resistance mismatch in double patterning process","authors":"Shaoning Yao, L. Clevenger, N. Zamdmer","doi":"10.1109/IITC-MAM.2015.7325648","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325648","url":null,"abstract":"Matched circuit components are widely used in logic circuits including resistors, capacitors and transistors. Any variations in those components could cause mismatch in circuit performance. In advanced technology nodes, double patterning (litho/etch/litho/etch) process has been introduced to pattern BEOL metal and via levels. Two patterning steps (litho/etch/litho/etch) with two sets of masks for litho printing and with two independent etch processes, could result in pattern dimension difference which leads to resistance and capacitance (RC) mismatch. In wire or via heavily dominated logic circuits, this RC mismatch may be sensitive to design-matched circuit components. In this paper, we studied resistance mismatch in 14nm BEOL metal level where the double patterning process is used. The mismatch of metal resistance between two locations with same-mask design and two-mask design are studied. The mismatch systematic mean offset and random variability have been discussed. The methodology of determining whether the mismatch is dominated by systematic mean offset or random variability and how to quantify the mismatch variability has been introduced and discussed in this paper.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"17 1","pages":"147-150"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89569899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325651
H. Ceric, S. Selberherr
The mechanical and electrical properties of solder bumps influence the overall reliability of 3D ICs. In this paper we present a compact model for prediction of the mean-time-to-failure of solder bumps under the influence of electromigration.
{"title":"Compact model for solder bump electromigration failure","authors":"H. Ceric, S. Selberherr","doi":"10.1109/IITC-MAM.2015.7325651","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325651","url":null,"abstract":"The mechanical and electrical properties of solder bumps influence the overall reliability of 3D ICs. In this paper we present a compact model for prediction of the mean-time-to-failure of solder bumps under the influence of electromigration.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"11 1","pages":"159-162"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84206984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-18DOI: 10.1109/IITC-MAM.2015.7325598
N. Kohler, T. Fischer, S. Zimmermann, S. Schulz
With the insertion of evaporated repair liquids into remote plasmas, a novel method to restore plasma damaged ultra low-k (ULK) materials will be introduced. The main advantage of this approach is the enhanced repair efficiency due to the formation of small plasma activated multiple repairing fragments. In this study Octamethylcyclotetrasiloxane (OMCTS) and Bis(dimethylamino)dimethylsilane (DMADMS) were chosen for blanket samples with a k-value of 2.4. Furthermore OMCTS with the addition of oxygen, methane or nitrogen was investigated on patterned ULK trench structures with 62 nm feature size.
{"title":"Experimental investigations on a plasma assisted in situ restoration process for sidewall damaged ultra low-k dielectrics","authors":"N. Kohler, T. Fischer, S. Zimmermann, S. Schulz","doi":"10.1109/IITC-MAM.2015.7325598","DOIUrl":"https://doi.org/10.1109/IITC-MAM.2015.7325598","url":null,"abstract":"With the insertion of evaporated repair liquids into remote plasmas, a novel method to restore plasma damaged ultra low-k (ULK) materials will be introduced. The main advantage of this approach is the enhanced repair efficiency due to the formation of small plasma activated multiple repairing fragments. In this study Octamethylcyclotetrasiloxane (OMCTS) and Bis(dimethylamino)dimethylsilane (DMADMS) were chosen for blanket samples with a k-value of 2.4. Furthermore OMCTS with the addition of oxygen, methane or nitrogen was investigated on patterned ULK trench structures with 62 nm feature size.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"76 1","pages":"353-356"},"PeriodicalIF":0.0,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90054295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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