Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6939971
Jung-Yi Guo, J. Liao, Yu-Min Lin, C. Cheng, J. Hsieh, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu
Cryogenic ion implantation process has received increasing attention because it provides better amorphization performance and less end-of-range defects. In this study, 20nm-thick CoSi2 film was formed on cryogenic carbon ion-implanted poly-Si substrate and the agglomeration behavior of CoSi2 film after high temperature RTA annealing was investigated by four-point-probe resistivity measurement. Results suggest that the thermal stability of CoSi2 film is greatly improved when cryogenic carbon pre-amorphization implant (PAI) with energy of 15keV and dose more than or equal to 2E15 ions/cm2 was performed on poly-Si substrate before CoSi2 formation. The suppression of agglomeration of CoSi2 film during 950°C RTA annealing is likely due to the homogeneous distribution of fine-grained CoSi2 film formed on fully amorphized poly-Si substrate. In addition, it was found that the microstructure of underlying poly-Si of stacked poly-Si substrate strongly affects the agglomeration behavior of CoSi2 film. The precise control of amorphization depth by adjusting carbon PAI energy can lead to improvement in CoSi2 thermal stability.
{"title":"Study on the improved thermal stability of cobalt silicide film by using cryogenic carbon PAI","authors":"Jung-Yi Guo, J. Liao, Yu-Min Lin, C. Cheng, J. Hsieh, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu","doi":"10.1109/IIT.2014.6939971","DOIUrl":"https://doi.org/10.1109/IIT.2014.6939971","url":null,"abstract":"Cryogenic ion implantation process has received increasing attention because it provides better amorphization performance and less end-of-range defects. In this study, 20nm-thick CoSi2 film was formed on cryogenic carbon ion-implanted poly-Si substrate and the agglomeration behavior of CoSi2 film after high temperature RTA annealing was investigated by four-point-probe resistivity measurement. Results suggest that the thermal stability of CoSi2 film is greatly improved when cryogenic carbon pre-amorphization implant (PAI) with energy of 15keV and dose more than or equal to 2E15 ions/cm2 was performed on poly-Si substrate before CoSi2 formation. The suppression of agglomeration of CoSi2 film during 950°C RTA annealing is likely due to the homogeneous distribution of fine-grained CoSi2 film formed on fully amorphized poly-Si substrate. In addition, it was found that the microstructure of underlying poly-Si of stacked poly-Si substrate strongly affects the agglomeration behavior of CoSi2 film. The precise control of amorphization depth by adjusting carbon PAI energy can lead to improvement in CoSi2 thermal stability.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"15 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73680190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6940034
Y. Imai, D. Kimura, K. Yano, S. Kumakura, T. Nishiokada, F. Sato, Y. Kato, T. Iida, M. Muramatsu, A. Kitagawa
We are constructing a tandem type electron cyclotron resonance ion source (ECRIS) and a beam line for extracting, analyzing ion beams, and their applications. The ion beam is extracted from the second stage by an accel-decel extraction system with single-holes and the ion beam current on each electrode is measured. The total ion beam current is measured by a faraday cup installed at downstream from the extraction electrodes. The ion beam current of each charge state is measured by the faraday cup beyond the sector magnet. The most of the total ion beam is consisted of mainly Ar+ ~ 4+ and we can measure up to Ar9+. We measure the total ion beam current and the currents of each charge state as a function of the mid-electrode potential. It is found that the ion current of each charge state depends on the same manner to the mid-electrode potential as similar to the total ion beam currents. The results obtained experimentally against the mid-electrode potential show qualitatively good agreement with a simple theoretical consideration including sheath potential effects for formation of ion beams. The beam loss is estimated by comparing the total ion beam currents with the sum of the currents after mass/charge analysis. The effect of mid-electrode potential is very useful for decreasing the beam loss and then optimizing beam transport for enhancing ion beam current extracted from tandem type ECRIS with many ion sources.
{"title":"Effect of mid-electrode potential on multi-charged ion beam extracted from electron cyclotron resonance ion source","authors":"Y. Imai, D. Kimura, K. Yano, S. Kumakura, T. Nishiokada, F. Sato, Y. Kato, T. Iida, M. Muramatsu, A. Kitagawa","doi":"10.1109/IIT.2014.6940034","DOIUrl":"https://doi.org/10.1109/IIT.2014.6940034","url":null,"abstract":"We are constructing a tandem type electron cyclotron resonance ion source (ECRIS) and a beam line for extracting, analyzing ion beams, and their applications. The ion beam is extracted from the second stage by an accel-decel extraction system with single-holes and the ion beam current on each electrode is measured. The total ion beam current is measured by a faraday cup installed at downstream from the extraction electrodes. The ion beam current of each charge state is measured by the faraday cup beyond the sector magnet. The most of the total ion beam is consisted of mainly Ar+ ~ 4+ and we can measure up to Ar9+. We measure the total ion beam current and the currents of each charge state as a function of the mid-electrode potential. It is found that the ion current of each charge state depends on the same manner to the mid-electrode potential as similar to the total ion beam currents. The results obtained experimentally against the mid-electrode potential show qualitatively good agreement with a simple theoretical consideration including sheath potential effects for formation of ion beams. The beam loss is estimated by comparing the total ion beam currents with the sum of the currents after mass/charge analysis. The effect of mid-electrode potential is very useful for decreasing the beam loss and then optimizing beam transport for enhancing ion beam current extracted from tandem type ECRIS with many ion sources.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"16 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85142876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6939995
B. Long, Giuseppe Alessio Verni, John O’Connell, J. Holmes, M. Shayesteh, D. O'Connell, R. Duffy
This work describes a non-destructive method to introduce impurity atoms into silicon (Si) and germanium (Ge) using Molecular Layer Doping (MLD). Molecules containing dopant atoms (arsenic) were designed, synthesized and chemically bound in self-limiting monolayers to the semiconductor surface. Subsequent annealing enabled diffusion of the dopant atom into the substrate. Material characterization included assessment of surface analysis (AFM) and impurity and carrier concentrations (ECV). Record carrier concentration levels of arsenic (As) in Si (~5×1020 atoms/cm3) by diffusion doping have been achieved, and to the best of our knowledge this work is the first demonstration of doping Ge by MLD. Furthermore due to the ever increasing surface to bulk ratio of future devices (FinFets, MugFETs, nanowire-FETS) surface packing spacing requirements of MLD dopant molecules is becoming more relaxed. It is estimated that a molecular spacing of 2 nm and 3 nm is required to achieve doping concentration of 1020 atoms/cm3 in a 5 nm wide fin and 5 nm diameter nanowire respectively. From a molecular perspective this is readily achievable.
{"title":"Molecular Layer Doping: Non-destructive doping of silicon and germanium","authors":"B. Long, Giuseppe Alessio Verni, John O’Connell, J. Holmes, M. Shayesteh, D. O'Connell, R. Duffy","doi":"10.1109/IIT.2014.6939995","DOIUrl":"https://doi.org/10.1109/IIT.2014.6939995","url":null,"abstract":"This work describes a non-destructive method to introduce impurity atoms into silicon (Si) and germanium (Ge) using Molecular Layer Doping (MLD). Molecules containing dopant atoms (arsenic) were designed, synthesized and chemically bound in self-limiting monolayers to the semiconductor surface. Subsequent annealing enabled diffusion of the dopant atom into the substrate. Material characterization included assessment of surface analysis (AFM) and impurity and carrier concentrations (ECV). Record carrier concentration levels of arsenic (As) in Si (~5×1020 atoms/cm3) by diffusion doping have been achieved, and to the best of our knowledge this work is the first demonstration of doping Ge by MLD. Furthermore due to the ever increasing surface to bulk ratio of future devices (FinFets, MugFETs, nanowire-FETS) surface packing spacing requirements of MLD dopant molecules is becoming more relaxed. It is estimated that a molecular spacing of 2 nm and 3 nm is required to achieve doping concentration of 1020 atoms/cm3 in a 5 nm wide fin and 5 nm diameter nanowire respectively. From a molecular perspective this is readily achievable.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"124 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80433809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6940021
Kazuhiro Watanabe, H. Sasaki, M. Kabasawa, M. Tsukihara, K. Ueno
In order to address the process requirements of leading-edge image sensors, a new single-wafer ultra-high energy ion implanter, the S-UHE, has been developed. This product incorporates two exceptional subassemblies. One is the eighteen-stage RF linear accelerator from the UHE, a multi-wafer ultra-high energy implanter, offering maximum beam energy of 2MeV per charge. The other is the field proven end station used by the MC3-II/GP, a single-wafer medium current implanter, which can provide throughput of over 450 wafers/hour. The S-UHE has a unique beam line concept where beam energy analyzing magnets bend the accelerated beam 180°. This system minimizes tool footprint, providing additional space for maintenance. Other key elements of the beam line include an electrostatic scanner, parallelizing lens and energy filter. The electrostatic scanner provides higher scan speed than mechanical systems - significantly improving dose uniformity compared to a batch high energy implanter. Additionally, the S-UHE ensures accurate implant angles and ultra-low level of metal contamination, both of which are very important parameters for advanced image sensors.
{"title":"Introduction of the S-UHE, a single-wafer ultra-high energy ion implanter","authors":"Kazuhiro Watanabe, H. Sasaki, M. Kabasawa, M. Tsukihara, K. Ueno","doi":"10.1109/IIT.2014.6940021","DOIUrl":"https://doi.org/10.1109/IIT.2014.6940021","url":null,"abstract":"In order to address the process requirements of leading-edge image sensors, a new single-wafer ultra-high energy ion implanter, the S-UHE, has been developed. This product incorporates two exceptional subassemblies. One is the eighteen-stage RF linear accelerator from the UHE, a multi-wafer ultra-high energy implanter, offering maximum beam energy of 2MeV per charge. The other is the field proven end station used by the MC3-II/GP, a single-wafer medium current implanter, which can provide throughput of over 450 wafers/hour. The S-UHE has a unique beam line concept where beam energy analyzing magnets bend the accelerated beam 180°. This system minimizes tool footprint, providing additional space for maintenance. Other key elements of the beam line include an electrostatic scanner, parallelizing lens and energy filter. The electrostatic scanner provides higher scan speed than mechanical systems - significantly improving dose uniformity compared to a batch high energy implanter. Additionally, the S-UHE ensures accurate implant angles and ultra-low level of metal contamination, both of which are very important parameters for advanced image sensors.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"10 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89745235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6940046
T. Kuroi
Power devices contribute to the building of a smart community in which people and the planet can coexist in prosperity. Analog and sensing devices as input and output interface to microcomputer provide total systems appropriate to expand smart solutions. Relatively matured process technology was used to fabricate these devices. However unique process techniques have recently been utilized to improve the performance of these devices. Especially, an increasing amount of attention has been devoted to ion implantation and annealing technology, since junction formation is the most important technology that can determine the device performance. In this paper, I will report on the technology trends, the current issues and some solutions to overcome these for power and analog devices.
{"title":"Power and analog devices trends, challenges: Implant and thermal processing applications","authors":"T. Kuroi","doi":"10.1109/IIT.2014.6940046","DOIUrl":"https://doi.org/10.1109/IIT.2014.6940046","url":null,"abstract":"Power devices contribute to the building of a smart community in which people and the planet can coexist in prosperity. Analog and sensing devices as input and output interface to microcomputer provide total systems appropriate to expand smart solutions. Relatively matured process technology was used to fabricate these devices. However unique process techniques have recently been utilized to improve the performance of these devices. Especially, an increasing amount of attention has been devoted to ion implantation and annealing technology, since junction formation is the most important technology that can determine the device performance. In this paper, I will report on the technology trends, the current issues and some solutions to overcome these for power and analog devices.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"30 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89983766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6940054
F. Mazen, F. Gonzatti, F. Madeira, S. Reboh, C. Deguet, F. Lallement, D. Landru, F. Rieutord, A. Royal
We have studied the impact of the incorporation of a buried and ultrathin layer (i.e a few nm), engineered to trap the implanted hydrogen in the donor substrate, on the silicon layer transfer by Smart Cut™. Two kinds of buried layers were studied: boron doped silicon and silicon-germanium alloy. We show that thin layers of boron doped silicon are particularly efficient to trap implanted hydrogen from the surrounding matrix. Using this structure, the transferred silicon layer presents typically a roughness of a few angstroms RMS, which represents an order of magnitude lower than the process without trapping layer. Moreover, this approach allows to transfer ultrathin silicon layer, i.e less than 100 nm thick, and is then promising for advanced generation of Silicon-On-Insulator wafers.
{"title":"Trapping of implanted hydrogen for ultrathin layer transfer","authors":"F. Mazen, F. Gonzatti, F. Madeira, S. Reboh, C. Deguet, F. Lallement, D. Landru, F. Rieutord, A. Royal","doi":"10.1109/IIT.2014.6940054","DOIUrl":"https://doi.org/10.1109/IIT.2014.6940054","url":null,"abstract":"We have studied the impact of the incorporation of a buried and ultrathin layer (i.e a few nm), engineered to trap the implanted hydrogen in the donor substrate, on the silicon layer transfer by Smart Cut™. Two kinds of buried layers were studied: boron doped silicon and silicon-germanium alloy. We show that thin layers of boron doped silicon are particularly efficient to trap implanted hydrogen from the surrounding matrix. Using this structure, the transferred silicon layer presents typically a roughness of a few angstroms RMS, which represents an order of magnitude lower than the process without trapping layer. Moreover, this approach allows to transfer ultrathin silicon layer, i.e less than 100 nm thick, and is then promising for advanced generation of Silicon-On-Insulator wafers.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"2 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87341340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6939768
L. Pipes, L. McGill, A. Jahagirdar
The emergence of three-dimensional structures (Tri-gate, FinFET, etc.) in modern CMOS manufacturing have required new technologies to mitigate ion implant damage effects. Traditional beamline ion implant provides a well understood and well controlled approach to fin doping given that the pitches between source/drain fins and/or the polysilicon gates allow it without shadowing of active device structures. However, traditional beamline ion implant also causes silicon damage that can prove particularly problematic at the dimensions associated with modern 3-dimensional transistors. In this work we perform traditional beamline ion implants into silicon wafer substrates that are heated to elevated temperatures in an effort to mitigate ion implant damage effects. The net impact of damage mitigation using this technology is shown on flat wafers, topographical wafers, and finally on 22 nm NMOS trigate devices.
{"title":"NMOS source-drain extension ion implantation into heated substrates","authors":"L. Pipes, L. McGill, A. Jahagirdar","doi":"10.1109/IIT.2014.6939768","DOIUrl":"https://doi.org/10.1109/IIT.2014.6939768","url":null,"abstract":"The emergence of three-dimensional structures (Tri-gate, FinFET, etc.) in modern CMOS manufacturing have required new technologies to mitigate ion implant damage effects. Traditional beamline ion implant provides a well understood and well controlled approach to fin doping given that the pitches between source/drain fins and/or the polysilicon gates allow it without shadowing of active device structures. However, traditional beamline ion implant also causes silicon damage that can prove particularly problematic at the dimensions associated with modern 3-dimensional transistors. In this work we perform traditional beamline ion implants into silicon wafer substrates that are heated to elevated temperatures in an effort to mitigate ion implant damage effects. The net impact of damage mitigation using this technology is shown on flat wafers, topographical wafers, and finally on 22 nm NMOS trigate devices.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"76 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72686523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6940015
S. Abo, Hidenori Osae, F. Wakaya, M. Takai, H. Oda
Depth profiles of a spreading resistance of ultra-shallow arsenic implanted into silicon with an energy of 2.0 keV and a dose of 1.0 × 1015 ions/cm2 activated with a combination of conventional spike lamp and laser annealing processes were measured using scanning spreading resistance microscopy (SSRM) with a depth resolution of less than 5 nm. The lowest resistances in the arsenic activated region by laser annealing with laser power densities of 0.33 kW/mm2 and 0.35 kW/mm2 followed by spike lamp annealing (a laser first process) were 44 and 88 % lower than those with spike lamp annealing followed by laser annealing (a spike first process) with the same laser power densities, respectively. The lowest resistance in the arsenic activated region by the laser first process with a laser power density of the 0.35 kW/mm2 was 42 % lower than that with a laser power density of 0.33 kW/mm2. The depth of p+.n junction by the laser first process with a laser power density of 0.35 kW/mm2 was 2 nm shallower than that by the spike first process with the same laser power density. The laser first process is more suitable for the fabrication of the sallow and low-resistance extension regions than the spike first process.
{"title":"Spreading resistance profiling of ultra shallow junction fabricated with low energy as implantation and combination of spike lamp and laser annealing processes using scanning spreading resistance microscopy","authors":"S. Abo, Hidenori Osae, F. Wakaya, M. Takai, H. Oda","doi":"10.1109/IIT.2014.6940015","DOIUrl":"https://doi.org/10.1109/IIT.2014.6940015","url":null,"abstract":"Depth profiles of a spreading resistance of ultra-shallow arsenic implanted into silicon with an energy of 2.0 keV and a dose of 1.0 × 1015 ions/cm2 activated with a combination of conventional spike lamp and laser annealing processes were measured using scanning spreading resistance microscopy (SSRM) with a depth resolution of less than 5 nm. The lowest resistances in the arsenic activated region by laser annealing with laser power densities of 0.33 kW/mm2 and 0.35 kW/mm2 followed by spike lamp annealing (a laser first process) were 44 and 88 % lower than those with spike lamp annealing followed by laser annealing (a spike first process) with the same laser power densities, respectively. The lowest resistance in the arsenic activated region by the laser first process with a laser power density of the 0.35 kW/mm2 was 42 % lower than that with a laser power density of 0.33 kW/mm2. The depth of p+.n junction by the laser first process with a laser power density of 0.35 kW/mm2 was 2 nm shallower than that by the spike first process with the same laser power density. The laser first process is more suitable for the fabrication of the sallow and low-resistance extension regions than the spike first process.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"201 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79948349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6939769
J. Borland, P. Konkola
We report room temperature p-type acceptor formation in Ge from B and C implant damage up to a level of 120Ω/□ or 1E19/cm3. For n-type dopant implants in Ge we found that an oxide surface capping layer was required above 625°C to prevent dopant surface loss. P followed by As then Sb gave the best dopant activation and at the same low temperature anneal B, P, As and Sb Rs values were always lower in Ge by 1.3x to 3x than in Si possibly directly related to the higher mobility ratio in Ge to Si and differences in Ge dopant surface loss and segregation into oxide.
{"title":"Implant dopant activation comparison between silicon and germanium","authors":"J. Borland, P. Konkola","doi":"10.1109/IIT.2014.6939769","DOIUrl":"https://doi.org/10.1109/IIT.2014.6939769","url":null,"abstract":"We report room temperature p-type acceptor formation in Ge from B and C implant damage up to a level of 120Ω/□ or 1E19/cm3. For n-type dopant implants in Ge we found that an oxide surface capping layer was required above 625°C to prevent dopant surface loss. P followed by As then Sb gave the best dopant activation and at the same low temperature anneal B, P, As and Sb Rs values were always lower in Ge by 1.3x to 3x than in Si possibly directly related to the higher mobility ratio in Ge to Si and differences in Ge dopant surface loss and segregation into oxide.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"10 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85628154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-30DOI: 10.1109/IIT.2014.6939969
Yonggen He, David-Wei Zhang, Hailong Liu, Yong Chen, Yu Guobing, Youfeng He, Lan Jin, Jiaqi Wu, Jie Zhao, W. Song, Y. Shaofeng, Jingang Wu
HfO2 based high-permittivity gate dielectric has been introduced to CMOS logic device manufacturing since from 45nm node. However, these dielectrics are still under investigation and continuous optimization because of their relatively high oxygen vacancy concentration. Post Dielectric Annealing (PDA) after HK film may be a promising approach to reduce HK film trapped defect density and improve device performance as some literature reported recently. In the present work, different annealing conditions were applied on interface layer (IL)/HfO2 stack films, including soak annealing, spike annealing, and flash lamp based Milli-Second Annealing (MSA). Both blanket wafer and MOSCAP wafer characterization results show post HK MSA is an effective method to repair HK intrinsic defect, like oxygen vacancy, while it also beneficial for improving the Si/IL, IL/HK interface quality.
{"title":"Investigation of different post HK annealing impact on HK film property and device performance","authors":"Yonggen He, David-Wei Zhang, Hailong Liu, Yong Chen, Yu Guobing, Youfeng He, Lan Jin, Jiaqi Wu, Jie Zhao, W. Song, Y. Shaofeng, Jingang Wu","doi":"10.1109/IIT.2014.6939969","DOIUrl":"https://doi.org/10.1109/IIT.2014.6939969","url":null,"abstract":"HfO2 based high-permittivity gate dielectric has been introduced to CMOS logic device manufacturing since from 45nm node. However, these dielectrics are still under investigation and continuous optimization because of their relatively high oxygen vacancy concentration. Post Dielectric Annealing (PDA) after HK film may be a promising approach to reduce HK film trapped defect density and improve device performance as some literature reported recently. In the present work, different annealing conditions were applied on interface layer (IL)/HfO2 stack films, including soak annealing, spike annealing, and flash lamp based Milli-Second Annealing (MSA). Both blanket wafer and MOSCAP wafer characterization results show post HK MSA is an effective method to repair HK intrinsic defect, like oxygen vacancy, while it also beneficial for improving the Si/IL, IL/HK interface quality.","PeriodicalId":6548,"journal":{"name":"2014 20th International Conference on Ion Implantation Technology (IIT)","volume":"8 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85966048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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