Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7354970
A. Sabry, W. Z. W. Hasan, M. A. Kadir, M. Radzi, S. Shafie
In developing Wireless Sensor Node (WSN) especially in automation applications, the power consumption and the size minimization are the main concern. Therefore, some strategies have been proposed for investigating the power consumption in this field. These strategies provide knowledge to expect the WSN cost, complexity, and lifetime, as well as to provide recommendations to automation designers and enhance to optimize the energy consumed based on the applications. This paper proposes a wireless sensor measurement as a precise strategy for power consumption evaluation, the proposed method is less not only in cost, but also in terms of complexity, the paper presents an approach for evaluating the power consumption of a wireless sensor node in automation applications by attempting on experimental measurements along with a set of tools to automate the proposed approach. Starting from a MATLAB programming language code, we develop algorithms and node configuration in such a way that the analogue sensor signal, the processing and analysis area accomplished without using microcontroller, but only the XBee RF modules with 1+0.3 mWatt power consumption. In order to evaluate the proposed approach, we compare the results obtained by this proposed method against ones obtained through oscilloscope reading.
{"title":"Power consumption and size minimization of a wireless sensor node in automation system application","authors":"A. Sabry, W. Z. W. Hasan, M. A. Kadir, M. Radzi, S. Shafie","doi":"10.1109/RSM.2015.7354970","DOIUrl":"https://doi.org/10.1109/RSM.2015.7354970","url":null,"abstract":"In developing Wireless Sensor Node (WSN) especially in automation applications, the power consumption and the size minimization are the main concern. Therefore, some strategies have been proposed for investigating the power consumption in this field. These strategies provide knowledge to expect the WSN cost, complexity, and lifetime, as well as to provide recommendations to automation designers and enhance to optimize the energy consumed based on the applications. This paper proposes a wireless sensor measurement as a precise strategy for power consumption evaluation, the proposed method is less not only in cost, but also in terms of complexity, the paper presents an approach for evaluating the power consumption of a wireless sensor node in automation applications by attempting on experimental measurements along with a set of tools to automate the proposed approach. Starting from a MATLAB programming language code, we develop algorithms and node configuration in such a way that the analogue sensor signal, the processing and analysis area accomplished without using microcontroller, but only the XBee RF modules with 1+0.3 mWatt power consumption. In order to evaluate the proposed approach, we compare the results obtained by this proposed method against ones obtained through oscilloscope reading.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"43 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81862270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7355012
A. Kamarudin, N. A. Zaidi, S. Suriati, M. Shahimin
Dye a sensitized solar cell (DSSC) is expected to be a potential leader in the technology of solar cells in the future. The low-cost manufacturing of this technology offers an alternative to the silicon-based solar cells. Realizing the low efficiency and rapid degradation of DSSCs, researchers are lead to analyze the factors to maintain its stability. In this paper, DSSC was fabricated by using natural dye, Oxalis Triangularis, with varying different solvents; ethanol, water and pure dye. The degradation trends and stability of the extracting dye in each solvent was observed by time-variation analysis. The degradation of extracted dye was observed at 0 min, 30 mins, 1 hour, 2 hours, 24 hours, 25 hours and 48 hours. As for the extracting solvent, ethanol yields a better performance by maintaining its stability for 48 hour, while for water solvent, the DSSC starts to degrade after 25 hour being fabricated. The highest efficiency of Oxalis Triangularis is achieved in ethanol solvent about 0.05907% with Voc 0.0810mV, Isc 0.0204mA/cm2, FF 614.5 at 2 hours, followed by in water solvent about 0.09540% with Voc 0.1359mV, Isc 0.0268mA/cm2, FF 3.6434 at 30 minutes and pure dye 0.00032% with Voc 0.1305mV, Isc 0.1721mA/cm2, FF 397.3 after 25 hours. Then, Oxalis Triangularis was extracted in different pH which pH 2.3, pH 3.2, pH 5, pH 7, pH 7.5, pH 7.8 for 0 min and after 1 hour. Oxalis Triangularis achieved high-energy conversion efficiency about 2.619×10-6%, at the high acidity and 4.53×10-6%, for alkaline pH value, which is at pH 2.5 and pH 7.8, respectively. Nevertheless, after one hour, the efficiency of each pH values was changed about 0.006×10-6% for pH 2.5 and 2.219×10-6% for pH 7.8 due to the oxidation and chemical reaction of the dye solution. The results discussed in this paper describe the acceptable optimum time for fabrication before degradation started to occur after the DSSCs being stored at room temperature.
{"title":"Impacts of dye extracting solvents and pH on the stability of the oxalis triangularis as dye sensitizer by time-varying on DSSCs","authors":"A. Kamarudin, N. A. Zaidi, S. Suriati, M. Shahimin","doi":"10.1109/RSM.2015.7355012","DOIUrl":"https://doi.org/10.1109/RSM.2015.7355012","url":null,"abstract":"Dye a sensitized solar cell (DSSC) is expected to be a potential leader in the technology of solar cells in the future. The low-cost manufacturing of this technology offers an alternative to the silicon-based solar cells. Realizing the low efficiency and rapid degradation of DSSCs, researchers are lead to analyze the factors to maintain its stability. In this paper, DSSC was fabricated by using natural dye, Oxalis Triangularis, with varying different solvents; ethanol, water and pure dye. The degradation trends and stability of the extracting dye in each solvent was observed by time-variation analysis. The degradation of extracted dye was observed at 0 min, 30 mins, 1 hour, 2 hours, 24 hours, 25 hours and 48 hours. As for the extracting solvent, ethanol yields a better performance by maintaining its stability for 48 hour, while for water solvent, the DSSC starts to degrade after 25 hour being fabricated. The highest efficiency of Oxalis Triangularis is achieved in ethanol solvent about 0.05907% with Voc 0.0810mV, Isc 0.0204mA/cm2, FF 614.5 at 2 hours, followed by in water solvent about 0.09540% with Voc 0.1359mV, Isc 0.0268mA/cm2, FF 3.6434 at 30 minutes and pure dye 0.00032% with Voc 0.1305mV, Isc 0.1721mA/cm2, FF 397.3 after 25 hours. Then, Oxalis Triangularis was extracted in different pH which pH 2.3, pH 3.2, pH 5, pH 7, pH 7.5, pH 7.8 for 0 min and after 1 hour. Oxalis Triangularis achieved high-energy conversion efficiency about 2.619×10-6%, at the high acidity and 4.53×10-6%, for alkaline pH value, which is at pH 2.5 and pH 7.8, respectively. Nevertheless, after one hour, the efficiency of each pH values was changed about 0.006×10-6% for pH 2.5 and 2.219×10-6% for pH 7.8 due to the oxidation and chemical reaction of the dye solution. The results discussed in this paper describe the acceptable optimum time for fabrication before degradation started to occur after the DSSCs being stored at room temperature.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"8 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87651346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7354988
Z. A. N. Faizah, I. Ahmad, P. J. Ker, P. S. Akmaa Roslan, A. Maheran
Metal-Oxide-Semiconductor Field Effect Transistors MOSFETs (MOSFETs) transistor have been scaled tremendously through Moore's Law since 1974 in order to compact transistors in a single chip. Thus, a proper scaling technique is compulsory to minimize the short channel effect (SCE) problems. In this paper, the virtual fabricated design and device's characterization of 14 nm HfO2/WSi2 n-type MOSFET device is presented. The device is scaled based on previous research on 32 nm transistors. The virtual fabrication and simulation of n-type MOSFETs are implemented using Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools named ATHENA and ATLAS. From the simulation, result shows that the optimal value of threshold voltage (VTH), drive current (ION) and leakage current (IOFF) are 0.232291 V, 78.922×10-6 A/um and 77.11×10-9 A/um respectively. These simulation results are believed to be able to create a touchstone towards the optimization and fabrication of 14 nm device's gate length utilizing High-K/Metal Gate n-type MOSFET in impending work.
{"title":"Modeling of 14 nm gate length n-Type MOSFET","authors":"Z. A. N. Faizah, I. Ahmad, P. J. Ker, P. S. Akmaa Roslan, A. Maheran","doi":"10.1109/RSM.2015.7354988","DOIUrl":"https://doi.org/10.1109/RSM.2015.7354988","url":null,"abstract":"Metal-Oxide-Semiconductor Field Effect Transistors MOSFETs (MOSFETs) transistor have been scaled tremendously through Moore's Law since 1974 in order to compact transistors in a single chip. Thus, a proper scaling technique is compulsory to minimize the short channel effect (SCE) problems. In this paper, the virtual fabricated design and device's characterization of 14 nm HfO2/WSi2 n-type MOSFET device is presented. The device is scaled based on previous research on 32 nm transistors. The virtual fabrication and simulation of n-type MOSFETs are implemented using Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools named ATHENA and ATLAS. From the simulation, result shows that the optimal value of threshold voltage (VTH), drive current (ION) and leakage current (IOFF) are 0.232291 V, 78.922×10-6 A/um and 77.11×10-9 A/um respectively. These simulation results are believed to be able to create a touchstone towards the optimization and fabrication of 14 nm device's gate length utilizing High-K/Metal Gate n-type MOSFET in impending work.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"47 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90254881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7354971
I. Saad, C. B. Seng, H. M. Zuhir, B. Hazwani, N. Bolong
CMOS device scaling faces several fundamental limits as it scaled beyond the sub-30nm regime. Non-scalability of the subthreshold slope (S) and adverse short channel effects degrading the current drivability and electron mobility of a MOSFET. An innovative device structure with appropriate device physics understanding is vitally needed for scaling the silicon MOSFET into nanometer regime. Underlying this problem is the subthreshold slope concept, which is a measure of switching abruptness in transistor. S is fundamentally limited at 60mV/decade by the drift-diffusion based transport in current CMOS technology. Impact ionization MOSFET (IMOS) that works on the principle of avalanche breakdown mechanism has become promising candidate to overcome this S value constraint. In this paper, we report for the first time an analytical modelling of vertical strained Impact Ionization MOSFET (VESIMOS). We derive the equations and their range of validity and compare the characteristic with TCAD simulations to give truthful interpretation and profound effects in evaluating the device operation for circuit application.
{"title":"Physics-based modelling of vertical strained impact ionization MOSFET (VESIMOS)","authors":"I. Saad, C. B. Seng, H. M. Zuhir, B. Hazwani, N. Bolong","doi":"10.1109/RSM.2015.7354971","DOIUrl":"https://doi.org/10.1109/RSM.2015.7354971","url":null,"abstract":"CMOS device scaling faces several fundamental limits as it scaled beyond the sub-30nm regime. Non-scalability of the subthreshold slope (S) and adverse short channel effects degrading the current drivability and electron mobility of a MOSFET. An innovative device structure with appropriate device physics understanding is vitally needed for scaling the silicon MOSFET into nanometer regime. Underlying this problem is the subthreshold slope concept, which is a measure of switching abruptness in transistor. S is fundamentally limited at 60mV/decade by the drift-diffusion based transport in current CMOS technology. Impact ionization MOSFET (IMOS) that works on the principle of avalanche breakdown mechanism has become promising candidate to overcome this S value constraint. In this paper, we report for the first time an analytical modelling of vertical strained Impact Ionization MOSFET (VESIMOS). We derive the equations and their range of validity and compare the characteristic with TCAD simulations to give truthful interpretation and profound effects in evaluating the device operation for circuit application.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"43 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73799536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7354996
B. Mathew, A. Alazzam, S. Khashan, G. Destgeer, H. Sung
This article deals with the development of a two-dimensional dynamic model for predicting the trajectory of microparticles in an acoustic field, associated with standing surface acoustic wave, on a continuous flow microfluidic device. The model consists of two governing equations, each describing the motion of the microparticle. The model is solved using finite difference method; the solution provides the displacements of the microparticles, in the two directions, for the time duration of interest. The model is subsequently employed for parametric study. The parameters considered include the width of the microchannel, radius of microparticles, initial transverse displacement of the microparticle and volumetric flow rate. The primary application of this model article would be in the design process.
{"title":"Trajectory of microparticles actuated with standing surface acoustic waves in microfluidic devices","authors":"B. Mathew, A. Alazzam, S. Khashan, G. Destgeer, H. Sung","doi":"10.1109/RSM.2015.7354996","DOIUrl":"https://doi.org/10.1109/RSM.2015.7354996","url":null,"abstract":"This article deals with the development of a two-dimensional dynamic model for predicting the trajectory of microparticles in an acoustic field, associated with standing surface acoustic wave, on a continuous flow microfluidic device. The model consists of two governing equations, each describing the motion of the microparticle. The model is solved using finite difference method; the solution provides the displacements of the microparticles, in the two directions, for the time duration of interest. The model is subsequently employed for parametric study. The parameters considered include the width of the microchannel, radius of microparticles, initial transverse displacement of the microparticle and volumetric flow rate. The primary application of this model article would be in the design process.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"31 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89930525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7354992
A. F. Muhammad Alimin, S. F. Wan Muhamad Hatta, N. Soin
This paper presents a simulation framework for reliability analysis of PMOS devices in the TCAD Sentaurus environment. The degradation of parameter is based on the numerical solution for the two-stage NBTI model mechanism. We demonstrate and analyze the voltage degradation, Vth of a high-k HfO2 dielectric pMOSFET structure with effective oxide thickness (EOT) of 1.092 nm. After 1000s of stress, the threshold voltage shift of higher stress bias shows higher degradation (~0.07V) compared to the lower stress bias (~0.008V).
{"title":"A study of the states kinetics in NBTI degradation by two-stage NBTI model implementation","authors":"A. F. Muhammad Alimin, S. F. Wan Muhamad Hatta, N. Soin","doi":"10.1109/RSM.2015.7354992","DOIUrl":"https://doi.org/10.1109/RSM.2015.7354992","url":null,"abstract":"This paper presents a simulation framework for reliability analysis of PMOS devices in the TCAD Sentaurus environment. The degradation of parameter is based on the numerical solution for the two-stage NBTI model mechanism. We demonstrate and analyze the voltage degradation, Vth of a high-k HfO2 dielectric pMOSFET structure with effective oxide thickness (EOT) of 1.092 nm. After 1000s of stress, the threshold voltage shift of higher stress bias shows higher degradation (~0.07V) compared to the lower stress bias (~0.008V).","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"16 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78332382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7354993
DR.A.K.M ZAKIR HOSSAIN, M. Ibrahimy, S. Motakabber
Even though the UWB passive RFID is getting so much attention for the researchers with the goal of replacing the conventional barcode system, the tag dimension still remains as a big issue which makes the tag price comparatively higher than the barcode. Many proposals have been made for last one decade to overcome this problem. In this paper an approach has been made to combine two different methods with the aim to reduce the tag dimensions. Both, the new tag and the existing tag are simulated in the CST MWS. It has been observed that with the new design, a reduction of 15.5% and 6% are found in terms of the width and length respectively and that leads to a reduction in occupied area around 20%.
{"title":"Tag for UWB chipless RFID: A single antenna approach","authors":"DR.A.K.M ZAKIR HOSSAIN, M. Ibrahimy, S. Motakabber","doi":"10.1109/RSM.2015.7354993","DOIUrl":"https://doi.org/10.1109/RSM.2015.7354993","url":null,"abstract":"Even though the UWB passive RFID is getting so much attention for the researchers with the goal of replacing the conventional barcode system, the tag dimension still remains as a big issue which makes the tag price comparatively higher than the barcode. Many proposals have been made for last one decade to overcome this problem. In this paper an approach has been made to combine two different methods with the aim to reduce the tag dimensions. Both, the new tag and the existing tag are simulated in the CST MWS. It has been observed that with the new design, a reduction of 15.5% and 6% are found in terms of the width and length respectively and that leads to a reduction in occupied area around 20%.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"34 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73750494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7354990
F. A. Rezali, S. Hatta, N. Soin
Leakages and short channel effects (SCE) impose challenges in the designing of CMOS devices as the device feature size enters the nanoscale regime. Advanced process design of CMOS devices are crucial in countering the limitations impose by SCE. This paper investigates the advantages of implementing the halo process into the design of the submicron-CMOS devices. Critical device performance merits and CV characterizations were explored as the device is scaled. Although the use of halo degraded slightly the performance for typically long channel transistor, the merging of halo implants at short transistor shows improvement with high stability of threshold voltage and low off-current. The Drain-induced barrier lowering (DIBL) specifically for the 45nm pMOS and nMOS alone had reduced to 25% and 41% respectively. With careful optimal choice for heavy doped halo of and reverse body biasing, it simultaneously relieved total leakage current by adjusting the threshold voltage.
{"title":"Scaling impact on design performance metric of sub-micron CMOS devices incorporated with halo","authors":"F. A. Rezali, S. Hatta, N. Soin","doi":"10.1109/RSM.2015.7354990","DOIUrl":"https://doi.org/10.1109/RSM.2015.7354990","url":null,"abstract":"Leakages and short channel effects (SCE) impose challenges in the designing of CMOS devices as the device feature size enters the nanoscale regime. Advanced process design of CMOS devices are crucial in countering the limitations impose by SCE. This paper investigates the advantages of implementing the halo process into the design of the submicron-CMOS devices. Critical device performance merits and CV characterizations were explored as the device is scaled. Although the use of halo degraded slightly the performance for typically long channel transistor, the merging of halo implants at short transistor shows improvement with high stability of threshold voltage and low off-current. The Drain-induced barrier lowering (DIBL) specifically for the 45nm pMOS and nMOS alone had reduced to 25% and 41% respectively. With careful optimal choice for heavy doped halo of and reverse body biasing, it simultaneously relieved total leakage current by adjusting the threshold voltage.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"41 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82301553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7355009
I. Hermida, G. Wiranto, D. Mahmudin, K. Deni Permana, L. Utari, A. Setiawan
A study on fabrication of thick film Ag, Pd/Ag, and Au for microstrip band pass filter application using screen printing method has been carried out. Research carried out by making three band pass filter using conductor paste Au, Ag, and Pd/Ag. Band pass filters are designed at the operating center frequency 456 MHz, bandwidth of 60 MHz, 1 VSWR, and -93.55 dB loss. SEM, EDS and FTIR characterization conducted to determine morphology and content of microstrip band pass filter. Meanwhile, the performance of band pass filter was examined by using VNA SEM results indicate grain size conductor strip using Au, Ag, and Pd/Ag are 0.435 nm, 0.389 nm and 0.913 nm. The thickness of each conductor strips are 10.47μm, 12.98 μm and 14.15μm. Based on SEM results showed pores scattered on the surface of conductor strip, which causes the value loss increases. EDS and FTIR results indicate the presence of impurities C, N, O, H and Al on conductor strip of microstrip. The measurement of three band pass filter with VNA get the results that the center frequency 456 MHz, bandwidth of 60 MHz, 3 dB loss and 1.3 VSWR. Fabrication results indicate the value of loss and VSWR, higher than the design. It was due to conductor loss that occurs due to pore on the surface microstrip and also due to the impurity.
{"title":"Ag, Pd/Ag, and Au thick films growth using screen printing method for microstrip band pass filter application","authors":"I. Hermida, G. Wiranto, D. Mahmudin, K. Deni Permana, L. Utari, A. Setiawan","doi":"10.1109/RSM.2015.7355009","DOIUrl":"https://doi.org/10.1109/RSM.2015.7355009","url":null,"abstract":"A study on fabrication of thick film Ag, Pd/Ag, and Au for microstrip band pass filter application using screen printing method has been carried out. Research carried out by making three band pass filter using conductor paste Au, Ag, and Pd/Ag. Band pass filters are designed at the operating center frequency 456 MHz, bandwidth of 60 MHz, 1 VSWR, and -93.55 dB loss. SEM, EDS and FTIR characterization conducted to determine morphology and content of microstrip band pass filter. Meanwhile, the performance of band pass filter was examined by using VNA SEM results indicate grain size conductor strip using Au, Ag, and Pd/Ag are 0.435 nm, 0.389 nm and 0.913 nm. The thickness of each conductor strips are 10.47μm, 12.98 μm and 14.15μm. Based on SEM results showed pores scattered on the surface of conductor strip, which causes the value loss increases. EDS and FTIR results indicate the presence of impurities C, N, O, H and Al on conductor strip of microstrip. The measurement of three band pass filter with VNA get the results that the center frequency 456 MHz, bandwidth of 60 MHz, 3 dB loss and 1.3 VSWR. Fabrication results indicate the value of loss and VSWR, higher than the design. It was due to conductor loss that occurs due to pore on the surface microstrip and also due to the impurity.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"6 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82526801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7354968
Yasir Mahmood Al Kubaisi, W. Hasan, S. B. MOHD NOOR, N. Azis, A. Sabry
This work proposes a method to enhance the green power demands through providing an energy source which utilizes the kinetic green energy of the vehicles in multi-level car parking building, where vehicles are already climbing when the driver looking for space to park, and then climb down to go out the building with a kinetic energy due to ground gravity. A novel mechanism has been designed to generate electric power in each individual level from the car parking building, this individuality not only would generate more energy but also simplified the system and reduce the installation cost. The simulation result shows a significant energy value which could cover the demand of the parking place from the electricity, such as lighting, ventilation, barrier gate and CCTV.
{"title":"Investigation on self energized automated multi levels car parking system","authors":"Yasir Mahmood Al Kubaisi, W. Hasan, S. B. MOHD NOOR, N. Azis, A. Sabry","doi":"10.1109/RSM.2015.7354968","DOIUrl":"https://doi.org/10.1109/RSM.2015.7354968","url":null,"abstract":"This work proposes a method to enhance the green power demands through providing an energy source which utilizes the kinetic green energy of the vehicles in multi-level car parking building, where vehicles are already climbing when the driver looking for space to park, and then climb down to go out the building with a kinetic energy due to ground gravity. A novel mechanism has been designed to generate electric power in each individual level from the car parking building, this individuality not only would generate more energy but also simplified the system and reduce the installation cost. The simulation result shows a significant energy value which could cover the demand of the parking place from the electricity, such as lighting, ventilation, barrier gate and CCTV.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"5 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83724556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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