Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7354983
A. Huda, M. K. Md Arshad, N. Othman, C. Voon, R. M. Ayub, S. Gopinath, K. L. Foo, A. R. Ruslinda, U. Hashim, H. C. Lee, P. Adelyn, S. M. Kahar
In this paper, the effect of silicon body thickness (TSi) and silicon body width (WSi) variation on DC characteristics in 100 nm gate length silicon-on-insulator (SOI) junctionless (JL) and junction transistors has been investigated by using numerical simulations. The digital figure-of-merits characteristics such as threshold voltage (VTH), on-current, subthreshold voltage, and drain-induced-barrier-lowering are the main parameters that have been investigated. Based on the simulations, the JT device is less sensitive to variation of TSi and WSi compared to JLT.
{"title":"Impact of size variation in junctionless vs junction planar SOI n-MOSFET transistor","authors":"A. Huda, M. K. Md Arshad, N. Othman, C. Voon, R. M. Ayub, S. Gopinath, K. L. Foo, A. R. Ruslinda, U. Hashim, H. C. Lee, P. Adelyn, S. M. Kahar","doi":"10.1109/RSM.2015.7354983","DOIUrl":"https://doi.org/10.1109/RSM.2015.7354983","url":null,"abstract":"In this paper, the effect of silicon body thickness (TSi) and silicon body width (WSi) variation on DC characteristics in 100 nm gate length silicon-on-insulator (SOI) junctionless (JL) and junction transistors has been investigated by using numerical simulations. The digital figure-of-merits characteristics such as threshold voltage (VTH), on-current, subthreshold voltage, and drain-induced-barrier-lowering are the main parameters that have been investigated. Based on the simulations, the JT device is less sensitive to variation of TSi and WSi compared to JLT.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"85 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89438161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7354987
A. Iqbal, F. Mohd-Yasin
This paper compares the performances of seven different cantilever designs (straight beam, straight-tapered beam, T beam, U beam, V beam, V-T beam and Y beam) to be employed as a piezoelectric energy harvester. All cantilever structures employs the same materials i.e. Aluminium Nitride as piezo layer, Cubic Silicon Carbide as structural layer and Molybdenum as proof mass and electrical electrodes. We use the same thicknesses for these layers for all structures. Their performances are compared in term of resonant frequency, maximum displacement, open-circuit voltage and stress. The results reveal that V-T shaped cantilever beam energy harvester emerges as the overall winner.
{"title":"Comparison of seven cantilever designs for piezoelectric energy harvester based On Mo/AlN/3C-SiC","authors":"A. Iqbal, F. Mohd-Yasin","doi":"10.1109/RSM.2015.7354987","DOIUrl":"https://doi.org/10.1109/RSM.2015.7354987","url":null,"abstract":"This paper compares the performances of seven different cantilever designs (straight beam, straight-tapered beam, T beam, U beam, V beam, V-T beam and Y beam) to be employed as a piezoelectric energy harvester. All cantilever structures employs the same materials i.e. Aluminium Nitride as piezo layer, Cubic Silicon Carbide as structural layer and Molybdenum as proof mass and electrical electrodes. We use the same thicknesses for these layers for all structures. Their performances are compared in term of resonant frequency, maximum displacement, open-circuit voltage and stress. The results reveal that V-T shaped cantilever beam energy harvester emerges as the overall winner.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"21 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82139753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7354969
F. R. M. Rashidi, O. Hussein, W. Hasan
In this paper, fundamental theories in developing piezoresistive pressure sensor will be discussed and our work on designing a foot plantar measurement system as the application will be explained. The mathematical equations and design procedures will be elaborate while the practical application will be investigate, experimented and analyzed. Simulation results from design theory will also be included and finally the conclusion of the proposed piezoresistive pressure sensor will be discussed.
{"title":"Investigation on developing of a piezoresistive pressure sensor for foot plantar measurement system","authors":"F. R. M. Rashidi, O. Hussein, W. Hasan","doi":"10.1109/RSM.2015.7354969","DOIUrl":"https://doi.org/10.1109/RSM.2015.7354969","url":null,"abstract":"In this paper, fundamental theories in developing piezoresistive pressure sensor will be discussed and our work on designing a foot plantar measurement system as the application will be explained. The mathematical equations and design procedures will be elaborate while the practical application will be investigate, experimented and analyzed. Simulation results from design theory will also be included and finally the conclusion of the proposed piezoresistive pressure sensor will be discussed.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"55 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86206380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7355007
N. H. Seng, Amy Voo Mei Mei
Hot carrier (HCI) is typical reliability test in qualifying new MOSFET device specified in JEDEC JP001 [1]. The tests are normally conducted on wafer level (WLR) using a manual probe station or automatic tester with probe card. Packaged level reliability (PLR) test system is used as well to test the MOSFET device in parallel. PLR allows higher number of samples (device under test, DUT) to be tested within a much shorter time, even applying longer stress time. The electrical connection through package units, sockets, and test boards is expected more stable than probing contact between probe pads and probe needle tips. Hence, more consistent degradation among DUT-to-DUT and accurate lifetime extrapolation can be achieved. The correlation between WLR and PLR was studied for MOSFET devices with 3.3 volt operating condition and also 12V LDMOS device. The PLR showed higher HCI degradation compared to WLR for 12V LDMOS device, whereas comparable for MOSFET. This was very low level of device self-heating effect on LDMOS from characteristic curves. However, the heat dissipation from ceramic packages took time compared to large silicon wafer on probe chuck. The stress-induced heating impact on LDMOS is discussed in this paper.
{"title":"Impact of stress-induced heating on PLR and WLR HCI testing","authors":"N. H. Seng, Amy Voo Mei Mei","doi":"10.1109/RSM.2015.7355007","DOIUrl":"https://doi.org/10.1109/RSM.2015.7355007","url":null,"abstract":"Hot carrier (HCI) is typical reliability test in qualifying new MOSFET device specified in JEDEC JP001 [1]. The tests are normally conducted on wafer level (WLR) using a manual probe station or automatic tester with probe card. Packaged level reliability (PLR) test system is used as well to test the MOSFET device in parallel. PLR allows higher number of samples (device under test, DUT) to be tested within a much shorter time, even applying longer stress time. The electrical connection through package units, sockets, and test boards is expected more stable than probing contact between probe pads and probe needle tips. Hence, more consistent degradation among DUT-to-DUT and accurate lifetime extrapolation can be achieved. The correlation between WLR and PLR was studied for MOSFET devices with 3.3 volt operating condition and also 12V LDMOS device. The PLR showed higher HCI degradation compared to WLR for 12V LDMOS device, whereas comparable for MOSFET. This was very low level of device self-heating effect on LDMOS from characteristic curves. However, the heat dissipation from ceramic packages took time compared to large silicon wafer on probe chuck. The stress-induced heating impact on LDMOS is discussed in this paper.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"245 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91319529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7355016
Ahmad Mukifza, S. Yusof, Clarence M. Ongkudon, Eddy M. Farid, Huzaikha Binti Awang
A fast and easy method for preparing the titanium dioxide (TiO2), using a caustic hydrothermal decomposition conditions followed with sulphate process using sulfuric acid (H2SO4), is presented. Synthetic rutile waste as a starting raw material going through these two simple processes then the effects of acid concentration and time of sulphate process were studied. The chemical composition of the product will be characterized using Electron Dispersive (EDX) and the micrographs were analyzed using a Field Emission Scanning Electron Microscope (FESEM). This study shows that a titanium dioxide (TiO2) was successfully synthesized after treated with medium acid concentration, 1M to 3M and short treatment time, 3h to 5h sulphate process.
{"title":"Effect of acid concentration and time of sulphate process on synthesizing the titanium dioxide from synthetic rutile waste","authors":"Ahmad Mukifza, S. Yusof, Clarence M. Ongkudon, Eddy M. Farid, Huzaikha Binti Awang","doi":"10.1109/RSM.2015.7355016","DOIUrl":"https://doi.org/10.1109/RSM.2015.7355016","url":null,"abstract":"A fast and easy method for preparing the titanium dioxide (TiO2), using a caustic hydrothermal decomposition conditions followed with sulphate process using sulfuric acid (H2SO4), is presented. Synthetic rutile waste as a starting raw material going through these two simple processes then the effects of acid concentration and time of sulphate process were studied. The chemical composition of the product will be characterized using Electron Dispersive (EDX) and the micrographs were analyzed using a Field Emission Scanning Electron Microscope (FESEM). This study shows that a titanium dioxide (TiO2) was successfully synthesized after treated with medium acid concentration, 1M to 3M and short treatment time, 3h to 5h sulphate process.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"76 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83847569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7354986
Chu-Liang Lee, R. Sidek, F. Rokhani, N. Sulaiman
A low power Bandgap Voltage Reference (BGR) is designed to supply a voltage reference for a low voltage Low-Dropout Regulator (LDO). This bandgap design consists of a bandgap core circuit, an output stage and a start-up circuit. The output of the bandgap adopted sub-1V voltage reference through the output stage circuit. The bandgap is simulated using 0.13 μm CMOS process. This BGR circuit provides voltage reference of 64mV± 1mV over -25°C to 120°C temperature range. The power supply of this BGR circuit is 1.20 V and the total current is 20 μA, thus resulting a low total power consumption of 24μW. The total layout area for this bandgap design is 66μm × 100μm.
{"title":"A low power bandgap voltage reference for Low-Dropout Regulator","authors":"Chu-Liang Lee, R. Sidek, F. Rokhani, N. Sulaiman","doi":"10.1109/RSM.2015.7354986","DOIUrl":"https://doi.org/10.1109/RSM.2015.7354986","url":null,"abstract":"A low power Bandgap Voltage Reference (BGR) is designed to supply a voltage reference for a low voltage Low-Dropout Regulator (LDO). This bandgap design consists of a bandgap core circuit, an output stage and a start-up circuit. The output of the bandgap adopted sub-1V voltage reference through the output stage circuit. The bandgap is simulated using 0.13 μm CMOS process. This BGR circuit provides voltage reference of 64mV± 1mV over -25°C to 120°C temperature range. The power supply of this BGR circuit is 1.20 V and the total current is 20 μA, thus resulting a low total power consumption of 24μW. The total layout area for this bandgap design is 66μm × 100μm.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"15 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88768135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7354964
S. G. Ling, M. Hamidon, Z. Yunusa
This paper presents the relationship of parallel resistor to the frequency response of the passive remote acoustic wave resonators (SAWRs) sensor system in 433.42MHz and 433.92MHz. Impedance matching is achieved with the connection of L-network to the parallel SAW resonator. The main objective of this finding is to improve the sensor of narrow bandwidth application. Circuit with high quality factor (Q factor) has better suppression for narrow band application. Parallel resistor improves the system by increasing the Q factor. Increasing the parallel resistance will decreased the bandwidth of the resonant frequency. Simulation results of the system are presented and discussed.
{"title":"Relation of parallel resistance to the passive double SAW resonator","authors":"S. G. Ling, M. Hamidon, Z. Yunusa","doi":"10.1109/RSM.2015.7354964","DOIUrl":"https://doi.org/10.1109/RSM.2015.7354964","url":null,"abstract":"This paper presents the relationship of parallel resistor to the frequency response of the passive remote acoustic wave resonators (SAWRs) sensor system in 433.42MHz and 433.92MHz. Impedance matching is achieved with the connection of L-network to the parallel SAW resonator. The main objective of this finding is to improve the sensor of narrow bandwidth application. Circuit with high quality factor (Q factor) has better suppression for narrow band application. Parallel resistor improves the system by increasing the Q factor. Increasing the parallel resistance will decreased the bandwidth of the resonant frequency. Simulation results of the system are presented and discussed.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"2 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73079605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7355011
S. Suhaimi, M. Shahimin, S. Z. Siddick, B. Razak, M. H. C. Mat
Dye-sensitized solar cells containing yellow curcumin of Harum Manis mango were extracted in water and ethanol solvent and fabricated at different temperatures to find the optimum condition with the best performance solar cell. Harum Manis mango was studied as an alternative sensitizer, that anchored to a nanoparticle titanium dioxide scaffold, due to its availability in native Malaysia climate. The absorption spectrum of each dye was measured using ultraviolet-visible spectroscopy. The absorption spectrum shows an absorption peak at 450nm in water and a broader absorption in the ethanol. The conversion efficiency achieved by dyes extracted in water and ethanol solvent at room temperature is about 0.03% and 0.51%. When temperature parameter is varied (room temperature, 50°C, 75°C, and 100°C), dye extracted in water solvent attains its highest efficiency of about 0.60% and 0.32% in ethanol at 50°C. In fact, 50°C extracting temperature in water solvent shows as an optimum condition for Harum Manis mango to achieve its best performance. This paper reveals detailed optimization of fabrication process at different extracting temperatures for Harum Manis mango photosensitizer based solar cells which can be used as an environmental friendly, low cost alternative system especially for further research in DSSCs technology.
{"title":"Effect of Harum Manis mango as natural photosensitizer at different extracting temperature on performance of dye-sensitized solar cells (DSSCs)","authors":"S. Suhaimi, M. Shahimin, S. Z. Siddick, B. Razak, M. H. C. Mat","doi":"10.1109/RSM.2015.7355011","DOIUrl":"https://doi.org/10.1109/RSM.2015.7355011","url":null,"abstract":"Dye-sensitized solar cells containing yellow curcumin of Harum Manis mango were extracted in water and ethanol solvent and fabricated at different temperatures to find the optimum condition with the best performance solar cell. Harum Manis mango was studied as an alternative sensitizer, that anchored to a nanoparticle titanium dioxide scaffold, due to its availability in native Malaysia climate. The absorption spectrum of each dye was measured using ultraviolet-visible spectroscopy. The absorption spectrum shows an absorption peak at 450nm in water and a broader absorption in the ethanol. The conversion efficiency achieved by dyes extracted in water and ethanol solvent at room temperature is about 0.03% and 0.51%. When temperature parameter is varied (room temperature, 50°C, 75°C, and 100°C), dye extracted in water solvent attains its highest efficiency of about 0.60% and 0.32% in ethanol at 50°C. In fact, 50°C extracting temperature in water solvent shows as an optimum condition for Harum Manis mango to achieve its best performance. This paper reveals detailed optimization of fabrication process at different extracting temperatures for Harum Manis mango photosensitizer based solar cells which can be used as an environmental friendly, low cost alternative system especially for further research in DSSCs technology.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"82 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74556801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7354991
I. N. Abdullah Khafit, A. F. Muhammad Alimin, S. F. Wan Muhamad Hatta, N. Soin
Lifetime of pMOSFETs is limited by negative bias temperature instability (NBTI). NBTI causes the degradation of drive current and threshold voltage of p-MOSFETs. This paper presents the comparison of DC and pulse train analysis on sub micrometer pMOSFETs lifetime prediction using on-the-fly (OTF) method. The SiO2 conventional PMOS transistor having effective oxide thickness (EOT) between 1.8nm and 2.8nm were simulated by applying various simulation conditions. The lifetime prediction was studied by varying the stress voltage and size of EOT for pMOSFETs. Results of this simulation demonstrate the impact of EOT variability on operational voltage, Vgop and interface trap vs stress time for both DC and pulse train analysis.
{"title":"Comparison of DC and pulse train analysis on submicrometer pMOSFETs lifetime prediction using on-the-fly method","authors":"I. N. Abdullah Khafit, A. F. Muhammad Alimin, S. F. Wan Muhamad Hatta, N. Soin","doi":"10.1109/RSM.2015.7354991","DOIUrl":"https://doi.org/10.1109/RSM.2015.7354991","url":null,"abstract":"Lifetime of pMOSFETs is limited by negative bias temperature instability (NBTI). NBTI causes the degradation of drive current and threshold voltage of p-MOSFETs. This paper presents the comparison of DC and pulse train analysis on sub micrometer pMOSFETs lifetime prediction using on-the-fly (OTF) method. The SiO2 conventional PMOS transistor having effective oxide thickness (EOT) between 1.8nm and 2.8nm were simulated by applying various simulation conditions. The lifetime prediction was studied by varying the stress voltage and size of EOT for pMOSFETs. Results of this simulation demonstrate the impact of EOT variability on operational voltage, Vgop and interface trap vs stress time for both DC and pulse train analysis.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87059942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/RSM.2015.7355020
A. Mohmad, B. Majlis, F. Bastiman, R. Richards, J. David
The quality of GaAsBi samples grown under various conditions were investigated by photoluminescence (PL) and atomic force microscopy (AFM). The samples were grown by molecular beam epitaxy at a rate of 0.36 and 0.61 μm/h. For each growth rates, three samples were grown under different Bi fluxes. For samples grown at a rate of 0.36 μm/h, the PL peak wavelength was red-shifted from 1103 to 1241 nm as the Bi flux was increased from 0.53 to 1.0 × 10-7 mBar. However, for sample grown with the highest Bi flux, the optical quality degraded showing a weak and broad PL spectrum. The AFM image shows that the sample grown with Bi flux of 0.53 × 10-7 mBar has a smooth surface with rms roughness of 0.78 nm. However, the presence of Bi droplets was observed for samples grown with higher Bi fluxes. A similar PL trend was also observed for samples grown at 0.61 μm/h. The results indicate that high Bi flux may increase the incorporation of Bi into GaAs but it is limited by the formation of Bi droplets.
{"title":"The effect of growth conditions to the optical quality of GaAsBi alloy","authors":"A. Mohmad, B. Majlis, F. Bastiman, R. Richards, J. David","doi":"10.1109/RSM.2015.7355020","DOIUrl":"https://doi.org/10.1109/RSM.2015.7355020","url":null,"abstract":"The quality of GaAsBi samples grown under various conditions were investigated by photoluminescence (PL) and atomic force microscopy (AFM). The samples were grown by molecular beam epitaxy at a rate of 0.36 and 0.61 μm/h. For each growth rates, three samples were grown under different Bi fluxes. For samples grown at a rate of 0.36 μm/h, the PL peak wavelength was red-shifted from 1103 to 1241 nm as the Bi flux was increased from 0.53 to 1.0 × 10-7 mBar. However, for sample grown with the highest Bi flux, the optical quality degraded showing a weak and broad PL spectrum. The AFM image shows that the sample grown with Bi flux of 0.53 × 10-7 mBar has a smooth surface with rms roughness of 0.78 nm. However, the presence of Bi droplets was observed for samples grown with higher Bi fluxes. A similar PL trend was also observed for samples grown at 0.61 μm/h. The results indicate that high Bi flux may increase the incorporation of Bi into GaAs but it is limited by the formation of Bi droplets.","PeriodicalId":6667,"journal":{"name":"2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)","volume":"32 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74289567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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