Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776554
Shengqiang Xu, Kaizhen Han, Yi-Chiau Huang, Yuye Kang, S. Masudy‐Panah, Ying Wu, D. Lei, Yunshan Zhao, X. Gong, Y. Yeo
We report the first demonstration of high performance germanium-tin (GeSn) multiple-quantum-well (MQW) photodiode (PD) on a 200 mm GeOI platform realized using a low temperature wafer bonding process. Record-low leakage of 25 mA/cm2 was achieved for GeSn PDs using this new architecture. Both Ge p-and n-FinFETs were also realized on the GeOI platform to substantiate the promising monolithic integration of all GeOI-based photonics components with Ge CMOS on this architecture via top-down processing approach. This work paves way for advanced optoelectronic integrated circuits (OEIC) operating at $2 mu text{m}$ band and beyond using GeSn as photo detection material for communication and sensing applications.
我们报道了在200 mm GeOI平台上使用低温晶圆键合工艺实现的高性能锗锡(GeSn)多量子阱(MQW)光电二极管(PD)的首次演示。使用这种新结构的GeSn pd实现了创纪录的低泄漏25 mA/cm2。Ge p- finfet和n- finfet也在GeOI平台上实现，通过自上而下的处理方法，在该架构上实现了所有基于GeOI的光子元件与Ge CMOS的有前途的单片集成。这项工作为工作在$2 mu text{m}$波段的先进光电集成电路(OEIC)铺平了道路，并使用GeSn作为通信和传感应用的光检测材料。
{"title":"High Performance GeSn Photodiode on a 200 mm Ge-on-insulator Photonics Platform for Advanced Optoelectronic Integration with Ge CMOS Operating at 2 μm Band","authors":"Shengqiang Xu, Kaizhen Han, Yi-Chiau Huang, Yuye Kang, S. Masudy‐Panah, Ying Wu, D. Lei, Yunshan Zhao, X. Gong, Y. Yeo","doi":"10.23919/VLSIT.2019.8776554","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776554","url":null,"abstract":"We report the first demonstration of high performance germanium-tin (GeSn) multiple-quantum-well (MQW) photodiode (PD) on a 200 mm GeOI platform realized using a low temperature wafer bonding process. Record-low leakage of 25 mA/cm2 was achieved for GeSn PDs using this new architecture. Both Ge p-and n-FinFETs were also realized on the GeOI platform to substantiate the promising monolithic integration of all GeOI-based photonics components with Ge CMOS on this architecture via top-down processing approach. This work paves way for advanced optoelectronic integrated circuits (OEIC) operating at $2 mu text{m}$ band and beyond using GeSn as photo detection material for communication and sensing applications.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"1 1","pages":"T176-T177"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88500091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776481
R. Southwick, M. Wang, S. Mochizuki, Xin He Miao, J. Li, C. Lee
Breakdown and bias temperature instability for n/pFETs are studied on a wide composition of SiGe channels on different strain relaxation buffers. This study represents the first in-depth look at AC/DC PBTI trends of low Ge% SiGe nFinFETs. Dielectric breakdown is shown to be largely independent of channel composition over the region studied. Finally, we calculate the end-of-life performance benefit compared to Si, demonstrating the potential benefit of CMOS SiGe as a technology element.
{"title":"SiGe Channel CMOS: Understanding Dielectric Breakdown and Bias Temperature Instability Tradeoffs","authors":"R. Southwick, M. Wang, S. Mochizuki, Xin He Miao, J. Li, C. Lee","doi":"10.23919/VLSIT.2019.8776481","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776481","url":null,"abstract":"Breakdown and bias temperature instability for n/pFETs are studied on a wide composition of SiGe channels on different strain relaxation buffers. This study represents the first in-depth look at AC/DC PBTI trends of low Ge% SiGe nFinFETs. Dielectric breakdown is shown to be largely independent of channel composition over the region studied. Finally, we calculate the end-of-life performance benefit compared to Si, demonstrating the potential benefit of CMOS SiGe as a technology element.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"36 1","pages":"T96-T97"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90848178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.23919/VLSIT.2019.8776515
E. Hsieh, H. W. Wang, C. H. Liu, S. Chung, T. P. Chen, S.A. Huang, T. J. Chen, O. Cheng
In this work, a novel concept of 2-bit-per-cell (2B/C) is introduced to realize high-density OTP PUF from a new scheme of dielectric breakdown. This PUF shows $10^{5}{text{x}}$ of large window, good immunity to high-temperature disturbance, and excellent retention under 150°C baking, which are particularly for automotive applications. In terms of security, this PUF exhibits near ideal normal distribution of hamming distance and narrow distribution of hamming weight. The bit error rates are low, 0.78% at 25°C and 1.95% at 150°C, benchmarked on a 256-bit array. Finally, the security test of this PUF against the hackers' attack from the machine learning process has been proved to have high security. Overall, the proposed 2B/C OTP PUF demonstrated great potential for IoT security in 5G era.
{"title":"Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era","authors":"E. Hsieh, H. W. Wang, C. H. Liu, S. Chung, T. P. Chen, S.A. Huang, T. J. Chen, O. Cheng","doi":"10.23919/VLSIT.2019.8776515","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776515","url":null,"abstract":"In this work, a novel concept of 2-bit-per-cell (2B/C) is introduced to realize high-density OTP PUF from a new scheme of dielectric breakdown. This PUF shows $10^{5}{text{x}}$ of large window, good immunity to high-temperature disturbance, and excellent retention under 150°C baking, which are particularly for automotive applications. In terms of security, this PUF exhibits near ideal normal distribution of hamming distance and narrow distribution of hamming weight. The bit error rates are low, 0.78% at 25°C and 1.95% at 150°C, benchmarked on a 256-bit array. Finally, the security test of this PUF against the hackers' attack from the machine learning process has been proved to have high security. Overall, the proposed 2B/C OTP PUF demonstrated great potential for IoT security in 5G era.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"24 1","pages":"T118-T119"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82784526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.23919/VLSIT.2019.8776508
Y. Tang, Che-Lun Fan, Ya-Chen Kao, N. Módolo, C. Su, T.-L. Wu, K. Kao, Pin-Jiun Wu, S.-W. Hsaio, A. Useinov, P. Su, W. Wu, G. Huang, J. Shieh, W. Yeh, Y. Wang
This paper clarifies for the first time the origin of ferroelectricity in the Negative Capacitance Field-Effect Transistors (NCFETs) by molecular dynamics (MD) simulation. MD simulation considering atomic interactions between all atoms enables accurate predictions for the microstructure even at all interfaces. By incorporating the results from MD simulations into a kinetic model, it is able to predict the conditions of crystallization and phase transition during RTP and cooling processes that govern ferroelectricity in FETs. Our simulation reveals that the comparable interfacial energy between o-and t-phase, and in-plane tensile stress from metal capping or interfacial layers (ILs) enable more phase transition from t-to o-phase, and more ferroelectricity in NCFETs. Finally, design methodology to maintain the electric variation of NCFETs is also proposed
{"title":"A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs","authors":"Y. Tang, Che-Lun Fan, Ya-Chen Kao, N. Módolo, C. Su, T.-L. Wu, K. Kao, Pin-Jiun Wu, S.-W. Hsaio, A. Useinov, P. Su, W. Wu, G. Huang, J. Shieh, W. Yeh, Y. Wang","doi":"10.23919/VLSIT.2019.8776508","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776508","url":null,"abstract":"This paper clarifies for the first time the origin of ferroelectricity in the Negative Capacitance Field-Effect Transistors (NCFETs) by molecular dynamics (MD) simulation. MD simulation considering atomic interactions between all atoms enables accurate predictions for the microstructure even at all interfaces. By incorporating the results from MD simulations into a kinetic model, it is able to predict the conditions of crystallization and phase transition during RTP and cooling processes that govern ferroelectricity in FETs. Our simulation reveals that the comparable interfacial energy between o-and t-phase, and in-plane tensile stress from metal capping or interfacial layers (ILs) enable more phase transition from t-to o-phase, and more ferroelectricity in NCFETs. Finally, design methodology to maintain the electric variation of NCFETs is also proposed","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"1 1","pages":"T222-T223"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90977213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.23919/VLSIT.2019.8776550
Yu-Shiang Huang, Hung-Yu Ye, Fang-Liang Lu, Yi-Chun Liu, Chien-Te Tu, Chung-yi Lin, Shih-Ya Lin, Sun-Rang Jan, C. W. Liu
The natural etching stop on {111} facets yields the small dangling bond density and roughness, enabling low SS and high $text{I}_{text{ON}}$ on {111} sidewalls of the GAA channels. In addition, the $sim 2%$ uniaxial compressive strain and $[text{Sn}]=9%$ in the channel can reduce the hole effective mass. As a result, 50% improvement of $text{I}_{text{ON}}= 120mu text{A}/mutext{m}$ (perimeter), and 71% improvement of $text{G}_{text{m}}=312mu text{S}/mutext{m}$ are achieved than our previous 3 stacked GeSn {001} nanosheets. Record high $text{I}_{text{ON}}$ of $19.3mu text{A}$ per stack at $text{V}_{text{OV}}=text{V}_{DS}=-0.5text{V}$ and record $text{G}_{text{m}}$ of $50.2mutext{S}$ per stack at $text{V}_{text{DS}}=-0.5text{V}$ among all GeSn FinFETs and GAAFETs are achieved. The $text{SS}_{text{lin}}$ as low as S4mV/dec is also obtained, 22% reduction than our previous work.
111{个刻面上的自然蚀刻停止产生小的悬垂键密度和粗糙度，从而在GAA通道的}111个侧壁上实现低SS和高$text{I}_{text{ON}}$。此外，通道内的{}$sim 2%$单轴压缩应变和$[text{Sn}]=9%$可以降低孔洞的有效质量。结果是，50% improvement of $text{I}_{text{ON}}= 120mu text{A}/mutext{m}$ (perimeter), and 71% improvement of $text{G}_{text{m}}=312mu text{S}/mutext{m}$ are achieved than our previous 3 stacked GeSn {001} nanosheets. Record high $text{I}_{text{ON}}$ of $19.3mu text{A}$ per stack at $text{V}_{text{OV}}=text{V}_{DS}=-0.5text{V}$ and record $text{G}_{text{m}}$ of $50.2mutext{S}$ per stack at $text{V}_{text{DS}}=-0.5text{V}$ among all GeSn FinFETs and GAAFETs are achieved. The $text{SS}_{text{lin}}$ as low as S4mV/dec is also obtained, 22% reduction than our previous work.
{"title":"First Vertically Stacked, Compressively Strained, and Triangular Ge0.91Sn0.09pGAAFETs with High $mathbf{I_{ON}}$ of $mathbf{19.3}mu mathbf{A} mathbf{at} mathbf{V_{OV}}=mathbf{V}_{mathbf{DS}}=mathbf{-0.5V}, mathbf{G}_{mathbf{m}}$ of $mathbf{50.2}mu mathbf{S}$ at $mathbf{V_{DS}}=mat","authors":"Yu-Shiang Huang, Hung-Yu Ye, Fang-Liang Lu, Yi-Chun Liu, Chien-Te Tu, Chung-yi Lin, Shih-Ya Lin, Sun-Rang Jan, C. W. Liu","doi":"10.23919/VLSIT.2019.8776550","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776550","url":null,"abstract":"The natural etching stop on {111} facets yields the small dangling bond density and roughness, enabling low SS and high <tex>$text{I}_{text{ON}}$</tex> on {111} sidewalls of the GAA channels. In addition, the <tex>$sim 2%$</tex> uniaxial compressive strain and <tex>$[text{Sn}]=9%$</tex> in the channel can reduce the hole effective mass. As a result, 50% improvement of <tex>$text{I}_{text{ON}}= 120mu text{A}/mutext{m}$</tex> (perimeter), and 71% improvement of <tex>$text{G}_{text{m}}=312mu text{S}/mutext{m}$</tex> are achieved than our previous 3 stacked GeSn {001} nanosheets. Record high <tex>$text{I}_{text{ON}}$</tex> of <tex>$19.3mu text{A}$</tex> per stack at <tex>$text{V}_{text{OV}}=text{V}_{DS}=-0.5text{V}$</tex> and record <tex>$text{G}_{text{m}}$</tex> of <tex>$50.2mutext{S}$</tex> per stack at <tex>$text{V}_{text{DS}}=-0.5text{V}$</tex> among all GeSn FinFETs and GAAFETs are achieved. The <tex>$text{SS}_{text{lin}}$</tex> as low as S4mV/dec is also obtained, 22% reduction than our previous work.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"1 1","pages":"T180-T181"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88690183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.23919/VLSIT.2019.8776482
Chien Liu, Hsuan-Han Chen, Chih-Chieh Hsu, C. Fan, H. Hsu, Chun‐Hu Cheng
We demonstrated that the 2.5nm-thick HfAIOx N-type NCFET based on defect-passivated multidomain switching can achieve a minimum 9 mV/dec subthreshold swing $(SS)$, a negligible hysteresis of 1mV, an ultralow $I_{off}$ of $135 text{fA}/mu text{m}$, a large $I_{on}/I_{0ff}$ ratio of $8.7times 10^{7}$ and a sub-60 mV/dec SS over 5 decade. For P-type NCFET, the non-hysteretic steep-slope switch is still reached under the synergistic effect of gate stress, defect passivation and doping engineering. The Al doping and defect passivation play the key role for reducing trap-related leakage, enhancing NC, and stabilizing multidomain switching. The highly scaled HfAIOx CMOS NCFET shows the potential for low power logic applications.
{"title":"Negative Capacitance CMOS Field-Effect Transistors with Non-Hysteretic Steep Sub-60mV/dec Swing and Defect-Passivated Multidomain Switching","authors":"Chien Liu, Hsuan-Han Chen, Chih-Chieh Hsu, C. Fan, H. Hsu, Chun‐Hu Cheng","doi":"10.23919/VLSIT.2019.8776482","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776482","url":null,"abstract":"We demonstrated that the 2.5nm-thick HfAIOx N-type NCFET based on defect-passivated multidomain switching can achieve a minimum 9 mV/dec subthreshold swing $(SS)$, a negligible hysteresis of 1mV, an ultralow $I_{off}$ of $135 text{fA}/mu text{m}$, a large $I_{on}/I_{0ff}$ ratio of $8.7times 10^{7}$ and a sub-60 mV/dec SS over 5 decade. For P-type NCFET, the non-hysteretic steep-slope switch is still reached under the synergistic effect of gate stress, defect passivation and doping engineering. The Al doping and defect passivation play the key role for reducing trap-related leakage, enhancing NC, and stabilizing multidomain switching. The highly scaled HfAIOx CMOS NCFET shows the potential for low power logic applications.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"22 1","pages":"T224-T225"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83829286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.23919/VLSIT.2019.8776488
E. Hsieh, H. Chang, S. Chung, T. P. Chen, S. A. Huang, T. J. Chen, O. Cheng, S. Wong
In this work, we will explore pure logic FinFET devices to realize the functionality of linear weight tuning capability as electric synapses. The unit cell of this new FinFET synapse is composed of two identical FinFETs in series; one serves as control and the other one as storage. This new FinFET synapse exhibits ideal linearity with nearly infinity training cycles $(> 10^{12})$, much lower programming voltage, 0.85V, and faster speed, 2.5ns. It can also analogically increase or decrease the transistor's $text{v}_{text{th}}$ to vary the drain conductance. As far as the analog performance is concerned, it performs excellent linearity and a wide tuning-window (20x) of weight-tuning capability. lkb synaptic array has also been designed. The spice-simulated results have shown that new FinFET synaptic array can expand the array-size to 64×64, exhibiting 300x of SNR, w.r.t. that of RRAM array. Finally, the training of the neural network based on the proposed FinFET synapse can achieve 97.43% accuracy as high as the GPU one does.
{"title":"A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 1012 Endurance","authors":"E. Hsieh, H. Chang, S. Chung, T. P. Chen, S. A. Huang, T. J. Chen, O. Cheng, S. Wong","doi":"10.23919/VLSIT.2019.8776488","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776488","url":null,"abstract":"In this work, we will explore pure logic FinFET devices to realize the functionality of linear weight tuning capability as electric synapses. The unit cell of this new FinFET synapse is composed of two identical FinFETs in series; one serves as control and the other one as storage. This new FinFET synapse exhibits ideal linearity with nearly infinity training cycles $(> 10^{12})$, much lower programming voltage, 0.85V, and faster speed, 2.5ns. It can also analogically increase or decrease the transistor's $text{v}_{text{th}}$ to vary the drain conductance. As far as the analog performance is concerned, it performs excellent linearity and a wide tuning-window (20x) of weight-tuning capability. lkb synaptic array has also been designed. The spice-simulated results have shown that new FinFET synaptic array can expand the array-size to 64×64, exhibiting 300x of SNR, w.r.t. that of RRAM array. Finally, the training of the neural network based on the proposed FinFET synapse can achieve 97.43% accuracy as high as the GPU one does.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"11 1","pages":"T138-T139"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78828366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-04-25DOI: 10.1109/VTSA.2005.1497061
H. Houten
Ambient intelligence has been defined as digital environments that are sensitive and responsive to the presence of people. It is not a purely technical vision, but a people oriented vision. The emotional dimension is crucial. In this sense it can be seen as a marriage of the unobtrusive computing world of Mark Weiser (1993), and the sociological vision of human-media interaction of Nass and Reeves (1998). What does it take for an environment to be truly "ambient intelligent"? A key requirement is that many invisible or unobtrusive devices should be distributed throughout the environment. These should be context aware, in that they should know about their situational state. These devices should also be personalized, so that their function is tailored towards a specific user's needs. They should be adaptive, able to learn and to recognize people. Ultimately, they should be anticipatory, in that the user's desires are anticipated without the need for input by commands.
{"title":"The physical layer of ambient intelligence","authors":"H. Houten","doi":"10.1109/VTSA.2005.1497061","DOIUrl":"https://doi.org/10.1109/VTSA.2005.1497061","url":null,"abstract":"Ambient intelligence has been defined as digital environments that are sensitive and responsive to the presence of people. It is not a purely technical vision, but a people oriented vision. The emotional dimension is crucial. In this sense it can be seen as a marriage of the unobtrusive computing world of Mark Weiser (1993), and the sociological vision of human-media interaction of Nass and Reeves (1998). What does it take for an environment to be truly \"ambient intelligent\"? A key requirement is that many invisible or unobtrusive devices should be distributed throughout the environment. These should be context aware, in that they should know about their situational state. These devices should also be personalized, so that their function is tailored towards a specific user's needs. They should be adaptive, able to learn and to recognize people. Ultimately, they should be anticipatory, in that the user's desires are anticipated without the need for input by commands.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"31 1","pages":"9-12"},"PeriodicalIF":0.0,"publicationDate":"2005-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80362816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015438
H. Meer, K. Meyer
High-performance fully-depleted SOI CMOS transistors have been realized on a 28 nm ultra thin silicon substrate with a physical gate length of 70 nm and a post NO-annealed gate oxide of 1.4 nm. A new fabrication scheme, the spacer/replacer scheme, has been used to optimize the device performance of the ultra thin-film SOI transistors. Excellent device performance has been obtained: I/sub on/ equals 711 /spl mu/A//spl mu/m and 350 /spl mu/A//spl mu/m at I/sub off/=16 nA//spl mu/m for nMOS and pMOS, respectively. The unloaded ring oscillator gate-delay is 14.5 ps at V/sub DD/=1.2 V.
{"title":"70 nm fully-depleted SOI CMOS using a new fabrication scheme: the spacer/replacer scheme","authors":"H. Meer, K. Meyer","doi":"10.1109/VLSIT.2002.1015438","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015438","url":null,"abstract":"High-performance fully-depleted SOI CMOS transistors have been realized on a 28 nm ultra thin silicon substrate with a physical gate length of 70 nm and a post NO-annealed gate oxide of 1.4 nm. A new fabrication scheme, the spacer/replacer scheme, has been used to optimize the device performance of the ultra thin-film SOI transistors. Excellent device performance has been obtained: I/sub on/ equals 711 /spl mu/A//spl mu/m and 350 /spl mu/A//spl mu/m at I/sub off/=16 nA//spl mu/m for nMOS and pMOS, respectively. The unloaded ring oscillator gate-delay is 14.5 ps at V/sub DD/=1.2 V.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"47 1","pages":"170-171"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74069364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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