Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776486
C.C. Hu, M.F. Chen, W. Chiou, Doug C. H. Yu
The electrical characterization of System on Integrated Chips (SoIC™), an innovative 3D heterogeneous integration technology manufactured in front-end of line with known-good-die is reported. Chiplets integration of devices including foundry leading edge 7nm FinFET technology with SoIC™ illustrates its advantages in high bandwidth density and high power efficiency, as compared with 2.5D and conventional 3D-IC with micro-bump/TSV.
{"title":"3D Multi-chip Integration with System on Integrated Chips (SoIC™)","authors":"C.C. Hu, M.F. Chen, W. Chiou, Doug C. H. Yu","doi":"10.23919/VLSIT.2019.8776486","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776486","url":null,"abstract":"The electrical characterization of System on Integrated Chips (SoIC™), an innovative 3D heterogeneous integration technology manufactured in front-end of line with known-good-die is reported. Chiplets integration of devices including foundry leading edge 7nm FinFET technology with SoIC™ illustrates its advantages in high bandwidth density and high power efficiency, as compared with 2.5D and conventional 3D-IC with micro-bump/TSV.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"86 1","pages":"T20-T21"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75109116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776565
C. Matsui, S. Fukuyama, Atsuna Hayakawa, K. Takeuchi
This paper proposes Variability-Aware Approximate Computing (V-AC) for TaOx ReRAM storage at data centers. For the first time, this paper shows that application-induced variability degrades the performance. To solve this problem, V-AC utilizes error resilience of machine learning (ML) application and reduces bit-error rate (BER) of typical cells by removing extra data copy and enlarging BER difference among cells. By combining device measurement and system emulations, this paper realizes system, circuit and device codesign (SCDCD). V-AC is key enabling technology to push the limits of performance, power, chip size and scaling of ReRAM for ML. Performance, energy and cell area of ReRAM storage improves by 7.0 times, 90% and 8.5%, respectively.
{"title":"Application-Induced Cell Reliability Variability-Aware Approximate Computing in TaOx-based ReRAM Data Center Storage for Machine Learning","authors":"C. Matsui, S. Fukuyama, Atsuna Hayakawa, K. Takeuchi","doi":"10.23919/VLSIT.2019.8776565","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776565","url":null,"abstract":"This paper proposes Variability-Aware Approximate Computing (V-AC) for TaOx ReRAM storage at data centers. For the first time, this paper shows that application-induced variability degrades the performance. To solve this problem, V-AC utilizes error resilience of machine learning (ML) application and reduces bit-error rate (BER) of typical cells by removing extra data copy and enlarging BER difference among cells. By combining device measurement and system emulations, this paper realizes system, circuit and device codesign (SCDCD). V-AC is key enabling technology to push the limits of performance, power, chip size and scaling of ReRAM for ML. Performance, energy and cell area of ReRAM storage improves by 7.0 times, 90% and 8.5%, respectively.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"29 1","pages":"T234-T235"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74480599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776546
Q. Luo, Jie Yu, Xumeng Zhang, K. Xue, J. Yuan, Yan Cheng, Tiancheng Gong, H. Lv, Xiaoxin Xu, Peng Yuan, Jiahao Yin, L. Tai, S. Long, Qi Liu, X. Miao, Jing Li, Ming Liu
In this work, we demonstrate a high performance Nb1-xO2 based selector with thermal feedback mechanism for 3D X-point application. Ultra-high endurance $(> 10^{12})$, high operation speed (10ns), bidirectional operation and excellent Vth stability were achieved. By adding a barrier layer between Nb1-xO2 film and electrode, the off-state leakage current was reduced by one order of magnitude (selectivity as high as 500). This work provides a universal selector solution for various emerging memories, including RRAM, MRAM and PCM.
{"title":"Nb1-xO2 based Universal Selector with Ultra-high Endurance (>1012), high speed (10ns) and Excellent Vth Stability","authors":"Q. Luo, Jie Yu, Xumeng Zhang, K. Xue, J. Yuan, Yan Cheng, Tiancheng Gong, H. Lv, Xiaoxin Xu, Peng Yuan, Jiahao Yin, L. Tai, S. Long, Qi Liu, X. Miao, Jing Li, Ming Liu","doi":"10.23919/VLSIT.2019.8776546","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776546","url":null,"abstract":"In this work, we demonstrate a high performance Nb<inf>1-</inf><inf>x</inf>O<inf>2</inf> based selector with thermal feedback mechanism for 3D X-point application. Ultra-high endurance <tex>$(> 10^{12})$</tex>, high operation speed (10ns), bidirectional operation and excellent V<inf>th</inf> stability were achieved. By adding a barrier layer between Nb<inf>1-x</inf>O<inf>2</inf> film and electrode, the off-state leakage current was reduced by one order of magnitude (selectivity as high as 500). This work provides a universal selector solution for various emerging memories, including RRAM, MRAM and PCM.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"1 1","pages":"T236-T237"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81079258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776570
O. Golonzka, U. Arslan, P. Bai, M. Bohr, O. Baykan, Yao-Feng Chang, A. Chaudhari, Albert B. Chen, N. Das, C. English, Pulkit Jain, H. Kothari, Blake C. Lin, James S. Clarke, Christopher F. Connor, Tahir Ghani, F. Hamzaoglu, P. Hentges, Christopher J. Jezewski, I. Karpov, Roza Kotlyar, M. Metz, J. O'Donnell, G. OuelletteDaniel, Joodong Park, A. Pirkle, Pedro A. Quintero, D. Seghete, M. Sekhar, A. Gupta, M. Seth, Strutt Nathan, C. Wiegand, Y. H. Jae, Kevin J. Fischer
This paper presents key specifications of RRAM-based nonvolatile memory embedded into Intel 22FFL FinFET Technology. 22FFL is a high performance, ultra low power technology developed for mobile and RF applications providing extensive high voltage and analog support and high design flexibility combined with low manufacturing costs [1]. Embedded RRAM technology presented in this paper achieves 104 cycle endurance combined with 85°C 10-year retention and high die yield. Technology data retention, endurance and yield are demonstrated on 7.2Mbit arrays. We describe device characteristics, bit cell integration into the logic flow, as well as key considerations for achieving high endurance and retention properties.
{"title":"Non-Volatile RRAM Embedded into 22FFL FinFET Technology","authors":"O. Golonzka, U. Arslan, P. Bai, M. Bohr, O. Baykan, Yao-Feng Chang, A. Chaudhari, Albert B. Chen, N. Das, C. English, Pulkit Jain, H. Kothari, Blake C. Lin, James S. Clarke, Christopher F. Connor, Tahir Ghani, F. Hamzaoglu, P. Hentges, Christopher J. Jezewski, I. Karpov, Roza Kotlyar, M. Metz, J. O'Donnell, G. OuelletteDaniel, Joodong Park, A. Pirkle, Pedro A. Quintero, D. Seghete, M. Sekhar, A. Gupta, M. Seth, Strutt Nathan, C. Wiegand, Y. H. Jae, Kevin J. Fischer","doi":"10.23919/VLSIT.2019.8776570","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776570","url":null,"abstract":"This paper presents key specifications of RRAM-based nonvolatile memory embedded into Intel 22FFL FinFET Technology. 22FFL is a high performance, ultra low power technology developed for mobile and RF applications providing extensive high voltage and analog support and high design flexibility combined with low manufacturing costs [1]. Embedded RRAM technology presented in this paper achieves 104 cycle endurance combined with 85°C 10-year retention and high die yield. Technology data retention, endurance and yield are demonstrated on 7.2Mbit arrays. We describe device characteristics, bit cell integration into the logic flow, as well as key considerations for achieving high endurance and retention properties.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"42 2 1","pages":"T230-T231"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89578290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776510
F. Khan, D. Moy, D. Anand, E. Schroeder, R. Katz, L. Jiang, E. Banghart, N. Robson, T. Kirihata
Described is a secure, multi-time programmable memory (MTPM) solution for the 14 nm FINFET node and beyond, which turns as-fabricated standard logic transistors into embedded non-volatile memory (eNVM) elements, without the need for any process adders or additional masks. These logic transistors, when employed as eNVM elements, are dubbed “Charge Trap Transistors” (CTTs). Outlined are the technological breakthroughs required for employing logic transistors as an MTPM. An erase technique, called “Self-heating Temperature Assisted eRase” (STAR), is introduced which enables 100% erase efficiency, as compared to $< 50%$ erase efficiency using conventional methods, in turn enabling MTPM functionality in CTTs. For the first time, hardware results demonstrate an endurance of $> 10^{4}$ program/erase cycles. Data retention lifetime of $> 10$ years at 125°C and scalability to 7 nm have been confirmed.
{"title":"Turning Logic Transistors into Secure, Multi-Time Programmable, Embedded Non-Volatile Memory Elements for 14 nm FINFET Technologies and Beyond","authors":"F. Khan, D. Moy, D. Anand, E. Schroeder, R. Katz, L. Jiang, E. Banghart, N. Robson, T. Kirihata","doi":"10.23919/VLSIT.2019.8776510","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776510","url":null,"abstract":"Described is a secure, multi-time programmable memory (MTPM) solution for the 14 nm FINFET node and beyond, which turns as-fabricated standard logic transistors into embedded non-volatile memory (eNVM) elements, without the need for any process adders or additional masks. These logic transistors, when employed as eNVM elements, are dubbed “Charge Trap Transistors” (CTTs). Outlined are the technological breakthroughs required for employing logic transistors as an MTPM. An erase technique, called “Self-heating Temperature Assisted eRase” (STAR), is introduced which enables 100% erase efficiency, as compared to $< 50%$ erase efficiency using conventional methods, in turn enabling MTPM functionality in CTTs. For the first time, hardware results demonstrate an endurance of $> 10^{4}$ program/erase cycles. Data retention lifetime of $> 10$ years at 125°C and scalability to 7 nm have been confirmed.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"22 1","pages":"T116-T117"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90201163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we present an integrated circuit which supports Full-Hd photorealistic refocusing. In contrast to the conventional single-image blurring, it provides physically-correct bokeh effect by rendering and then averaging hundreds of novel views from five images taken in different perspectives. To address the huge requirement of DRAM bandwidth and computing power, we adopt a block-based multi-rate framework and further propose two techniques: four-direction view generation and highly-parallel view rendering. The former provides a compact system architecture to save 32% of SRAM area and 92% of DRAM bandwidth without noticeable quality degradation. The latter efficiently generates 5.4G novel pixels per second to provide high-quality refocusing. This chip is fabricated in 40nm CMOS process, and the core area is 3.61 mm2. It consumes 250mW when operating at 200MHz and 0.9V to support Full-HD photorealistic refocusing up to 40 fps.
{"title":"A 250mW 5.4G-Novel-Pixel/s Photorealistic Refocusing Processor for Full-HD Five-Camera Applications","authors":"Po-Han Chen, Shu-Wen Yang, Shih-Yao Huang, Li-De Chen, Chao-Tsung Huang","doi":"10.23919/VLSIT.2019.8776561","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776561","url":null,"abstract":"In this paper, we present an integrated circuit which supports Full-Hd photorealistic refocusing. In contrast to the conventional single-image blurring, it provides physically-correct bokeh effect by rendering and then averaging hundreds of novel views from five images taken in different perspectives. To address the huge requirement of DRAM bandwidth and computing power, we adopt a block-based multi-rate framework and further propose two techniques: four-direction view generation and highly-parallel view rendering. The former provides a compact system architecture to save 32% of SRAM area and 92% of DRAM bandwidth without noticeable quality degradation. The latter efficiently generates 5.4G novel pixels per second to provide high-quality refocusing. This chip is fabricated in 40nm CMOS process, and the core area is 3.61 mm2. It consumes 250mW when operating at 200MHz and 0.9V to support Full-HD photorealistic refocusing up to 40 fps.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"42 1","pages":"C154-C155"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86077610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776490
A. Vandooren, Z. Wu, A. Khaled, J. Franco, B. Parvais, W. Li, L. Witters, A. Walke, L. Peng, N. Rassoul, P. Matagne, H. Debruyn, G. Jamieson, F. Inoue, K. Devriendt, L. Teugels, N. Heylen, E. Vecchio, T. Zheng, D. Radisic, E. Rosseel, W. Vanherle, A. Hikavyy, B. Chan, G. Besnard, W. Schwarzenbach, G. Gaudin, I. Radu, B. Nguyen, N. Waldron, V. De Heyn, S. Demuynck, J. Boemmels, J. Ryckaert, N. Collaert, D. Mocuta
3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic Vthtuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ~103mV/V and ~139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the $I_{ON}$ performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.
{"title":"Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications","authors":"A. Vandooren, Z. Wu, A. Khaled, J. Franco, B. Parvais, W. Li, L. Witters, A. Walke, L. Peng, N. Rassoul, P. Matagne, H. Debruyn, G. Jamieson, F. Inoue, K. Devriendt, L. Teugels, N. Heylen, E. Vecchio, T. Zheng, D. Radisic, E. Rosseel, W. Vanherle, A. Hikavyy, B. Chan, G. Besnard, W. Schwarzenbach, G. Gaudin, I. Radu, B. Nguyen, N. Waldron, V. De Heyn, S. Demuynck, J. Boemmels, J. Ryckaert, N. Collaert, D. Mocuta","doi":"10.23919/VLSIT.2019.8776490","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776490","url":null,"abstract":"3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic Vthtuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ~103mV/V and ~139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the $I_{ON}$ performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"14 1","pages":"T56-T57"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87920267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/vlsit.2019.8776528
{"title":"Joint Evening Panel Discussion The Semiconductor Industry at a Tipping Point: What's Next?","authors":"","doi":"10.23919/vlsit.2019.8776528","DOIUrl":"https://doi.org/10.23919/vlsit.2019.8776528","url":null,"abstract":"","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"17 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80796770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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