Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776502
P. Zuliani, A. Conte, P. Cappelletti
A comparative analysis of different Resistive Memories proposed as Non Volatile Memories for embedded applications is here presented. Based on today scenario of industry-standard Floating Gate solutions, key factors as performances, reliability and technology maturity are considered when facing more innovative memory cells. In particular the race seems to be open at 28nm, where different players are proposing different memories integrated in the Back End Of the Line. Original results obtained on multi-megabits array integrating Phase Change Memories are here discussed covering cell scalability, High Temperature data retention and extended endurance capability, all in line with eNVM application requirements.
{"title":"The PCM way for embedded Non Volatile Memories applications","authors":"P. Zuliani, A. Conte, P. Cappelletti","doi":"10.23919/VLSIT.2019.8776502","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776502","url":null,"abstract":"A comparative analysis of different Resistive Memories proposed as Non Volatile Memories for embedded applications is here presented. Based on today scenario of industry-standard Floating Gate solutions, key factors as performances, reliability and technology maturity are considered when facing more innovative memory cells. In particular the race seems to be open at 28nm, where different players are proposing different memories integrated in the Back End Of the Line. Original results obtained on multi-megabits array integrating Phase Change Memories are here discussed covering cell scalability, High Temperature data retention and extended endurance capability, all in line with eNVM application requirements.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"1 1","pages":"T192-T193"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89713354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776578
Xiaowei Cai, A. Vardi, J. Grajal, J. D. del Alamo
We study the performance degradation of InGaAs FinFETs as they scale to sub-10 nm fin width. This is often attributed to degradation in intrinsic transport parameters. High frequency measurements, however, indicate increasingly severe oxide trapping as the fin width narrows. This is confirmed by pulsed-IV measurements. A new mobility extraction method using concurrent S-parameter and DC-IV measurements avoids the impact of oxide trapping and reveals promising mobility in thin-channel InGaAs planar MOSFETs and narrow-width FinFETs. Our study suggests that performance degradation of InGaAs FinFETs is largely an extrinsic phenomenon that can be engineered around and that the potential performance of deeply-scaled InGaAs FinFETs is significantly underestimated.
{"title":"Reassessing InGaAs for Logic: Mobility Extraction in sub-10nm Fin-Width FinFETs","authors":"Xiaowei Cai, A. Vardi, J. Grajal, J. D. del Alamo","doi":"10.23919/VLSIT.2019.8776578","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776578","url":null,"abstract":"We study the performance degradation of InGaAs FinFETs as they scale to sub-10 nm fin width. This is often attributed to degradation in intrinsic transport parameters. High frequency measurements, however, indicate increasingly severe oxide trapping as the fin width narrows. This is confirmed by pulsed-IV measurements. A new mobility extraction method using concurrent S-parameter and DC-IV measurements avoids the impact of oxide trapping and reveals promising mobility in thin-channel InGaAs planar MOSFETs and narrow-width FinFETs. Our study suggests that performance degradation of InGaAs FinFETs is largely an extrinsic phenomenon that can be engineered around and that the potential performance of deeply-scaled InGaAs FinFETs is significantly underestimated.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"25 1","pages":"T246-T247"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91286472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776477
Zuoguang Liu, Heng Wu, Chen Zhang, Xin He Miao, Huimei Zhou, R. Southwick, T. Yamashita, D. Guo
More-Moore logic device technology roadmap suggests Lateral/Vertical Gate-All-Around (LGAA /VGAA) device architectures beyond FinFETs for further scaling and performance. At extremely scaled gate pitches, parasitic resistance significant impacts the performance of the devices. Direct partition measurement of the resistance components in FinFETs has been established. Stacked LGAA devices at further scaled gate pitches exhibit high S/D series resistance and contact resistance which can be partitioned with similar Kelvin measurement. VGAA transistors have a very different structure from FinFETs or LGAAs. Their asymmetric bottom and top S/D results in significant spreading resistance and different contact resistance values. Separate partition of the resistances at the bottom and top is needed. In this paper, VGAA test structures and measurement methodology is introduced for partitioning the resistance components.
{"title":"Direct Partition Measurement of Parasitic Resistance Components in Advanced Transistor Architectures","authors":"Zuoguang Liu, Heng Wu, Chen Zhang, Xin He Miao, Huimei Zhou, R. Southwick, T. Yamashita, D. Guo","doi":"10.23919/VLSIT.2019.8776477","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776477","url":null,"abstract":"More-Moore logic device technology roadmap suggests Lateral/Vertical Gate-All-Around (LGAA /VGAA) device architectures beyond FinFETs for further scaling and performance. At extremely scaled gate pitches, parasitic resistance significant impacts the performance of the devices. Direct partition measurement of the resistance components in FinFETs has been established. Stacked LGAA devices at further scaled gate pitches exhibit high S/D series resistance and contact resistance which can be partitioned with similar Kelvin measurement. VGAA transistors have a very different structure from FinFETs or LGAAs. Their asymmetric bottom and top S/D results in significant spreading resistance and different contact resistance values. Separate partition of the resistances at the bottom and top is needed. In this paper, VGAA test structures and measurement methodology is introduced for partitioning the resistance components.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"172 1","pages":"T146-T147"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84502515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776523
T.-E. Lee, K. Kato, M. Ke, M. Takenaka, S. Takagi
We demonstrate the low interface trap density at SiGe p-MOS interfaces with TiN/Y2O3gate stacks by employing the Trimethylaluminum (TMA) passivation. PMA temperature is optimized to maximize scavenging of GeOx. The impact of the gate electrode among TiN, Al, Au and W is studied for Y2O3/SiGe interfaces. The TiN/Y2O3/ SiGe interfaces with PMA at 450°C minimize interface trap density $(text{D}_{text{it}})$, hysteresis and gate leakage current. TMA passivation is found to further improve the interfacial pronerties. The record-low minimum $text{D}_{text{it}}$ of $2.7text{x}10^{10} 5.4{text{x}}10^{10},1.7text{x}10^{11},2.0text{x}10^{11},7.4text{x}10^{11}$ and $4.2text{x}10^{12}text{eV}^{-1}text{cm}^{-2}$ are obtained for SiGe MOS interfaces with the Ge contents of 0.13, 0.22, 0.32, 0.38, 0.49, and 0.62, respectively.
{"title":"Improvement of SiGe MOS interface properties with a wide range of Ge contents by using TiN/Y2O3 gate stacks with TMA nassivation","authors":"T.-E. Lee, K. Kato, M. Ke, M. Takenaka, S. Takagi","doi":"10.23919/VLSIT.2019.8776523","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776523","url":null,"abstract":"We demonstrate the low interface trap density at SiGe p-MOS interfaces with TiN/Y<inf>2</inf>O<inf>3</inf>gate stacks by employing the Trimethylaluminum (TMA) passivation. PMA temperature is optimized to maximize scavenging of GeO<inf>x</inf>. The impact of the gate electrode among TiN, Al, Au and W is studied for Y<inf>2</inf>O<inf>3</inf>/SiGe interfaces. The TiN/Y<inf>2</inf>O<inf>3</inf>/ SiGe interfaces with PMA at 450°C minimize interface trap density <tex>$(text{D}_{text{it}})$</tex>, hysteresis and gate leakage current. TMA passivation is found to further improve the interfacial pronerties. The record-low minimum <tex>$text{D}_{text{it}}$</tex> of <tex>$2.7text{x}10^{10} 5.4{text{x}}10^{10},1.7text{x}10^{11},2.0text{x}10^{11},7.4text{x}10^{11}$</tex> and <tex>$4.2text{x}10^{12}text{eV}^{-1}text{cm}^{-2}$</tex> are obtained for SiGe MOS interfaces with the Ge contents of 0.13, 0.22, 0.32, 0.38, 0.49, and 0.62, respectively.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"27 1","pages":"T100-T101"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82940575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776581
Fang-Liang Lu, Chung-En Tsai, Chih-Hsiung Huang, Hung-Yu Ye, Shih-Ya Lin, C. W. Liu
The record low contact resistivity $(rho_{text{c}})$ of $4.4text{x}10^{-10}Omega-text{cm}^{2}$ is achieved in Ti metal contact to in-situ B-doped $text{GeSn}$ using B $(> 1text{x}10^{21}text{cm}^{-3})$ and Sn $(> 12%)$ segregations at the Ti/GeSn:B interface. Sn incorporation into Ge lowers the Schottky barrier height of holes. Increasing B doping at the $text{Ti}/text{GeSn}:text{B}$ interface reduces the hole tunneling distance. Thanks to the low growth temperature (305°C) of the chemical vapor deposition using Ge2H6, the GeSn:B with the bulk active [B] of $2.1text{x}10^{20}text{cm}^{-3} (>> > text{the}$ solid solubility of B in $text{Ge}=5.5text{x}10^{18}text{cm}^{-3}$) and the bulk [Sn] of 4.9% is successfully grown. Without the needs of the previously reported Ga dopants and the high temperature annealing for dopant activation, the record low $rho_{text{c}}$ is achieved with all the process temperatures $leq 400^{text{o}}text{C}$.
利用B $(> 1text{x}10^{21}text{cm}^{-3})$和Sn $(> 12%)$在Ti/GeSn:B界面上的分离，在Ti金属与原位B掺杂$text{GeSn}$的接触中，获得了创纪录的低接触电阻$(rho_{text{c}})$$4.4text{x}10^{-10}Omega-text{cm}^{2}$。Sn与Ge的掺入降低了空穴的肖特基势垒高度。在$text{Ti}/text{GeSn}:text{B}$界面处增加B掺杂可以减小空穴隧穿距离。由于采用Ge2H6化学气相沉积的生长温度较低(305℃)，制备的GeSn:B的体积活性[B]为$2.1text{x}10^{20}text{cm}^{-3} (>> > text{the}$, B在$text{Ge}=5.5text{x}10^{18}text{cm}^{-3}$中的固溶度为4.9% is successfully grown. Without the needs of the previously reported Ga dopants and the high temperature annealing for dopant activation, the record low $rho_{text{c}}$ is achieved with all the process temperatures $leq 400^{text{o}}text{C}$.
{"title":"Record Low Contact Resistivity (4.4×10−10 Ω-cm2) to Ge Using In-situ B and Sn Incorporation by CVD With Low Thermal Budget (≤400°C) and Without Ga","authors":"Fang-Liang Lu, Chung-En Tsai, Chih-Hsiung Huang, Hung-Yu Ye, Shih-Ya Lin, C. W. Liu","doi":"10.23919/VLSIT.2019.8776581","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776581","url":null,"abstract":"The record low contact resistivity $(rho_{text{c}})$ of $4.4text{x}10^{-10}Omega-text{cm}^{2}$ is achieved in Ti metal contact to in-situ B-doped $text{GeSn}$ using B $(> 1text{x}10^{21}text{cm}^{-3})$ and Sn $(> 12%)$ segregations at the Ti/GeSn:B interface. Sn incorporation into Ge lowers the Schottky barrier height of holes. Increasing B doping at the $text{Ti}/text{GeSn}:text{B}$ interface reduces the hole tunneling distance. Thanks to the low growth temperature (305°C) of the chemical vapor deposition using Ge2H6, the GeSn:B with the bulk active [B] of $2.1text{x}10^{20}text{cm}^{-3} (>> > text{the}$ solid solubility of B in $text{Ge}=5.5text{x}10^{18}text{cm}^{-3}$) and the bulk [Sn] of 4.9% is successfully grown. Without the needs of the previously reported Ga dopants and the high temperature annealing for dopant activation, the record low $rho_{text{c}}$ is achieved with all the process temperatures $leq 400^{text{o}}text{C}$.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"197 1","pages":"T178-T179"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76957161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776493
A. Greene, Huimei Zhou, R. Xie, Chanro Park, L. Economikos, V. Chan, K. Akarvardar, R. Bao, I. Seshadri, R. Conti, Miaomiao Wang, M. Sankarapandian, J. Demarest, Juntao Li, Liying Jiang, K. Zhao, R. Robison, T. Ando, N. Cave, A. Knorr, D. Gupta, S. Kanakasabapathy, D. Guo, B. Haran, V. Basker, H. Bu
In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.
{"title":"Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction","authors":"A. Greene, Huimei Zhou, R. Xie, Chanro Park, L. Economikos, V. Chan, K. Akarvardar, R. Bao, I. Seshadri, R. Conti, Miaomiao Wang, M. Sankarapandian, J. Demarest, Juntao Li, Liying Jiang, K. Zhao, R. Robison, T. Ando, N. Cave, A. Knorr, D. Gupta, S. Kanakasabapathy, D. Guo, B. Haran, V. Basker, H. Bu","doi":"10.23919/VLSIT.2019.8776493","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776493","url":null,"abstract":"In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"41 1","pages":"T144-T145"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80838017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776484
William Chen, B. Bottoms
Our industry has reinvented itself through multiple disruptive changes in market, products, and technology. We are at the triple inflection point, brought about by tech company disruption, Moore's Law plateauing, and the explosive growth of the digital economy. Continued progress will require a new vision for electronic innovations. This paper shows examples of Heterogeneous Integration (SiP) for two market segments, Smart Phone and HPC Server and describes the purpose and organization of the Heterogeneous Integration Roadmap.
{"title":"Heterogeneous Integration Roadmap: Driving Force and Enabling Technology for Systems of the Future","authors":"William Chen, B. Bottoms","doi":"10.23919/VLSIT.2019.8776484","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776484","url":null,"abstract":"Our industry has reinvented itself through multiple disruptive changes in market, products, and technology. We are at the triple inflection point, brought about by tech company disruption, Moore's Law plateauing, and the explosive growth of the digital economy. Continued progress will require a new vision for electronic innovations. This paper shows examples of Heterogeneous Integration (SiP) for two market segments, Smart Phone and HPC Server and describes the purpose and organization of the Heterogeneous Integration Roadmap.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"94 1","pages":"T50-T51"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83182361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776531
Soyoun Kim, S.K. Kim, J. kim, B.H. Choi, B. Park, Y. Yasuda-Masuoka, S. Kwon
An advanced FinFET design is identified to improve both variation and minimum operation voltage $(V_{text{min}})$ in various temperature and supply voltage $(V_{text{dd}})$ ranges, using sub-10 nm FinFET transistors. Through a clarification of each electrical parameter's impact on both variation and operation voltage, a suitable FinFET design is successfully demonstrated to reduce $I_{text{eff}}$ variation by 0.4x, as well as Idoff variation by 0.8x in various $V_{text{dd}}$ ranges. This paper also provides Tr. design to improve $V_{text{min}}$ by 35 mV with the switching energy 0.87x reduction.
{"title":"Sub-If nm Advanced FinFET Design for Different Applications in Various Vdd and Temperature Operation Ranges","authors":"Soyoun Kim, S.K. Kim, J. kim, B.H. Choi, B. Park, Y. Yasuda-Masuoka, S. Kwon","doi":"10.23919/VLSIT.2019.8776531","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776531","url":null,"abstract":"An advanced FinFET design is identified to improve both variation and minimum operation voltage $(V_{text{min}})$ in various temperature and supply voltage $(V_{text{dd}})$ ranges, using sub-10 nm FinFET transistors. Through a clarification of each electrical parameter's impact on both variation and operation voltage, a suitable FinFET design is successfully demonstrated to reduce $I_{text{eff}}$ variation by 0.4x, as well as Idoff variation by 0.8x in various $V_{text{dd}}$ ranges. This paper also provides Tr. design to improve $V_{text{min}}$ by 35 mV with the switching energy 0.87x reduction.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"38 1","pages":"T108-T109"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74676056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776509
T. Choi, H. Choi, J.H. Choi, H. Choo, H. Jung, H.Y. Kim, T. Song, J. Kye, S. Jung
High-sigma yield simulation analysis based on accurate SPICE mismatch model is required for high volume product design. Especially for the low power design in sub-7nm technology, the non-Gaussian behavior of the transistor drain currents $(I_{text{ds}})$ is intensifying due to large mismatch variation. To achieve reliable high-sigma simulation, SPICE mismatch model needs to accurately reflect the non-Gaussian $I_{text{ds}}$ distribution obtained from the silicon data. Gaussian distribution modeling of channel resistance factor $(R_{text{ch}_{-}text{f}})$ and source/drain external resistance $(R_{text{ext}})$ is proven to be effective to model the skewed Gaussian distribution shape of massive silicon Ids data.
{"title":"Accurate High-Sigma Mismatch Model for Low Power Design in Sub-7nm Technology","authors":"T. Choi, H. Choi, J.H. Choi, H. Choo, H. Jung, H.Y. Kim, T. Song, J. Kye, S. Jung","doi":"10.23919/VLSIT.2019.8776509","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776509","url":null,"abstract":"High-sigma yield simulation analysis based on accurate SPICE mismatch model is required for high volume product design. Especially for the low power design in sub-7nm technology, the non-Gaussian behavior of the transistor drain currents $(I_{text{ds}})$ is intensifying due to large mismatch variation. To achieve reliable high-sigma simulation, SPICE mismatch model needs to accurately reflect the non-Gaussian $I_{text{ds}}$ distribution obtained from the silicon data. Gaussian distribution modeling of channel resistance factor $(R_{text{ch}_{-}text{f}})$ and source/drain external resistance $(R_{text{ext}})$ is proven to be effective to model the skewed Gaussian distribution shape of massive silicon Ids data.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"9 1","pages":"T106-T107"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87637348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776494
Ying Wu, Haiwen Xu, L. Chua, Kaizhen Han, W. Zou, T. Henry, Jishen Zhang, Chengkuan Wang, Chen Sun, X. Gong
A novel ladder transmission line method (LTLM) that features eliminated parasitic resistance from contact metal and access electrodes, simple fabrication process, and $2times 10^{-10}Omega-text{cm}^{2}$ resolution for highly-accurate extraction of specific contact resistivity $(rho_{c})$ in the $sim 10^{-10}$ to 10−9$Omega-text{cm}^{2}$ regime is demonstrated. The current distribution and extraction of $rho_{c}text{ln}$ LTLM are verified by TCAD and numerical distributive-resistor-network method, respectively. The extraction error caused by the current spreading and crowding in LTLM are modeled, and design guidelines to achieve 10−10$Omega-text{cm}^{2}$ resolution for $rho_{c}$ extraction are provided. By applying LTLM to the Ni/p+-Ge0.95Sn0.05 contact, a record-low $rho_{c}$ down to $4.0pm 2.0times 10^{-10}Omega-text{cm}^{2}$ was obtained. LTLM is insensitive to variation of metal resistance, unlike the refined TLM (RTLM) which could overestimate $rho_{c}$ by at least tens of times.
{"title":"A Novel Fast-Turn-Around Ladder TLM Methodology with Parasitic Metal Resistance Elimination, and 2×10−10 Ω-cm2Resolution: Theoretical Design and Experimental Demonstration","authors":"Ying Wu, Haiwen Xu, L. Chua, Kaizhen Han, W. Zou, T. Henry, Jishen Zhang, Chengkuan Wang, Chen Sun, X. Gong","doi":"10.23919/VLSIT.2019.8776494","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776494","url":null,"abstract":"A novel ladder transmission line method (LTLM) that features eliminated parasitic resistance from contact metal and access electrodes, simple fabrication process, and <tex>$2times 10^{-10}Omega-text{cm}^{2}$</tex> resolution for highly-accurate extraction of specific contact resistivity <tex>$(rho_{c})$</tex> in the <tex>$sim 10^{-10}$</tex> to 10<sup>−9</sup><tex>$Omega-text{cm}^{2}$</tex> regime is demonstrated. The current distribution and extraction of <tex>$rho_{c}text{ln}$</tex> LTLM are verified by TCAD and numerical distributive-resistor-network method, respectively. The extraction error caused by the current spreading and crowding in LTLM are modeled, and design guidelines to achieve 10<sup>−10</sup><tex>$Omega-text{cm}^{2}$</tex> resolution for <tex>$rho_{c}$</tex> extraction are provided. By applying LTLM to the Ni/p<sup>+</sup>-Ge<inf>0.95</inf>Sn<inf>0.05</inf> contact, a record-low <tex>$rho_{c}$</tex> down to <tex>$4.0pm 2.0times 10^{-10}Omega-text{cm}^{2}$</tex> was obtained. LTLM is insensitive to variation of metal resistance, unlike the refined TLM (RTLM) which could overestimate <tex>$rho_{c}$</tex> by at least tens of times.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"2 1","pages":"T150-T151"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89278539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：