Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776568
S. Fujii, R. Ichihara, T. Konno, M. Yamaguchi, Harumi Seki, Hiroki Tanaka, Dandan Zhao, Y. Yoshimura, M. Saitoh, M. Koyama
We demonstrated a cross-point memory array composed of 40nm Ag ionic memory cell with $text{sub}-mu text{A}$ and selectorless operation and 10-year data retention, making it a promising candidate for terabit-scale high-density memory application. Discontinuous conductive path with large and dense Ag clusters enabled 10-year retention even at sub-μA current with keeping high non-linearity in I-V. We implemented, for the first time, the improved cell into a 40nm cross-point array and demonstrated narrow read distribution which satisfies requirements for reliable array operation.
{"title":"Ag Ionic Memory Cell Technology for Terabit-Scale High-Density Application","authors":"S. Fujii, R. Ichihara, T. Konno, M. Yamaguchi, Harumi Seki, Hiroki Tanaka, Dandan Zhao, Y. Yoshimura, M. Saitoh, M. Koyama","doi":"10.23919/VLSIT.2019.8776568","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776568","url":null,"abstract":"We demonstrated a cross-point memory array composed of 40nm Ag ionic memory cell with $text{sub}-mu text{A}$ and selectorless operation and 10-year data retention, making it a promising candidate for terabit-scale high-density memory application. Discontinuous conductive path with large and dense Ag clusters enabled 10-year retention even at sub-μA current with keeping high non-linearity in I-V. We implemented, for the first time, the improved cell into a 40nm cross-point array and demonstrated narrow read distribution which satisfies requirements for reliable array operation.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"15 1","pages":"T188-T189"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80033637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776517
T. Wen, B. Colombeau, C.l. Li, S. Liu, B. Guo, H. Meer, M. Hou, B. Yang, H.C. Feng, C. Hsu, C.C. Huang, Y. Tasi, H.P. Chen, S. Huang, C.W. Huang, C. Chen, J. Lin, K. Shim, J. Kuo, S. Lee, L. Holcman, K. Nafisr, J. Fernandez, D. Fung, N. H. Yang, J.Y. Wu, G. Hung
In advanced FinFET devices, STI gap fill and $vert text{LD}_{0}$ stress are responsible for fin defects, fin bending as well as device performance degradations due to the local layout effect (LLE). In this paper, for the first time, we look at different ways to modulate the stress from the Flowable CVD (FCVD) films either by additional UV treatment and/or ion beam treatment (hot Helium implantation). By leveraging in-line e-beam metrology capabilities of PROVision™ for massive measurements of critical dimensions (CDs), the process impact on fin spacing and LLEs are characterized and analyzed. Significant improvement for LLE is observed for nFET device which correlates to fin bending improvement. In addition, ~5% drive current gain for pFET is observed after $text{ILD}_{0}$ stress optimization.
{"title":"Fin Bending Mitigation and Local Layout Effect Alleviation in Advanced FinFET Technology through Material Engineering and Metrology Optimization","authors":"T. Wen, B. Colombeau, C.l. Li, S. Liu, B. Guo, H. Meer, M. Hou, B. Yang, H.C. Feng, C. Hsu, C.C. Huang, Y. Tasi, H.P. Chen, S. Huang, C.W. Huang, C. Chen, J. Lin, K. Shim, J. Kuo, S. Lee, L. Holcman, K. Nafisr, J. Fernandez, D. Fung, N. H. Yang, J.Y. Wu, G. Hung","doi":"10.23919/VLSIT.2019.8776517","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776517","url":null,"abstract":"In advanced FinFET devices, STI gap fill and $vert text{LD}_{0}$ stress are responsible for fin defects, fin bending as well as device performance degradations due to the local layout effect (LLE). In this paper, for the first time, we look at different ways to modulate the stress from the Flowable CVD (FCVD) films either by additional UV treatment and/or ion beam treatment (hot Helium implantation). By leveraging in-line e-beam metrology capabilities of PROVision™ for massive measurements of critical dimensions (CDs), the process impact on fin spacing and LLEs are characterized and analyzed. Significant improvement for LLE is observed for nFET device which correlates to fin bending improvement. In addition, ~5% drive current gain for pFET is observed after $text{ILD}_{0}$ stress optimization.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"33 1","pages":"T110-T111"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74110014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776571
R. Degraeve, J. Doevenspeck, A. Fantini, P. Debacker, D. Linten, D. Verkest
The way a person walks, i.e. his/her gait, can be as unique as a fingerprint. With portable accelerometers and/or gyroscopes available in present-day smartphones, gait verification and identification can be exploited for low-level security [1]. Achieving this requires machine learning of a time sequence.
{"title":"Gait identification using stochastic OXRRAM-based time sequence machine learning","authors":"R. Degraeve, J. Doevenspeck, A. Fantini, P. Debacker, D. Linten, D. Verkest","doi":"10.23919/VLSIT.2019.8776571","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776571","url":null,"abstract":"The way a person walks, i.e. his/her gait, can be as unique as a fingerprint. With portable accelerometers and/or gyroscopes available in present-day smartphones, gait verification and identification can be exploited for low-level security [1]. Achieving this requires machine learning of a time sequence.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"10 1","pages":"T84-T85"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87435316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776507
S. Pal, Dong-hyeon Park, Siying Feng, Paul Gao, Jielun Tan, A. Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Tim Wesley, Jonathan Beaumont, Kuan-Yu Chen, C. Chakrabarti, M. Taylor, T. Mudge, D. Blaauw, Hun-Seok Kim, R. Dreslinski
A Sparse Matrix-Matrix multiplication (SpMM) accelerator with 48 heterogeneous cores and a reconfigurable memory hierarchy is fabricated in 40 nm CMOS. On-chip memories are reconfigured as scratchpad or cache and interconnected with synthesizable coalescing crossbars for efficient memory access in each phase of the algorithm. The $2.0 text{mm}times 2.6 text{mm}$ chip exhibits $12.6times(8.4times)$ energy efficiency gain, $11.7times(77.6times)$ off-chip bandwidth efficiency gain and $17.1times(36.9times)$ compute density gain against a high-end CPU (GPU) across a diverse set of synthetic and real-world power-law graph based sparse matrices.
{"title":"A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm","authors":"S. Pal, Dong-hyeon Park, Siying Feng, Paul Gao, Jielun Tan, A. Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Tim Wesley, Jonathan Beaumont, Kuan-Yu Chen, C. Chakrabarti, M. Taylor, T. Mudge, D. Blaauw, Hun-Seok Kim, R. Dreslinski","doi":"10.23919/VLSIT.2019.8776507","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776507","url":null,"abstract":"A Sparse Matrix-Matrix multiplication (SpMM) accelerator with 48 heterogeneous cores and a reconfigurable memory hierarchy is fabricated in 40 nm CMOS. On-chip memories are reconfigured as scratchpad or cache and interconnected with synthesizable coalescing crossbars for efficient memory access in each phase of the algorithm. The $2.0 text{mm}times 2.6 text{mm}$ chip exhibits $12.6times(8.4times)$ energy efficiency gain, $11.7times(77.6times)$ off-chip bandwidth efficiency gain and $17.1times(36.9times)$ compute density gain against a high-end CPU (GPU) across a diverse set of synthetic and real-world power-law graph based sparse matrices.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"166 9 Suppl 1","pages":"C150-C151"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83339714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776559
S. Bianchi, I. Muñoz-Martín, G. Pedretti, O. Melnic, S. Ambrogio, Daniele Ielmini
Artificial neural networks (ANNs) can outperform the human ability of object recognition by supervised training of synaptic parameters with large datasets. Contrarily to the human brain, however, ANNs cannot continually learn, i.e. acquire new information without catastrophically forgetting previous knowledge. To solve this issue, we present a novel hybrid neural network based on CMOS logic and phase change memory (PCM) synapses, mixing a supervised convolutional neural network (CNN) with bio-inspired unsupervised learning and neuronal redundancy. We demonstrate high classification accuracy in MNIST and CIFAR10 datasets (98% and 85%, respectively) and energy-efficient continual learning of up to 30% of non-trained classes with 83% average accuracy.
{"title":"Energy-efficient continual learning in hybrid supervised-unsupervised neural networks with PCM synapses","authors":"S. Bianchi, I. Muñoz-Martín, G. Pedretti, O. Melnic, S. Ambrogio, Daniele Ielmini","doi":"10.23919/VLSIT.2019.8776559","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776559","url":null,"abstract":"Artificial neural networks (ANNs) can outperform the human ability of object recognition by supervised training of synaptic parameters with large datasets. Contrarily to the human brain, however, ANNs cannot continually learn, i.e. acquire new information without catastrophically forgetting previous knowledge. To solve this issue, we present a novel hybrid neural network based on CMOS logic and phase change memory (PCM) synapses, mixing a supervised convolutional neural network (CNN) with bio-inspired unsupervised learning and neuronal redundancy. We demonstrate high classification accuracy in MNIST and CIFAR10 datasets (98% and 85%, respectively) and energy-efficient continual learning of up to 30% of non-trained classes with 83% average accuracy.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"21 1","pages":"T172-T173"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87107189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776534
S. Dutta, A. Khanna, W. Chakraborty, J. Gomez, S. Joshi, S. Datta
The paradigm of biologically-inspired computing endows the components of a neural network with dynamical functionality, such as self-oscillations, and harnesses emergent physical phenomena like synchronization, to learn and classify complex temporal patterns. In this work, we exploit the synchronization dynamics of a network of ultra-compact, low power Vanadium dioxide (VO2) based insulator-to-metal phase-transition nano-oscillators (IMT-NO) to classify complex temporal pattern for speech discrimination. We successfully train a network of four capacitively coupled IMT-NOs to recognize spoken vowels by tuning their oscillation frequencies electrically according to a real-time learning rule and achieve high recognition rates of 90.5% for spoken vowels. Such an energy-efficient compact hardware with a small number of functional elements are a promising technology option for edge artificial intelligence.
{"title":"Spoken vowel classification using synchronization of phase transition nano-oscillators","authors":"S. Dutta, A. Khanna, W. Chakraborty, J. Gomez, S. Joshi, S. Datta","doi":"10.23919/VLSIT.2019.8776534","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776534","url":null,"abstract":"The paradigm of biologically-inspired computing endows the components of a neural network with dynamical functionality, such as self-oscillations, and harnesses emergent physical phenomena like synchronization, to learn and classify complex temporal patterns. In this work, we exploit the synchronization dynamics of a network of ultra-compact, low power Vanadium dioxide (VO2) based insulator-to-metal phase-transition nano-oscillators (IMT-NO) to classify complex temporal pattern for speech discrimination. We successfully train a network of four capacitively coupled IMT-NOs to recognize spoken vowels by tuning their oscillation frequencies electrically according to a real-time learning rule and achieve high recognition rates of 90.5% for spoken vowels. Such an energy-efficient compact hardware with a small number of functional elements are a promising technology option for edge artificial intelligence.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"44 4","pages":"T128-T129"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72576563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/vlsit.2019.8776575
{"title":"Technology Evening Panel Discussion What Will the Foundries of the Future Do?","authors":"","doi":"10.23919/vlsit.2019.8776575","DOIUrl":"https://doi.org/10.23919/vlsit.2019.8776575","url":null,"abstract":"","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"52 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77604068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776547
W. Gallagher, Eric Chien, Chiang Tien-Wei, Jian-Cheng Huang, Meng-Chun Shih, Wang Chia-Yu, C. Bair, George Lee, Y. Shih, Lee Chia-Fu, Roger Wang, K. Shen, J. J. Wu, Wayne Wang, H. Chuang
MRAM can play a variety of on-chip memory roles in advanced VLSI technology spanning from high retention, solder-reflow-capable non-volatile memory (NVM) to dense non-volatile or high retention working RAMs. This paper describes results for a solder-reflow-capable MRAM NVM and for extensions that trade off high retention against speed, power, and density.
{"title":"Recent Progress and Next Directions for Embedded MRAM Technology","authors":"W. Gallagher, Eric Chien, Chiang Tien-Wei, Jian-Cheng Huang, Meng-Chun Shih, Wang Chia-Yu, C. Bair, George Lee, Y. Shih, Lee Chia-Fu, Roger Wang, K. Shen, J. J. Wu, Wayne Wang, H. Chuang","doi":"10.23919/VLSIT.2019.8776547","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776547","url":null,"abstract":"MRAM can play a variety of on-chip memory roles in advanced VLSI technology spanning from high retention, solder-reflow-capable non-volatile memory (NVM) to dense non-volatile or high retention working RAMs. This paper describes results for a solder-reflow-capable MRAM NVM and for extensions that trade off high retention against speed, power, and density.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"24 1","pages":"T190-T191"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74309072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-01DOI: 10.23919/VLSIT.2019.8776512
Masato Hayashi, Takashi Takemoto, C. Yoshimura, M. Yamaoka
This paper presents a CMOS annealing processor (CMOS-AP) that accelerates ground state searches of the Ising model. The main feature of this processor is its inter-chip connection interface for making a larger chip. A credit card sized compute node integrating two CMOS-APs was also developed as an interface with existing computer systems. The compute node can handle up to 61,952 spins at a time. A performance evaluation using the node improved the CPU speed by 55 times in solving a minimum vertex cover problem, one of the NP-hard combinatorial optimization problems. Finally, we describe a cloud interface for the compute node to make the CMOS-APs more useful and to promote application development for it.
{"title":"A Cloud-ready Scalable Annealing Processor for Solving Large-scale Combinatorial Optimization Problems","authors":"Masato Hayashi, Takashi Takemoto, C. Yoshimura, M. Yamaoka","doi":"10.23919/VLSIT.2019.8776512","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776512","url":null,"abstract":"This paper presents a CMOS annealing processor (CMOS-AP) that accelerates ground state searches of the Ising model. The main feature of this processor is its inter-chip connection interface for making a larger chip. A credit card sized compute node integrating two CMOS-APs was also developed as an interface with existing computer systems. The compute node can handle up to 61,952 spins at a time. A performance evaluation using the node improved the CPU speed by 55 times in solving a minimum vertex cover problem, one of the NP-hard combinatorial optimization problems. Finally, we describe a cloud interface for the compute node to make the CMOS-APs more useful and to promote application development for it.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"5 1","pages":"C148-C149"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79008475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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