Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776522
Zhihong Liu, Hanlin Xie, K. Lee, C. S. Tan, G. Ng, E. Fitzgerald
GaN-on-Si has revealed its great potential for next-generation power electronics applications, however, there remains a challenge in increasing the breakdown voltage $(BV_{text{off}})$ due to the limit of the GaN epilayer thickness on large size wafers. In this work we propose a GaN-on-Insulator (GNOI)-on-Si structure to address this issue. A 200 mm GNOI-on-Si wafer was prepared through removing the original Si substrate of a GaN-on-Si wafer and bonding onto a fresh SiO2/Si substrate. HEMTs were fabricated with measured $BV_{text{off}}$ much larger than those on GaN-on-Si. Record high $BV text{off}$ up to 2200 V and high figure-of-merit (FOM) $BV_{off^2}/R_{text{on, sp}}$ up to 1.87 GW/cm2 have been achieved in the HEMTs on a 200 mm GNOI-on-Si wafer with a thin GaN epilayer of $3.2 {mu m}$.
{"title":"GaN HEMTs with Breakdown Voltage of 2200 V Realized on a 200 mm GaN-on-Insulator(GNOI)-on-Si Wafer","authors":"Zhihong Liu, Hanlin Xie, K. Lee, C. S. Tan, G. Ng, E. Fitzgerald","doi":"10.23919/VLSIT.2019.8776522","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776522","url":null,"abstract":"GaN-on-Si has revealed its great potential for next-generation power electronics applications, however, there remains a challenge in increasing the breakdown voltage $(BV_{text{off}})$ due to the limit of the GaN epilayer thickness on large size wafers. In this work we propose a GaN-on-Insulator (GNOI)-on-Si structure to address this issue. A 200 mm GNOI-on-Si wafer was prepared through removing the original Si substrate of a GaN-on-Si wafer and bonding onto a fresh SiO2/Si substrate. HEMTs were fabricated with measured $BV_{text{off}}$ much larger than those on GaN-on-Si. Record high $BV text{off}$ up to 2200 V and high figure-of-merit (FOM) $BV_{off^2}/R_{text{on, sp}}$ up to 1.87 GW/cm2 have been achieved in the HEMTs on a 200 mm GNOI-on-Si wafer with a thin GaN epilayer of $3.2 {mu m}$.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"47 1","pages":"T242-T243"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88314157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776506
S. Srinivasa, Yung-Ning Tu, Xin Si, Cheng-Xin Xue, Chun-Ying Lee, F. Hsueh, Chane-Hone Shen, J. Shieh, W. Yeh, A. Ramanathan, M. Ho, J. Sampson, Meng-Fan Chang, V. Narayanan
This paper presents the first monolithic 3D two-layer reconfigurable SRAM macro capable of executing multiple Compute-in-Memory (CiM) tasks as part of data readout. Fabricated using low cost FinFET based 3D+-IC, the SRAM offers concurrent data read from both layers and write from layer 2 with 0.4V $text{V}_{text{dd}min}$ 12.8x improved computation latency is achieved as compared to near memory computation of successive Boolean operations.
{"title":"Monolithic 3D+ -IC based Reconfigurable Compute-in-Memory SRAM Macro","authors":"S. Srinivasa, Yung-Ning Tu, Xin Si, Cheng-Xin Xue, Chun-Ying Lee, F. Hsueh, Chane-Hone Shen, J. Shieh, W. Yeh, A. Ramanathan, M. Ho, J. Sampson, Meng-Fan Chang, V. Narayanan","doi":"10.23919/VLSIT.2019.8776506","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776506","url":null,"abstract":"This paper presents the first monolithic 3D two-layer reconfigurable SRAM macro capable of executing multiple Compute-in-Memory (CiM) tasks as part of data readout. Fabricated using low cost FinFET based 3D+-IC, the SRAM offers concurrent data read from both layers and write from layer 2 with 0.4V $text{V}_{text{dd}min}$ 12.8x improved computation latency is achieved as compared to near memory computation of successive Boolean operations.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"103 1","pages":"T32-T33"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80297739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776487
S. Dutta, A. Saha, P. Panda, W. Chakraborty, J. Gomez, A. Khanna, S. Gupta, K. Roy, S. Datta
Biologically plausible mechanism like homeostasis compliments Hebbian learning to allow unsupervised learning in spiking neural networks [1]. In this work, we propose a novel ferroelectric-based quasi-LIF neuron that induces intrinsic homeostasis. We experimentally characterize and perform phase-field simulations to delineate the non-trivial transient polarization relaxation mechanism associated with multi-domain interaction in poly-crystalline ferroelectric, such as Zr doped $text{HfO}_{2}$, that underlines the Q-LIF behavior. Network level simulations with the Q-LIF neuron model exhibits a 2.3x reduction in firing rate compared to traditional LIF neuron while maintaining iso-accuracy of 84-85% across varying network sizes. Such an energy-efficient hardware for spiking neuron can enable ultra-low power data processing in energy constrained environments suitable for edge-intelligence.
{"title":"Biologically Plausible Ferroelectric Quasi-Leaky Integrate and Fire Neuron","authors":"S. Dutta, A. Saha, P. Panda, W. Chakraborty, J. Gomez, A. Khanna, S. Gupta, K. Roy, S. Datta","doi":"10.23919/VLSIT.2019.8776487","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776487","url":null,"abstract":"Biologically plausible mechanism like homeostasis compliments Hebbian learning to allow unsupervised learning in spiking neural networks [1]. In this work, we propose a novel ferroelectric-based quasi-LIF neuron that induces intrinsic homeostasis. We experimentally characterize and perform phase-field simulations to delineate the non-trivial transient polarization relaxation mechanism associated with multi-domain interaction in poly-crystalline ferroelectric, such as Zr doped $text{HfO}_{2}$, that underlines the Q-LIF behavior. Network level simulations with the Q-LIF neuron model exhibits a 2.3x reduction in firing rate compared to traditional LIF neuron while maintaining iso-accuracy of 84-85% across varying network sizes. Such an energy-efficient hardware for spiking neuron can enable ultra-low power data processing in energy constrained environments suitable for edge-intelligence.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"6 1","pages":"T140-T141"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88010137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776513
P. Schuddinck, O. Zografos, P. Weckx, P. Matagne, S. Sarkar, Y. Sherazi, R. Baert, D. Jang, D. Yakimets, A. Gupta, B. Parvais, J. Ryckaert, D. Verkest, A. Mocuta
The structure of the complementary FET (CFET) with NMOS stacked on top of PMOS, inherently yields standard cells and SRAM cells with 25% smaller layout area, 25% higher pin density and 2x higher routing flexibility than FinFET with same overall active footprint. Moreover, our work, based on advanced modelling, demonstrates that 4 track CFET can match and even outperform 5 track FinFET; without the need to lower S/D contact resistivity down to $5text{e}-10Omega.text{cm}^{2}$ or to elevate the channel stress up to 2GPa. All gains in power-performance-area at circuit-level are maintained at block-level, making 4 track CFET a suitable candidate for N3 & N2 technologies. Keywords: CFET, scaling, S/D engineering, Pi-gate.
{"title":"Device-, Circuit- & Block-level evaluation of CFET in a 4 track library","authors":"P. Schuddinck, O. Zografos, P. Weckx, P. Matagne, S. Sarkar, Y. Sherazi, R. Baert, D. Jang, D. Yakimets, A. Gupta, B. Parvais, J. Ryckaert, D. Verkest, A. Mocuta","doi":"10.23919/VLSIT.2019.8776513","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776513","url":null,"abstract":"The structure of the complementary FET (CFET) with NMOS stacked on top of PMOS, inherently yields standard cells and SRAM cells with 25% smaller layout area, 25% higher pin density and 2x higher routing flexibility than FinFET with same overall active footprint. Moreover, our work, based on advanced modelling, demonstrates that 4 track CFET can match and even outperform 5 track FinFET; without the need to lower S/D contact resistivity down to $5text{e}-10Omega.text{cm}^{2}$ or to elevate the channel stress up to 2GPa. All gains in power-performance-area at circuit-level are maintained at block-level, making 4 track CFET a suitable candidate for N3 & N2 technologies. Keywords: CFET, scaling, S/D engineering, Pi-gate.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"38 1","pages":"T204-T205"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91038183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776536
Dae-woo Kim, Taejoo Hwang
As the 4th industry revolution emerges into the semiconductor industry, high computing power and high data bandwidth are required for semiconductor devices. These demands lead to the adaption of the advanced packaging technology. For mobile application, fan-out technologies are used for smart phones due to small form factors and thermal performances. For server applications, 2.5D and 3D technologies are employed for cloud and artificial intelligence in terms of high memory bandwidth and a big die. However, there are two significant issues to resolve for advanced packaging. One is a thermal issue and the other is an electrical issue. Novel thermal materials and package structures are expected to improve the thermal performances. Redistribution substrate and through silicon via will reduce electrical loss for high speed signals. In this paper, we will investigate how the packaging technologies evolve in the future.
{"title":"The Future of Advanced Package Solutions","authors":"Dae-woo Kim, Taejoo Hwang","doi":"10.23919/VLSIT.2019.8776536","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776536","url":null,"abstract":"As the 4th industry revolution emerges into the semiconductor industry, high computing power and high data bandwidth are required for semiconductor devices. These demands lead to the adaption of the advanced packaging technology. For mobile application, fan-out technologies are used for smart phones due to small form factors and thermal performances. For server applications, 2.5D and 3D technologies are employed for cloud and artificial intelligence in terms of high memory bandwidth and a big die. However, there are two significant issues to resolve for advanced packaging. One is a thermal issue and the other is an electrical issue. Novel thermal materials and package structures are expected to improve the thermal performances. Redistribution substrate and through silicon via will reduce electrical loss for high speed signals. In this paper, we will investigate how the packaging technologies evolve in the future.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"33 1","pages":"T48-T49"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74834144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776566
Z. Chai, W. Zhang, R. Degraeve, S. Clima, F. Hatem, J. F. Zhang, P. Freitas, J. Marsland, A. Fantini, D. Garbin, L. Goux, G. Kar
Comprehensive experimental and simulation evidence of the filamentary-type switching and Vth relaxation mechanism associated with defect charging/discharging in GexSe1-xovonic threshold switching (OTS) selector is reported. For the first time, area independence of conduction current at both on/off states, Weibull distribution of time-to-switch-on/off (t-on/off), Vth relaxation and its dependence on time, bias and temperature, which is in good agreement with our first-principles simulations in density functional theory, provide strong support for filament modulation by defect delocalzation/localization that is responsible for volatile switching.
{"title":"Evidence of filamentary switching and relaxation mechanisms in GexSe1-xOTS selectors","authors":"Z. Chai, W. Zhang, R. Degraeve, S. Clima, F. Hatem, J. F. Zhang, P. Freitas, J. Marsland, A. Fantini, D. Garbin, L. Goux, G. Kar","doi":"10.23919/VLSIT.2019.8776566","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776566","url":null,"abstract":"Comprehensive experimental and simulation evidence of the filamentary-type switching and Vth relaxation mechanism associated with defect charging/discharging in GexSe1-xovonic threshold switching (OTS) selector is reported. For the first time, area independence of conduction current at both on/off states, Weibull distribution of time-to-switch-on/off (t-on/off), Vth relaxation and its dependence on time, bias and temperature, which is in good agreement with our first-principles simulations in density functional theory, provide strong support for filament modulation by defect delocalzation/localization that is responsible for volatile switching.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"14 1","pages":"T238-T239"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78769415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776535
H. Arimura, D. Cott, G. Boccardi, R. Loo, K. Wostyn, S. Brus, E. Capogreco, A. Opdebeeck, L. Witters, T. Conard, S. Suhard, D. V. van Dorp, K. Kenis, L. Ragnarsson, J. Mitard, F. Holsteyns, V. De Heyn, D. Mocuta, N. Collaert, N. Horiguchi
We have demonstrated Ge nFinFETs with a record high $text{G}_{text{mSA}Gamma}/text{SS}_{text{SAT}}$ and PBTI reliability by improving the RMG high-k last process. The SiO2 dummy gate oxide (DGO) deposition and removal processes have been identified as knobs to improve electron mobility and PBTI reliability even with a nominally identical Si-passivated Ge gate stack. Surface oxidation of Ge channel during the DGO deposition is considered to impact the final gate stack. By suppressing the Ge channel surface oxidation, increasing mobility with decreasing fin width is obtained, whereas PBTI reliability, $text{D}_{text{IT}}$ of scaled fin as well as high-field mobility are improved by extending the DGO in-situ clean process, resulting in the record $text{Gm}_{text{SAT}}/text{SS}_{text{SAT}}$ of 5.4 at 73 nm Lg.
{"title":"A record GmSAT/SSSAT and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparation","authors":"H. Arimura, D. Cott, G. Boccardi, R. Loo, K. Wostyn, S. Brus, E. Capogreco, A. Opdebeeck, L. Witters, T. Conard, S. Suhard, D. V. van Dorp, K. Kenis, L. Ragnarsson, J. Mitard, F. Holsteyns, V. De Heyn, D. Mocuta, N. Collaert, N. Horiguchi","doi":"10.23919/VLSIT.2019.8776535","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776535","url":null,"abstract":"We have demonstrated Ge nFinFETs with a record high $text{G}_{text{mSA}Gamma}/text{SS}_{text{SAT}}$ and PBTI reliability by improving the RMG high-k last process. The SiO2 dummy gate oxide (DGO) deposition and removal processes have been identified as knobs to improve electron mobility and PBTI reliability even with a nominally identical Si-passivated Ge gate stack. Surface oxidation of Ge channel during the DGO deposition is considered to impact the final gate stack. By suppressing the Ge channel surface oxidation, increasing mobility with decreasing fin width is obtained, whereas PBTI reliability, $text{D}_{text{IT}}$ of scaled fin as well as high-field mobility are improved by extending the DGO in-situ clean process, resulting in the record $text{Gm}_{text{SAT}}/text{SS}_{text{SAT}}$ of 5.4 at 73 nm Lg.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"78 1","pages":"T92-T93"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83932802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776492
R. Xie, Chanro Park, R. Conti, R. Robison, Huimei Zhou, I. Saraf, A. Carr, S. Fan, K. Ryan, M. Belyansky, S. Pancharatnam, A. Young, Junli Wang, A. Greene, K. Cheng, Juntao Li, R. Conte, Hao Tang, K. Choi, H. Amanapu, B. Peethala, R. Muthinti, M. Raymond, C. Prindle, Yong Liang, S. Tsai, V. Kamineni, A. Labonté, N. Cave, D. Gupta, V. Basker, N. Loubet, D. Guo, B. Haran, A. Knorr, H. Bu
We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride materials that allows superior process integration for scaling while simplifying the SRAM cross-couple wiring. We show that the key feature to avoid both gate-contact (CB) to source-drain local interconnect (LI) shorts and the LI-contact (CA) to gate shorts is the shape of the LI cap. A trapezoid-shaped oxide (SiO2) LI cap with an appropriate taper angle eliminates shorting between the contacts in the gate and source-drain region. We further demonstrate that this oxide LI cap is fully compatible with Cobalt (Co) metallization with a novel selective tungsten (W) growth process. Additionally, this process enables the SRAM cross-couple (XC) in the same metallization level, eliminating the need for an upper level wiring and greatly simplifying routing in the SRAM cell.
{"title":"Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm","authors":"R. Xie, Chanro Park, R. Conti, R. Robison, Huimei Zhou, I. Saraf, A. Carr, S. Fan, K. Ryan, M. Belyansky, S. Pancharatnam, A. Young, Junli Wang, A. Greene, K. Cheng, Juntao Li, R. Conte, Hao Tang, K. Choi, H. Amanapu, B. Peethala, R. Muthinti, M. Raymond, C. Prindle, Yong Liang, S. Tsai, V. Kamineni, A. Labonté, N. Cave, D. Gupta, V. Basker, N. Loubet, D. Guo, B. Haran, A. Knorr, H. Bu","doi":"10.23919/VLSIT.2019.8776492","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776492","url":null,"abstract":"We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride materials that allows superior process integration for scaling while simplifying the SRAM cross-couple wiring. We show that the key feature to avoid both gate-contact (CB) to source-drain local interconnect (LI) shorts and the LI-contact (CA) to gate shorts is the shape of the LI cap. A trapezoid-shaped oxide (SiO2) LI cap with an appropriate taper angle eliminates shorting between the contacts in the gate and source-drain region. We further demonstrate that this oxide LI cap is fully compatible with Cobalt (Co) metallization with a novel selective tungsten (W) growth process. Additionally, this process enables the SRAM cross-couple (XC) in the same metallization level, eliminating the need for an upper level wiring and greatly simplifying routing in the SRAM cell.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"35 1","pages":"T148-T149"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81109102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776498
Chao-Ching Cheng, Yun-Yan Chung, Uing-Yang Li, Chao-Ting Lin, Chi-Feng Li, Jyun-Hong Chen, T. Lai, Kai-Shin Li, J. Shieh, S. Su, H. Chiang, Tzu-Chiang Chen, Lain‐Jong Li, H. P. Wong, C. Chien
Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS2 p-channel field-effect transistors (p-FETs) fabricated on SiOx/Si substrate using channel area-selective CVD growth. Smooth and uniform WS2 comprising approximately 6 layers was formed by area-selective CVD growth in which a patterned tungsten-source/drain served as the seed for WS2 growth. For a 40 nm gate length transistor, the device has impressive electrical characteristics: on/off ratio of ~106, a S.S. of ~97 mV/dec., and nearly zero DIBL.
{"title":"First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate","authors":"Chao-Ching Cheng, Yun-Yan Chung, Uing-Yang Li, Chao-Ting Lin, Chi-Feng Li, Jyun-Hong Chen, T. Lai, Kai-Shin Li, J. Shieh, S. Su, H. Chiang, Tzu-Chiang Chen, Lain‐Jong Li, H. P. Wong, C. Chien","doi":"10.23919/VLSIT.2019.8776498","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776498","url":null,"abstract":"Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS2 p-channel field-effect transistors (p-FETs) fabricated on SiOx/Si substrate using channel area-selective CVD growth. Smooth and uniform WS2 comprising approximately 6 layers was formed by area-selective CVD growth in which a patterned tungsten-source/drain served as the seed for WS2 growth. For a 40 nm gate length transistor, the device has impressive electrical characteristics: on/off ratio of ~106, a S.S. of ~97 mV/dec., and nearly zero DIBL.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"54 1","pages":"T244-T245"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84732429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776514
T. Srimani, G. Hills, C. Lau, M. Shulaker
Here we show a hardware prototype of a monolithic three-dimensional (3D) imaging system that integrates computing layers directly in the back-end-of-line (BEOL) of a conventional silicon imager. Such systems can transform imager output from raw pixel data to highly processed information. To realize our imager, we fabricate 3 vertical circuit layers directly on top of each other: a bottom layer of silicon pixels followed by two layers of CMOS carbon nanotube FETs (CNFETs) (comprising 2,784 CNFETs) that perform in-situ edge detection in real-time, before storing data in memory. This approach promises to enable image classification systems with improved nrocessing latencies.
{"title":"Monolithic Three-Dimensional Imaging System: Carbon Nanotube Computing Circuitry Integrated Directly Over Silicon Imager","authors":"T. Srimani, G. Hills, C. Lau, M. Shulaker","doi":"10.23919/VLSIT.2019.8776514","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776514","url":null,"abstract":"Here we show a hardware prototype of a monolithic three-dimensional (3D) imaging system that integrates computing layers directly in the back-end-of-line (BEOL) of a conventional silicon imager. Such systems can transform imager output from raw pixel data to highly processed information. To realize our imager, we fabricate 3 vertical circuit layers directly on top of each other: a bottom layer of silicon pixels followed by two layers of CMOS carbon nanotube FETs (CNFETs) (comprising 2,784 CNFETs) that perform in-situ edge detection in real-time, before storing data in memory. This approach promises to enable image classification systems with improved nrocessing latencies.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"33 1","pages":"T24-T25"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77817326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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