Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282471
I. Orlov, Frédéric Falise
We illustrate how automated scanners visualise internal defects in raw sapphire prior to its processing, and present some defect statistics that Scientific Visual has collected over five years of serving key sapphire suppliers in Europe and Asia. The article illustrates use of defect location and morphology data to reveal trends in sapphire quality, compare production modes, and to find out the optimal parameters for sapphire growth.
{"title":"Quality Control in Sapphire Growing: From Automated Defect Detection to Big Data Approach","authors":"I. Orlov, Frédéric Falise","doi":"10.1109/CSTIC49141.2020.9282471","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282471","url":null,"abstract":"We illustrate how automated scanners visualise internal defects in raw sapphire prior to its processing, and present some defect statistics that Scientific Visual has collected over five years of serving key sapphire suppliers in Europe and Asia. The article illustrates use of defect location and morphology data to reveal trends in sapphire quality, compare production modes, and to find out the optimal parameters for sapphire growth.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"107 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90861051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282453
Jingbo Gao, Wenbo Yin, W. Luk, Lingli Wang
Latency-sensitive applications, such as Network File System (NFS) and High-Frequency Trading (HFT), demand ultra-low latency in network communications. These applications usually need more than one TCP session to guarantee Quality of Service (QoS) in case of communication interruption. This paper introduces a scalable multi-session TCP Offload Engine (TOE) for latency-sensitive applications which reduces the delay using the kernel bypass approach. The input-output receiving latency of a 48-byte-payload packet is 262.4 ns, and the sending latency of the same size packet is 179.3 ns. The latencies grow linearly with the amount of data at the rate of 12.8 ns per 8 bytes. The latencies are irrelevant to the TCP session number, which shows the scalability of our implementation.
{"title":"Scalable Multi-Session TCP Offload Engine for Latency-Sensitive Applications","authors":"Jingbo Gao, Wenbo Yin, W. Luk, Lingli Wang","doi":"10.1109/CSTIC49141.2020.9282453","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282453","url":null,"abstract":"Latency-sensitive applications, such as Network File System (NFS) and High-Frequency Trading (HFT), demand ultra-low latency in network communications. These applications usually need more than one TCP session to guarantee Quality of Service (QoS) in case of communication interruption. This paper introduces a scalable multi-session TCP Offload Engine (TOE) for latency-sensitive applications which reduces the delay using the kernel bypass approach. The input-output receiving latency of a 48-byte-payload packet is 262.4 ns, and the sending latency of the same size packet is 179.3 ns. The latencies grow linearly with the amount of data at the rate of 12.8 ns per 8 bytes. The latencies are irrelevant to the TCP session number, which shows the scalability of our implementation.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"31 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83238045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282422
Lulu Lai, Rui Qian, Biqiu Liu, Xiaobo Guo, Cong Zhang, Jun Huang, Y. J.
A more accurate and precise control of overlay performance in lithography process is required as design rule shrinks. Overlay performance is mainly determined by alignment and overlay measurement process, of which alignment and overlay marks play an important role. SADP (Self-aligned double patterning) process becomes widely adopted to realize half pitch of original design for 14nm technology node and beyond. The alignment and overlay marks formed by SADP process differ from traditional ones, which should be well designed to better comply with process condition and reduce the pattern loading effect induced by CMP and ETCH process, and eventually improve overlay performance. In this paper, the alignment behavior of different alignment marks formed via SADP process is investigated. On the other side, the overlay performance of segmented overlay marks is designed and compared with traditional ones to reveal the effect of segmentation on improving the overlay measurement precision and accuracy.
{"title":"Study of Alignment & Overlay Strategy in 14 nm Lithography Process","authors":"Lulu Lai, Rui Qian, Biqiu Liu, Xiaobo Guo, Cong Zhang, Jun Huang, Y. J.","doi":"10.1109/CSTIC49141.2020.9282422","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282422","url":null,"abstract":"A more accurate and precise control of overlay performance in lithography process is required as design rule shrinks. Overlay performance is mainly determined by alignment and overlay measurement process, of which alignment and overlay marks play an important role. SADP (Self-aligned double patterning) process becomes widely adopted to realize half pitch of original design for 14nm technology node and beyond. The alignment and overlay marks formed by SADP process differ from traditional ones, which should be well designed to better comply with process condition and reduce the pattern loading effect induced by CMP and ETCH process, and eventually improve overlay performance. In this paper, the alignment behavior of different alignment marks formed via SADP process is investigated. On the other side, the overlay performance of segmented overlay marks is designed and compared with traditional ones to reveal the effect of segmentation on improving the overlay measurement precision and accuracy.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"52 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81440273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In state of the art technologies, defect reduction is central to the achievement of low cost, high yield manufacturing. The defects occurred during the CMP process would lead to severe circuit failure and affect yield. In this paper, effect of slurry chemistry on surface defect during barrier CMP was studied. The experimental results showed that the complexation can effectively remove the copper residue, but would induce large dishing and erosion, if the complexation is so strong. The strong electrostatic attraction on oxide surface can improve the removal rate selectivity of OX to Cu and reduce the dishing and erosion. The dispersion effect and wetting effect can prevent the agglomeration of abrasive particles and make the copper surface hydrophilic, it can effectively reduce scratch defect during CMP.
{"title":"Role of Slurry Chemistry for Defects Reduction During Barrier CMP","authors":"Chenwei Wang, Yue Li, Guoqiang Song, Zhaoqing Huo, Jia Liu, Yu-ling Liu","doi":"10.1109/CSTIC49141.2020.9282561","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282561","url":null,"abstract":"In state of the art technologies, defect reduction is central to the achievement of low cost, high yield manufacturing. The defects occurred during the CMP process would lead to severe circuit failure and affect yield. In this paper, effect of slurry chemistry on surface defect during barrier CMP was studied. The experimental results showed that the complexation can effectively remove the copper residue, but would induce large dishing and erosion, if the complexation is so strong. The strong electrostatic attraction on oxide surface can improve the removal rate selectivity of OX to Cu and reduce the dishing and erosion. The dispersion effect and wetting effect can prevent the agglomeration of abrasive particles and make the copper surface hydrophilic, it can effectively reduce scratch defect during CMP.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"227 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89191331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, a novel bio-inspired hardware design of lateral divisive inhibition is proposed and demonstrated by using only one transistor of ferroelectric FET. The proposed design is simulated based on our developed FeFET model, and is also proved to be functional in spiking neural network. The new design with ultra-low hardware cost exhibits good biological plausibility, showing its great potential for neuromorphic computing.
{"title":"Implementation of Lateral Divisive Inhibition Based on Ferroelectric Fet with Ultra-Low Hardware Cost for Neuromorphic Computing","authors":"Shuhan Liu, Tianyi Liu, Zhiyuan Fu, Cheng Chen, Qianqian Huang, Ru Huang","doi":"10.1109/CSTIC49141.2020.9282540","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282540","url":null,"abstract":"In this work, a novel bio-inspired hardware design of lateral divisive inhibition is proposed and demonstrated by using only one transistor of ferroelectric FET. The proposed design is simulated based on our developed FeFET model, and is also proved to be functional in spiking neural network. The new design with ultra-low hardware cost exhibits good biological plausibility, showing its great potential for neuromorphic computing.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"31 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81578737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The effect of different injection beams (3ma, 5ma and 7ma) on the square resistance of polysilicon was studied by implanting BF2 with GSD200 (an energy of 30 Kev and dose of 2E15 under 1000°C, 30S rapid thermal annealing). The experimental results showed that the higher beam current would result in the lower resistance of polysilicon. The higher implant beam current will lead to more damage in polysilicon which will result in bigger poly grain size after thermal annealing, the bigger grain size will make more carriers in grain boundary and the resistance of polysilicon decreases accordingly. Key words: Polysilicon, Resistance, Implant, BF2, Beam current
{"title":"Effect of Implant Beam Current on Resistance of BF2 Implanted Polysilicon","authors":"Lichao Zong, Chunling Liu, Xingjie Wang, Liming Chen","doi":"10.1109/CSTIC49141.2020.9282404","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282404","url":null,"abstract":"The effect of different injection beams (3ma, 5ma and 7ma) on the square resistance of polysilicon was studied by implanting BF2 with GSD200 (an energy of 30 Kev and dose of 2E15 under 1000°C, 30S rapid thermal annealing). The experimental results showed that the higher beam current would result in the lower resistance of polysilicon. The higher implant beam current will lead to more damage in polysilicon which will result in bigger poly grain size after thermal annealing, the bigger grain size will make more carriers in grain boundary and the resistance of polysilicon decreases accordingly. Key words: Polysilicon, Resistance, Implant, BF2, Beam current","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"136 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77360945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282448
Lei Wang, Song Ma
With continued scaling of deep-submicron CMOS technology, more and more transistors are integrated within one die. Both the function verification and reliability performance are taken into account. In order to decrease unnecessary cost on backend package and assembling, variety of the test items and flows are transferred from FT (Final Test) level to CP (Chip Probing) level. However, the probe card is the key while wafer sort is in processing. Clean sheet, abrasion coefficient, clean frequency and overdrive impact the test stability and the cost of test directly. The balance on the above critical factors is necessary to be analyzed. The paper focuses on the abrasion coefficient model establishment and the probe card lifetime control for the specific probe card. The consumption algorithm model could be applied to improve the efficiency and control the cost of the test.
{"title":"Probe Card Lifetime Control and Abrasion Coefficient Study","authors":"Lei Wang, Song Ma","doi":"10.1109/CSTIC49141.2020.9282448","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282448","url":null,"abstract":"With continued scaling of deep-submicron CMOS technology, more and more transistors are integrated within one die. Both the function verification and reliability performance are taken into account. In order to decrease unnecessary cost on backend package and assembling, variety of the test items and flows are transferred from FT (Final Test) level to CP (Chip Probing) level. However, the probe card is the key while wafer sort is in processing. Clean sheet, abrasion coefficient, clean frequency and overdrive impact the test stability and the cost of test directly. The balance on the above critical factors is necessary to be analyzed. The paper focuses on the abrasion coefficient model establishment and the probe card lifetime control for the specific probe card. The consumption algorithm model could be applied to improve the efficiency and control the cost of the test.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"24 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74314911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282469
Lei Zhang, Y. Meng, Yi Xian, Wei Zhang, Haifeng Zhou, J. Fang
To achieve the local, as well as global, planarity of the wafer surface many innovative technologies have been developed. A robust Cu chemical mechanical polishing (CMP) process with better post CMP polishing profile, smooth copper surface, tighten metal line sheet resistance (Rs) and pattern loading control has been evaluated during the Cu CMP process at 14nm and beyond. It is well known that CMP causes pattern loading of a layer to be planarized due to uneven distribution of device structures and thus reducing the effectiveness of this technology. This paper will present how to improve pattern loading and dishing control with optimized polish methodology. Experiment results shown that there is no loading between dense line area and ISO line area, and better dishing performance.
{"title":"Pattern Loading Effect Optimization of BEOL Cu CMP in 14nm Technology Node","authors":"Lei Zhang, Y. Meng, Yi Xian, Wei Zhang, Haifeng Zhou, J. Fang","doi":"10.1109/CSTIC49141.2020.9282469","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282469","url":null,"abstract":"To achieve the local, as well as global, planarity of the wafer surface many innovative technologies have been developed. A robust Cu chemical mechanical polishing (CMP) process with better post CMP polishing profile, smooth copper surface, tighten metal line sheet resistance (Rs) and pattern loading control has been evaluated during the Cu CMP process at 14nm and beyond. It is well known that CMP causes pattern loading of a layer to be planarized due to uneven distribution of device structures and thus reducing the effectiveness of this technology. This paper will present how to improve pattern loading and dishing control with optimized polish methodology. Experiment results shown that there is no loading between dense line area and ISO line area, and better dishing performance.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"21 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80348319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gold wire bonding processes on Cu/low-K dies are simulated with two sequential bonding processes: capillary lowering down and USG power bonding. The major purpose of this modeling is to verify one engineering fact in wire bonding: bonded ball shape has significant impact on the IMC performance, i.e., the bond quality. In this study BBR is defined as the ratio of the bond ball height (BBH) to bond ball diameter (BBD) and regarded as the basic feature of bonded ball shape. The simulation results indicate that BBR at 25% has the highest appearance frequency of tensile strain in bond interface, and the appearance frequency of tensile strain decreases with BBR increasing from 25% to 45%. Since high appearance frequency of tensile strain in bond interface may cause good IMC, the BBR at 25% could be the best for IMC performance and bond quality. This conclusion from simulation is almost coincident with all gold wire bonding practices where the BBR needs to be kept around 25% for the best bonding performance.
{"title":"Effect of Bonded Ball Shape on Gold Wire Bonding Quality Based on ANSYS/LS-DYNA Simulation","authors":"Weidong Huang, Wei Wu, Jacky Wu, Grass Dong, CF Oo","doi":"10.1109/CSTIC49141.2020.9282527","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282527","url":null,"abstract":"Gold wire bonding processes on Cu/low-K dies are simulated with two sequential bonding processes: capillary lowering down and USG power bonding. The major purpose of this modeling is to verify one engineering fact in wire bonding: bonded ball shape has significant impact on the IMC performance, i.e., the bond quality. In this study BBR is defined as the ratio of the bond ball height (BBH) to bond ball diameter (BBD) and regarded as the basic feature of bonded ball shape. The simulation results indicate that BBR at 25% has the highest appearance frequency of tensile strain in bond interface, and the appearance frequency of tensile strain decreases with BBR increasing from 25% to 45%. Since high appearance frequency of tensile strain in bond interface may cause good IMC, the BBR at 25% could be the best for IMC performance and bond quality. This conclusion from simulation is almost coincident with all gold wire bonding practices where the BBR needs to be kept around 25% for the best bonding performance.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"45 4","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72549989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282525
Ziheng Li, Baicen Wan, Hongdi Wang, Andy Wang, Pujia Shan, Z. Liang, Jian Li, Zhijie Zhang
High-K Metal Gate (HKMG) is one of the most significant steps in CMOS manufacturing for 28nm node process and beyond. For Metal Gate step to be accurately controlled the Chemical-mechanical planarization (CMP) method is required for surface planarization. In Al-CMP, the control of metal residue defect and thickness uniformity were crucial to influence the device and yield performance. In this work, different slurry was investigated to control different pattern selectivity and within die uniformity. We found that, different selectivity slurry combined with different polish pad and disk have different effect in within die uniformity. With the same pad disk, for Al/Poly selectivity, slurry A was the twice of slurry B, and Al/Oxide selectivity didn't change at the same time. As a result, poly thickness was improved by 7% when gate height meet target, and over polish risk can be reduced. With another Pad/disk, poly thickness can be improved by 10% when Al residue was all removed clear. Besides, chemical rinse treatment were also investigated to remove Al residue..
{"title":"High-K Metal Gate Al-CMP Within Die Uniformity and Selectivity Study","authors":"Ziheng Li, Baicen Wan, Hongdi Wang, Andy Wang, Pujia Shan, Z. Liang, Jian Li, Zhijie Zhang","doi":"10.1109/CSTIC49141.2020.9282525","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282525","url":null,"abstract":"High-K Metal Gate (HKMG) is one of the most significant steps in CMOS manufacturing for 28nm node process and beyond. For Metal Gate step to be accurately controlled the Chemical-mechanical planarization (CMP) method is required for surface planarization. In Al-CMP, the control of metal residue defect and thickness uniformity were crucial to influence the device and yield performance. In this work, different slurry was investigated to control different pattern selectivity and within die uniformity. We found that, different selectivity slurry combined with different polish pad and disk have different effect in within die uniformity. With the same pad disk, for Al/Poly selectivity, slurry A was the twice of slurry B, and Al/Oxide selectivity didn't change at the same time. As a result, poly thickness was improved by 7% when gate height meet target, and over polish risk can be reduced. With another Pad/disk, poly thickness can be improved by 10% when Al residue was all removed clear. Besides, chemical rinse treatment were also investigated to remove Al residue..","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76406728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：