Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282443
Qingpeng Wang, Yu De Chen, Jacky Huang, Wuping Liu, Ervin Joseph
This paper provides an example of yield enhancement using virtual fabrication. A 6 transistors based static random access memory example on 7nm node technology was used in this case study. Yield loss caused by via contact-metal edge placement error was modeled and analyzed. The results show that yield can be enhanced from 48.4% to 99.0% through process window optimization and improved specification control. We identified high resistance failure as the top failure mode in both non-optimized and optimized process models.
{"title":"Yield Enhancement by Virtual Fabrication: Using Failure Bin Classification, Yield Prediction and Process Window Optimization to Identify and Prevent Process Failures","authors":"Qingpeng Wang, Yu De Chen, Jacky Huang, Wuping Liu, Ervin Joseph","doi":"10.1109/CSTIC49141.2020.9282443","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282443","url":null,"abstract":"This paper provides an example of yield enhancement using virtual fabrication. A 6 transistors based static random access memory example on 7nm node technology was used in this case study. Yield loss caused by via contact-metal edge placement error was modeled and analyzed. The results show that yield can be enhanced from 48.4% to 99.0% through process window optimization and improved specification control. We identified high resistance failure as the top failure mode in both non-optimized and optimized process models.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"19 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86949638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282586
Haiying Yuan, Kai Zhang, Tong Zheng, Yichen Wang
Temperature change, aging and voltage fluctuation also cause clock deviation of the crystal oscillator frequency, which makes a great impact on the real-time communication and network stability in the distributed control system. While local clock value is periodically corrected based on SAE AS6802 clock synchronization protocol in Time- Triggered Ethernet, but a large cumulative error occurs to the calibration cycle, which reduces the clock synchronization accuracy. According to the severe influence of temperature on crystal oscillator frequency, a digital frequency calibration circuit is designed in Local_clock module ofTTEthernet nodes, and it is modeled based on the frequency error Look-Up table generated by Temperature-Frequency characteristics. The maximum clock deviation between network nodes was analyzed to verify the synchronization performance of the TTEthernet. Numerous experimental results show that proposed digital frequency calibration scheme achieves high clock synchronization accuracy.
{"title":"Crystal Oscillator Frequency compensation technology of High Precision Clock Synchronization for Time-triggered Ethernet","authors":"Haiying Yuan, Kai Zhang, Tong Zheng, Yichen Wang","doi":"10.1109/CSTIC49141.2020.9282586","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282586","url":null,"abstract":"Temperature change, aging and voltage fluctuation also cause clock deviation of the crystal oscillator frequency, which makes a great impact on the real-time communication and network stability in the distributed control system. While local clock value is periodically corrected based on SAE AS6802 clock synchronization protocol in Time- Triggered Ethernet, but a large cumulative error occurs to the calibration cycle, which reduces the clock synchronization accuracy. According to the severe influence of temperature on crystal oscillator frequency, a digital frequency calibration circuit is designed in Local_clock module ofTTEthernet nodes, and it is modeled based on the frequency error Look-Up table generated by Temperature-Frequency characteristics. The maximum clock deviation between network nodes was analyzed to verify the synchronization performance of the TTEthernet. Numerous experimental results show that proposed digital frequency calibration scheme achieves high clock synchronization accuracy.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"09 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89734195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the flash cell physical size is scaled down, the related down scaling of decoder and page buffer area are also a challenge for chip design. High performance N type MOS including HVN_PT (in word-line decode circuit) and HVN_PB (in page buffer circuit) for l×-nm planner NAND flash are described in this paper. These N type MOS adopted a series of optimized structure and process integrated methods based on 2D TCAD process and device simulation, to achieve high channel, junction breakdown, and isolation voltage with smaller transistor area limited by down scaled NAND flash cell unit. Finally, these structure and process integrated methods were validated in HLMC 12-inch l×-nm NAND process flow.
{"title":"High Performance HVNMOS Development for Advanced Planner Nand Flash","authors":"Juanjuan Li, Zhi Tian, Xiao-Hua Ju, Tao Liu, Shaokang Yao, Haewan Yang, Yaoyu Chen","doi":"10.1109/CSTIC49141.2020.9282600","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282600","url":null,"abstract":"As the flash cell physical size is scaled down, the related down scaling of decoder and page buffer area are also a challenge for chip design. High performance N type MOS including HVN_PT (in word-line decode circuit) and HVN_PB (in page buffer circuit) for l×-nm planner NAND flash are described in this paper. These N type MOS adopted a series of optimized structure and process integrated methods based on 2D TCAD process and device simulation, to achieve high channel, junction breakdown, and isolation voltage with smaller transistor area limited by down scaled NAND flash cell unit. Finally, these structure and process integrated methods were validated in HLMC 12-inch l×-nm NAND process flow.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"140 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86589447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282480
Yu-Pu Yang, T. Lu, Song-Ho Wang, Hsueh-Er Chang, Peter j. Wang, Walter Lai, Y. Fuh, Tomi T. T. Li
In this study, pulsed dc reactive sputtering of aluminum nitride (AlN) thin films was investigated. The aluminum nitride thin films were deposited on Si (100) using a reactive direct current (DC) unbalanced magnetron sputtering system. The DC reactive sputtering was used in sputtering the aluminum targets in a mixture of argon (Ar) and nitrogen (N2) plasma. Processes of aluminum target sputtering were carried out in an atmosphere of a mixture of Ar and N2. However, pulsed DC reactive sputtering of aluminum targets was carried out at total pressures with N2:Ar ratios from 7:30 to 45:15. In-situ optical emission spectrometry (OES) was applied to obtain the optimal deposition rate and the highest sputtering yield from the effects of flow nitrogen/argon (N2:Ar) ratio and pulse frequency on OES intensity. Thus, we have compared Fourier-transform infrared spectroscopy (FTIR) spectra and X-ray diffraction (XRD) patterns of AlN films deposited on Si (100) by DC reactive sputtering with an Al target in the mixture of Ar and N2. FTIR and XRD investigated the quality of the films and the preferred orientation.
{"title":"Optimization on Deposition of Aluminum Nitride by Pulsed Direct Current Reactive Magnetron Sputtering","authors":"Yu-Pu Yang, T. Lu, Song-Ho Wang, Hsueh-Er Chang, Peter j. Wang, Walter Lai, Y. Fuh, Tomi T. T. Li","doi":"10.1109/CSTIC49141.2020.9282480","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282480","url":null,"abstract":"In this study, pulsed dc reactive sputtering of aluminum nitride (AlN) thin films was investigated. The aluminum nitride thin films were deposited on Si (100) using a reactive direct current (DC) unbalanced magnetron sputtering system. The DC reactive sputtering was used in sputtering the aluminum targets in a mixture of argon (Ar) and nitrogen (N2) plasma. Processes of aluminum target sputtering were carried out in an atmosphere of a mixture of Ar and N2. However, pulsed DC reactive sputtering of aluminum targets was carried out at total pressures with N2:Ar ratios from 7:30 to 45:15. In-situ optical emission spectrometry (OES) was applied to obtain the optimal deposition rate and the highest sputtering yield from the effects of flow nitrogen/argon (N2:Ar) ratio and pulse frequency on OES intensity. Thus, we have compared Fourier-transform infrared spectroscopy (FTIR) spectra and X-ray diffraction (XRD) patterns of AlN films deposited on Si (100) by DC reactive sputtering with an Al target in the mixture of Ar and N2. FTIR and XRD investigated the quality of the films and the preferred orientation.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"EM-33 2","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72609862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282567
H. Morinaga
In order to expand the use of CMP technologies into new applications, it is necessary to develop polishing technologies for a diverse range of materials and shapes. To improve the material removal rate of chemically stable materials, it is important i) to increase the abrasive particle velocity (vs. polishing object) to maximize the friction, and ii) to increase the number of working (adhered/active) particles by controlling the surface charge. To polish 3D shape precisely, design of polishing consumables (3D pad, magnetic polish slurry, polishing compound) and accurate pressure control are the keys.
{"title":"Solving CMP Challenges for Chemically Stable Materials and 3D Shapes","authors":"H. Morinaga","doi":"10.1109/CSTIC49141.2020.9282567","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282567","url":null,"abstract":"In order to expand the use of CMP technologies into new applications, it is necessary to develop polishing technologies for a diverse range of materials and shapes. To improve the material removal rate of chemically stable materials, it is important i) to increase the abrasive particle velocity (vs. polishing object) to maximize the friction, and ii) to increase the number of working (adhered/active) particles by controlling the surface charge. To polish 3D shape precisely, design of polishing consumables (3D pad, magnetic polish slurry, polishing compound) and accurate pressure control are the keys.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"23 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74462944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282596
Chao Wang, Jianwei Zhou, Chenwei Wang, Xue Zhang
In this paper, the influence of a novel complex agent (NH4)2SO3 and inhibitor 2,2’ -[[(methyl-1H-benzotriazol-1-yl) methyl]imino]diethanol (TT) based on hydrogen peroxide (H2O2) on Cu/Ru/TEOS was studied. Since our research group has studied the relationship between Cu and Ru before, we now make further supplement. The results showed that both Ru and TEOS increased with the increase of ammonium ion/NH4+) concentration, and the mechanism was studied by means of electrochemistry, possibly because of the electrostatic attraction between the NH4+ ions and Ru, and the addition of ammonium ions may reduce the thickness of the double electric layer on the surface of TEOS. So the Ru and TEOS removal rate goes up.
{"title":"Role of slurry Additions on Chemical Mechanical Polishing of Cu/Ru/TEOS in H2O2-based Slurry","authors":"Chao Wang, Jianwei Zhou, Chenwei Wang, Xue Zhang","doi":"10.1109/CSTIC49141.2020.9282596","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282596","url":null,"abstract":"In this paper, the influence of a novel complex agent (NH<inf>4</inf>)<inf>2</inf>SO<inf>3</inf> and inhibitor 2,2’ -[[(methyl-1H-benzotriazol-1-yl) methyl]imino]diethanol (TT) based on hydrogen peroxide (H<inf>2</inf>O<inf>2</inf>) on Cu/Ru/TEOS was studied. Since our research group has studied the relationship between Cu and Ru before, we now make further supplement. The results showed that both Ru and TEOS increased with the increase of ammonium ion/NH<inf>4</inf><sup>+</sup>) concentration, and the mechanism was studied by means of electrochemistry, possibly because of the electrostatic attraction between the NH<inf>4</inf><sup>+</sup> ions and Ru, and the addition of ammonium ions may reduce the thickness of the double electric layer on the surface of TEOS. So the Ru and TEOS removal rate goes up.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"15 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78937931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nanosilver paste with high operation temperature and low sintering temperature has attracted more and more attention for its promising application in high power devices. In this paper, the thermal properties of multi-scale nanosilver paste composed of nanometer and micrometer silver particles, and Ag-coated SiC particles were investigated. The thermal conductivity of multi-scale nanosilver paste increases with the increasing amount of SiC particles with Ag coating. The maximum value of Vickers hardness for multi-scale nanosilver paste with 0.5 wt.% Ag-coated SiC particles were 24.
{"title":"Characterterization of Multi-Scale Nanosilver Paste Reinforced with SIC Particles","authors":"Ziwei Jiang, Yongqian Sun, Qiaoran Zhang, Zhenlin Lv, Yan-pei Wu, Weijuan Xi, Cheng Zhou, Shujin Chen, Maomao Zhang, Johan Liu, Xiuzhen Lu","doi":"10.1109/CSTIC49141.2020.9282590","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282590","url":null,"abstract":"Nanosilver paste with high operation temperature and low sintering temperature has attracted more and more attention for its promising application in high power devices. In this paper, the thermal properties of multi-scale nanosilver paste composed of nanometer and micrometer silver particles, and Ag-coated SiC particles were investigated. The thermal conductivity of multi-scale nanosilver paste increases with the increasing amount of SiC particles with Ag coating. The maximum value of Vickers hardness for multi-scale nanosilver paste with 0.5 wt.% Ag-coated SiC particles were 24.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"24 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78961955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282446
Jiahao Liu, Liang He, Hua Chen, Pan Zhao, Yahui Su, Li Chao, Q. Pan
The reliability of solder joint determines whether the electronic system operates steadily and lastingly. As a common type of load, thermal stress has a non-ignorable effect on the reliability of electronic products. During the thermal cycles, the solder joints are subjected to periodic tensile and compressive stresses since the difference in thermal expansion coefficient of adjacent materials, whereby causing creep and thermal fatigue damage. As fatigue damage builds up, cracks generate and propagate continuously, which will lead to solder joint failure. In this paper, the finite element simulation method is used to simulate the stress-strain distribution in the Sn63Pb37 BGA solder joint array under temperature cyclic loading, the position of dangerous solder joint is located, and the lifetime of solder joints is predicted through the Manson-coffin model. Furthermore, the influence of PCB thickness and solder joint height on lifetime are analyzed.
{"title":"Reliability Simulation and Life Prediction of Sn63Pb37 BGA Solder Joint Under Thermal Cycling Load","authors":"Jiahao Liu, Liang He, Hua Chen, Pan Zhao, Yahui Su, Li Chao, Q. Pan","doi":"10.1109/CSTIC49141.2020.9282446","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282446","url":null,"abstract":"The reliability of solder joint determines whether the electronic system operates steadily and lastingly. As a common type of load, thermal stress has a non-ignorable effect on the reliability of electronic products. During the thermal cycles, the solder joints are subjected to periodic tensile and compressive stresses since the difference in thermal expansion coefficient of adjacent materials, whereby causing creep and thermal fatigue damage. As fatigue damage builds up, cracks generate and propagate continuously, which will lead to solder joint failure. In this paper, the finite element simulation method is used to simulate the stress-strain distribution in the Sn63Pb37 BGA solder joint array under temperature cyclic loading, the position of dangerous solder joint is located, and the lifetime of solder joints is predicted through the Manson-coffin model. Furthermore, the influence of PCB thickness and solder joint height on lifetime are analyzed.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"13 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75418568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282492
Dan Chen, Zhiyong Yang, Yuebin Zhu
Interferometer dynamic switching (IDS) is one of core technologies of long-travel-range moving stage of high-generation TFT scanner. The accuracy and repeat -ability of IDS have a major influence on the servo performance of moving stage, further, on the hierarchical overlay error of lithography machine. Zeroing model and dynamic switching strategy are of great significance to IDS. To solve IDS problem efficiently, in this paper, a novel zeroing model as well as a dynamic switching strategy have been proposed. Experiment results show that, the IDS error specification has been satisfied in both single and multiple IDS test scenarios by using our proposed method.
{"title":"Study of High-Precision Interferometer Dynamic Switching for TFT Long-Travel-Range Moving Stage","authors":"Dan Chen, Zhiyong Yang, Yuebin Zhu","doi":"10.1109/CSTIC49141.2020.9282492","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282492","url":null,"abstract":"Interferometer dynamic switching (IDS) is one of core technologies of long-travel-range moving stage of high-generation TFT scanner. The accuracy and repeat -ability of IDS have a major influence on the servo performance of moving stage, further, on the hierarchical overlay error of lithography machine. Zeroing model and dynamic switching strategy are of great significance to IDS. To solve IDS problem efficiently, in this paper, a novel zeroing model as well as a dynamic switching strategy have been proposed. Experiment results show that, the IDS error specification has been satisfied in both single and multiple IDS test scenarios by using our proposed method.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"20 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75449110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Scanning electron microscope (SEM) measurement is the dominant method to obtain critical dimension (CD) in lithography. In SEM measurement, electron beam exposed on photo resist (PR) will affect PR physical-chemically and cause PR shrinkage inevitably. This phenomenon is well-known in lithography and also studied by many researchers. In this paper, we reviewed previous research results and investigated the PR shrinkage effects on CD measurement of 193nm immersion photo resist in 14nm node. With patterns sizing down, it is important to choose an appropriate voltage, current and frame to avoid large amount shrinkage in the measurement. A 30nm size CD shrinks more than 10% until getting saturation. Different patterns and CD sizes possess different through pitch shrinkage performance, which means PR shrinkage will also impact OPC model setup.
{"title":"Effects of Electron Beam on Photo Resist Shrinkage and Critical Dimension in SEM Measurement","authors":"Yuyang Bian, Hongxu Sun, Lipeng Wang, Xijun Guan, Xiaobo Guo, Biqiu Liu, Cong Zhang, Jun Huang, Yu Zhang","doi":"10.1109/CSTIC49141.2020.9282495","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282495","url":null,"abstract":"Scanning electron microscope (SEM) measurement is the dominant method to obtain critical dimension (CD) in lithography. In SEM measurement, electron beam exposed on photo resist (PR) will affect PR physical-chemically and cause PR shrinkage inevitably. This phenomenon is well-known in lithography and also studied by many researchers. In this paper, we reviewed previous research results and investigated the PR shrinkage effects on CD measurement of 193nm immersion photo resist in 14nm node. With patterns sizing down, it is important to choose an appropriate voltage, current and frame to avoid large amount shrinkage in the measurement. A 30nm size CD shrinks more than 10% until getting saturation. Different patterns and CD sizes possess different through pitch shrinkage performance, which means PR shrinkage will also impact OPC model setup.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"16 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80135091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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