Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282559
Shuang Sun, Baotong Zhang, Yuancheng Yang, X. An, Xiaoyan Xu, Ru Huang, Ming Li
In this study, a kind of rectangular suspended single crystal Si nanowire with (001) planes and along <001> direction is developed via a CMOS-compatible top-down scheme. In this scheme, the nanowires are formed by anisotropic etching of TMAH on different silicon crystallography orientations. By designing the initial orientations of hard mask patterns, the rectangular suspended silicon nanowires can be successfully fabricated without any sacrificial epitaxial layers. Due to the damage-free process and the high mobility on (001) planes, this scheme will provide a high-quality channel for the future gate-alI-around silicon transistor technology.
{"title":"Rectangular suspended single crystal Si nanowire with (001) planes and <001> direction developed via TMAH wet chemical etching","authors":"Shuang Sun, Baotong Zhang, Yuancheng Yang, X. An, Xiaoyan Xu, Ru Huang, Ming Li","doi":"10.1109/CSTIC49141.2020.9282559","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282559","url":null,"abstract":"In this study, a kind of rectangular suspended single crystal Si nanowire with (001) planes and along <001> direction is developed via a CMOS-compatible top-down scheme. In this scheme, the nanowires are formed by anisotropic etching of TMAH on different silicon crystallography orientations. By designing the initial orientations of hard mask patterns, the rectangular suspended silicon nanowires can be successfully fabricated without any sacrificial epitaxial layers. Due to the damage-free process and the high mobility on (001) planes, this scheme will provide a high-quality channel for the future gate-alI-around silicon transistor technology.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"33 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80250767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282434
Dan Chen
A prominent problem of TFT lithography machine is that its plate stage's size and weight increase rapidly as it develops to higher generation. Because of plate stage's large size and heavy weight, it could be extremely difficult to achieve high bandwidth. Hence, it could be technical complicatedly and economic expensively to compensate vertical control error by the movement of plate stage. In this paper, a novel vertical closed-loop control method using the idea of coordinated movement of reticle stage and plate stage has been proposed. Experiment results show that, the total vertical control error based on our method has better performance, and CDU results based on these two methods are similar. However, our method has much higher technical feasibility and lower cost.
{"title":"A Novel Vertical Closed-Loop Control Method for High Generation TFT Lithography Machine","authors":"Dan Chen","doi":"10.1109/CSTIC49141.2020.9282434","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282434","url":null,"abstract":"A prominent problem of TFT lithography machine is that its plate stage's size and weight increase rapidly as it develops to higher generation. Because of plate stage's large size and heavy weight, it could be extremely difficult to achieve high bandwidth. Hence, it could be technical complicatedly and economic expensively to compensate vertical control error by the movement of plate stage. In this paper, a novel vertical closed-loop control method using the idea of coordinated movement of reticle stage and plate stage has been proposed. Experiment results show that, the total vertical control error based on our method has better performance, and CDU results based on these two methods are similar. However, our method has much higher technical feasibility and lower cost.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"282 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72701879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282405
W. Liang, Wenjian Yu
In this paper, we present a capacitance solver based on finite difference method (FDM). It simulates the cross section of interconnect structures and computes the capacitances per unit length. The techniques of forming symmetric coefficient matrix and nonuniform FDM grids are developed. And, with a sparse direct solver based on Cholesky factorization the presented solver exhibits high runtime efficiency with good accuracy. Experiments on pattern structures show that the presented solver is 3X faster than Raphael rc2, and is capable of accurately extracting structures with trapezoidal cross-section conductors and conformal dielectrics.
{"title":"A 2-D Capacitance Solver with Finite Difference Method","authors":"W. Liang, Wenjian Yu","doi":"10.1109/CSTIC49141.2020.9282405","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282405","url":null,"abstract":"In this paper, we present a capacitance solver based on finite difference method (FDM). It simulates the cross section of interconnect structures and computes the capacitances per unit length. The techniques of forming symmetric coefficient matrix and nonuniform FDM grids are developed. And, with a sparse direct solver based on Cholesky factorization the presented solver exhibits high runtime efficiency with good accuracy. Experiments on pattern structures show that the presented solver is 3X faster than Raphael rc2, and is capable of accurately extracting structures with trapezoidal cross-section conductors and conformal dielectrics.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"211 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74423017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282556
Ting Li, Qianqian Huang, Le Ye, Yuan Zhong, Mengxuan Yang, Yiqing Li, Yimei Li, Zhongxin Liang, Ru Huang
In this work, for bulk tunnel field-effect transistors (TFET), the electrical isolation solutions between neighboring devices for TFET integration are investigated. To suppress the leakage current of the P-type doped regions through the P-type substrate, a new effective isolation method is proposed and verified via simulation. The simulation shows the leakage current can be reduced from 10−5 A/µm to 10−13 A/µm. The solution is beneficial for TFETs to keep its advantages for ultra-low power applications such as implantable medical devices and Internet of Things.
{"title":"A Novel Electrical Isolation Solution for Tunnel FET Integration","authors":"Ting Li, Qianqian Huang, Le Ye, Yuan Zhong, Mengxuan Yang, Yiqing Li, Yimei Li, Zhongxin Liang, Ru Huang","doi":"10.1109/CSTIC49141.2020.9282556","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282556","url":null,"abstract":"In this work, for bulk tunnel field-effect transistors (TFET), the electrical isolation solutions between neighboring devices for TFET integration are investigated. To suppress the leakage current of the P-type doped regions through the P-type substrate, a new effective isolation method is proposed and verified via simulation. The simulation shows the leakage current can be reduced from 10−5 A/µm to 10−13 A/µm. The solution is beneficial for TFETs to keep its advantages for ultra-low power applications such as implantable medical devices and Internet of Things.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"48 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86054328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282544
Hairui Wang, Junyao Wang, Bo Wang
In this paper, we propose a hybrid domain framework to model the predistorter (PD) of a power amplifier (PA). It is available for obtaining the PD not only through a PA model but also a PA circuit on ADS. Simulation results show that with predistortion, the NMSE of the linearity can reach -50 dB and the ACPR can reduce around 17dB. What's more, a processing unit is designed to work with the PD, so that the PD's coefficients can adjust to the changes of the PA adaptively, making the PA perform great linear in the transmitter system. The proposed framework is a helpful guidance for the design of circuits.
{"title":"A Hybrid Domain Framework for Predistorter Modeling and Adaptive Digital Predistortion Realization","authors":"Hairui Wang, Junyao Wang, Bo Wang","doi":"10.1109/CSTIC49141.2020.9282544","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282544","url":null,"abstract":"In this paper, we propose a hybrid domain framework to model the predistorter (PD) of a power amplifier (PA). It is available for obtaining the PD not only through a PA model but also a PA circuit on ADS. Simulation results show that with predistortion, the NMSE of the linearity can reach -50 dB and the ACPR can reduce around 17dB. What's more, a processing unit is designed to work with the PD, so that the PD's coefficients can adjust to the changes of the PA adaptively, making the PA perform great linear in the transmitter system. The proposed framework is a helpful guidance for the design of circuits.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"29 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85300298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282468
N. Rashidi, Sungjun Yoon, J. Silva-Martínez
A Sigma-Delta Modulator (ΣΔ) that employs a hybrid loop filter to reduce its sensitivity to clock jitter is proposed. Part of the loop filter is implemented in the digital domain. The clock jitter effects are significantly reduced without changing the loop gain properties. The ΣΔ Modulator is implemented in TSMC 40 nm CMOS technology and occupies a 0.06 mm2. The solution consumes 6.9mW and operates at a clock rate of 500 MS/s. In the presence of 20psrms clock jitter (peak to peak jitter of almost 215 ps) and bandwidth of 10 MHz, the measured peak signal-to-noise-ratio (SNR) and peak signal-to-noise+distortion ratio (SNDR) are 65 dB, and 64 dB, respectively.
{"title":"A Clock Jitter Tolerant ΣΔ Modulator Employing a Hybrid Loop Filter in CMOS 40NM Technology","authors":"N. Rashidi, Sungjun Yoon, J. Silva-Martínez","doi":"10.1109/CSTIC49141.2020.9282468","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282468","url":null,"abstract":"A Sigma-Delta Modulator (ΣΔ) that employs a hybrid loop filter to reduce its sensitivity to clock jitter is proposed. Part of the loop filter is implemented in the digital domain. The clock jitter effects are significantly reduced without changing the loop gain properties. The ΣΔ Modulator is implemented in TSMC 40 nm CMOS technology and occupies a 0.06 mm2. The solution consumes 6.9mW and operates at a clock rate of 500 MS/s. In the presence of 20psrms clock jitter (peak to peak jitter of almost 215 ps) and bandwidth of 10 MHz, the measured peak signal-to-noise-ratio (SNR) and peak signal-to-noise+distortion ratio (SNDR) are 65 dB, and 64 dB, respectively.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"26 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90784656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282558
Shanshan Chen, Hungling Chen, Yin Long, Fengjia Pan, Wang Kai
With critical dimension shrinks during semiconductor process development, E-beam inspection (EBI) technique has play a vital role in detecting inline electrical defect by voltage contrast (VC). This study we introduce three different defect monitoring for 28nm process. The first is Cell to Cell inspection, which relies on comparing gray level differences between the defect site and adjacent sites or a reference image. However, while pixel size and grey level differences are small enough that defect is not easy to be detected as device shrink beyond, hot spot and die to database (D2DB) inspection that can help to distinguish true defects from a large amount of false alarm defects. These inspections provide timely and high efficiency feedback for health of line monitoring and yield improvement.
在半导体工艺发展过程中，电子束检测(EBI)技术在电压对比检测(VC)在线电气缺陷中发挥着至关重要的作用。本文介绍了三种不同的28nm制程缺陷监测方法。第一种是Cell to Cell检查，它依赖于比较缺陷位置和相邻位置或参考图像之间的灰度差。然而，虽然像素大小和灰度级差异足够小，由于设备缩小，缺陷不容易被发现，但热点和模到数据库(D2DB)检测可以帮助区分真正的缺陷和大量的虚警缺陷。这些检测为生产线的健康监测和成品率的提高提供了及时、高效的反馈。
{"title":"Detection of Electrical Defects by Distinguish Methodology Using an Advanced E-Beam Inspection System","authors":"Shanshan Chen, Hungling Chen, Yin Long, Fengjia Pan, Wang Kai","doi":"10.1109/CSTIC49141.2020.9282558","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282558","url":null,"abstract":"With critical dimension shrinks during semiconductor process development, E-beam inspection (EBI) technique has play a vital role in detecting inline electrical defect by voltage contrast (VC). This study we introduce three different defect monitoring for 28nm process. The first is Cell to Cell inspection, which relies on comparing gray level differences between the defect site and adjacent sites or a reference image. However, while pixel size and grey level differences are small enough that defect is not easy to be detected as device shrink beyond, hot spot and die to database (D2DB) inspection that can help to distinguish true defects from a large amount of false alarm defects. These inspections provide timely and high efficiency feedback for health of line monitoring and yield improvement.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"24 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91248600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282386
Shoutian Li, Changzhen Jia, X. Ren
The formulation approaches on ceria-based SoN (Stop on Nitride) slurry depend on the surface charge of ceria particles. For the ceria particles with positive charges, the slurry formulation will be different from the negative charged ceria. In this paper, we discuss the pros and cons of different approaches in formulating SoN slurry. Finally, we present the CMP performance results from the SoN slurry that is formulated with positive charged ceria.
{"title":"Stop on Nitride Slurry Development","authors":"Shoutian Li, Changzhen Jia, X. Ren","doi":"10.1109/CSTIC49141.2020.9282386","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282386","url":null,"abstract":"The formulation approaches on ceria-based SoN (Stop on Nitride) slurry depend on the surface charge of ceria particles. For the ceria particles with positive charges, the slurry formulation will be different from the negative charged ceria. In this paper, we discuss the pros and cons of different approaches in formulating SoN slurry. Finally, we present the CMP performance results from the SoN slurry that is formulated with positive charged ceria.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"131 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90367626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282425
Jing Zhang, Wei Xiong, Hualun Chen
In this paper, HV gate-oxide process has been optimized for solving SONOS 1.5T Flash cell Over-oxidation issue. In this type SONOS, TEOS was used as flash cell poly spacer, which has poorer ability blocking O2 diffusion during high temperature process. For this problem, traditional SONOS flash cell formation sequence was changed, N-pass HV gate oxide was preferential fabricated before flash cell. This method has demonstrated to dramatically prevent flash cell from suffering over-oxidation issue.
{"title":"HV Gate Oxide Over-Oxidation Process Optimization for SONOS 1.5T Flash Cell","authors":"Jing Zhang, Wei Xiong, Hualun Chen","doi":"10.1109/CSTIC49141.2020.9282425","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282425","url":null,"abstract":"In this paper, HV gate-oxide process has been optimized for solving SONOS 1.5T Flash cell Over-oxidation issue. In this type SONOS, TEOS was used as flash cell poly spacer, which has poorer ability blocking O2 diffusion during high temperature process. For this problem, traditional SONOS flash cell formation sequence was changed, N-pass HV gate oxide was preferential fabricated before flash cell. This method has demonstrated to dramatically prevent flash cell from suffering over-oxidation issue.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"05 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89725079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282415
Wei Yu, Xu Chen, Jing-fen Lu, Zhengying Wei
Over the past decades, semiconductor manufacturing has been drawing more and more attention. The procedures it involves could be considered as one of the most complicated processes in manufacturing. Owing to this, cases caused by abnormal machines happened from time to time. It requires a large amount of time and experience to solve this problem manually. Meanwhile, state of machines changes as time goes by. As a result, engineers are expected to find out root causes as soon as possible. In this paper, adaptive genetic algorithm is introduced to identify common bad tools and provide suggestions for case study.
{"title":"An Application of Adaptive Genetic Algorithm Combining Monte Carlo Method","authors":"Wei Yu, Xu Chen, Jing-fen Lu, Zhengying Wei","doi":"10.1109/CSTIC49141.2020.9282415","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282415","url":null,"abstract":"Over the past decades, semiconductor manufacturing has been drawing more and more attention. The procedures it involves could be considered as one of the most complicated processes in manufacturing. Owing to this, cases caused by abnormal machines happened from time to time. It requires a large amount of time and experience to solve this problem manually. Meanwhile, state of machines changes as time goes by. As a result, engineers are expected to find out root causes as soon as possible. In this paper, adaptive genetic algorithm is introduced to identify common bad tools and provide suggestions for case study.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89987430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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