Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282535
Z. Ji, James Brown, Jianfu Zhang
True Random number Generator (TRNG) is critical for secure communications. In this work, we explain in details regarding our recent solution on TRNG using random telegraph noise (RTN) including the benefits and the disadvantages. Security check is performed using the NIST randomness tests for both the RTN-based TRNG and various conventional pseudo random umber generator. The newly-proposed design shows excellent randomness, power consumption, low design complexity, small area and high speed, making it a suitable candidate for future cryptographically secured applications within the internet of things.
{"title":"True Random Number Generator (TRNG) for Secure Communications in the Era of IoT","authors":"Z. Ji, James Brown, Jianfu Zhang","doi":"10.1109/CSTIC49141.2020.9282535","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282535","url":null,"abstract":"True Random number Generator (TRNG) is critical for secure communications. In this work, we explain in details regarding our recent solution on TRNG using random telegraph noise (RTN) including the benefits and the disadvantages. Security check is performed using the NIST randomness tests for both the RTN-based TRNG and various conventional pseudo random umber generator. The newly-proposed design shows excellent randomness, power consumption, low design complexity, small area and high speed, making it a suitable candidate for future cryptographically secured applications within the internet of things.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"9 Suppl 1 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78356164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282551
Yanfei Ma, Yang Song, Changfeng Wang
In this paper, the formation of FDSOI raised source/drain (RSD) will be presented targeting for 22nm node technology. The source and drain are formed by epitaxial growth of Si or SiGe from SOI layer for NMOS or PMOS respectively. During the fabrication process, there are two major concerns regarding to the RSD formation --- the remained SOI acts as the seed for epitaxial growth, the epitaxy growth method will influence the performance of the device. In this work, we will discuss experimentally from three aspects in order to obtain sufficient SOI remain, and will propose two SiGe epitaxial schemes in order to attain uniform epitaxial profile. Advantages and disadvantages of each scheme will be investigated.
{"title":"Investigation of FDSOI Raised S/D Formation","authors":"Yanfei Ma, Yang Song, Changfeng Wang","doi":"10.1109/CSTIC49141.2020.9282551","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282551","url":null,"abstract":"In this paper, the formation of FDSOI raised source/drain (RSD) will be presented targeting for 22nm node technology. The source and drain are formed by epitaxial growth of Si or SiGe from SOI layer for NMOS or PMOS respectively. During the fabrication process, there are two major concerns regarding to the RSD formation --- the remained SOI acts as the seed for epitaxial growth, the epitaxy growth method will influence the performance of the device. In this work, we will discuss experimentally from three aspects in order to obtain sufficient SOI remain, and will propose two SiGe epitaxial schemes in order to attain uniform epitaxial profile. Advantages and disadvantages of each scheme will be investigated.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"416 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76817807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282427
Shijie Hu, Ming Li, Ru Huang
In this work, a TCAD simulation platform was set up to study the real poly-channel modeling, trap-induced noise and random grain doping in 3D NAND cell transistor. The random telegraph noise and size dependence was simulated and analyzed. Simulation results show that the RTN and grain size change have greater influence on threshold voltage (VT) and channel current (ID) in 3D NAND than doping fluctuation. It is shown that the instability caused by random doping cannot be ignored, too.
{"title":"TCAD Simulation on Random Telegraphy Noise and Grain-Induced Fluctuation of 3D Nand Cell Transisitors","authors":"Shijie Hu, Ming Li, Ru Huang","doi":"10.1109/CSTIC49141.2020.9282427","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282427","url":null,"abstract":"In this work, a TCAD simulation platform was set up to study the real poly-channel modeling, trap-induced noise and random grain doping in 3D NAND cell transistor. The random telegraph noise and size dependence was simulated and analyzed. Simulation results show that the RTN and grain size change have greater influence on threshold voltage (VT) and channel current (ID) in 3D NAND than doping fluctuation. It is shown that the instability caused by random doping cannot be ignored, too.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"33 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85523942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The investigation aims at the metal trench critical dimension (CD) and overlay variation monitoring methodology with voltage-contrast (VC) inspection. The VC inspection with negative charging mode was performed to detect metal trench CD and overlay variation issue, at NDC film deposition layer post second metal layer chemical and mechanical polish. Dark VC (DVC) defects were found at extreme wafer edge, which would cause end of line (EOL) yield loss by data retention soft bin failure. DVC defects were identified by inline SEM review results with high voltage and PFA analysis results. It was demonstrated that the defects were induced by metal trench CD and overlay variation. Furthermore, the defects impacted factors, including uniformity of thin film deposition and chemical and mechanical polish (CMP), the etching rate performance of all in one etch process, and even the e-chuck accumulated contamination of lithography, were also investigated. By increasing the relative process tools' offline monitor frequency and optimizing the prevent maintenance method of lithography tool, defects were fixed and trend low. The study here extended the usage of VC inspection to detect CD and overlay minor variation.
{"title":"Metal Trench Critical Dimension and Overlay Minor Variation Monitoring Method with Voltage Contrast Inspection","authors":"Lijing Huang, Qiliang Ni, Xiaofang Gu, Chao Han, Jiansi Yuan","doi":"10.1109/CSTIC49141.2020.9282585","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282585","url":null,"abstract":"The investigation aims at the metal trench critical dimension (CD) and overlay variation monitoring methodology with voltage-contrast (VC) inspection. The VC inspection with negative charging mode was performed to detect metal trench CD and overlay variation issue, at NDC film deposition layer post second metal layer chemical and mechanical polish. Dark VC (DVC) defects were found at extreme wafer edge, which would cause end of line (EOL) yield loss by data retention soft bin failure. DVC defects were identified by inline SEM review results with high voltage and PFA analysis results. It was demonstrated that the defects were induced by metal trench CD and overlay variation. Furthermore, the defects impacted factors, including uniformity of thin film deposition and chemical and mechanical polish (CMP), the etching rate performance of all in one etch process, and even the e-chuck accumulated contamination of lithography, were also investigated. By increasing the relative process tools' offline monitor frequency and optimizing the prevent maintenance method of lithography tool, defects were fixed and trend low. The study here extended the usage of VC inspection to detect CD and overlay minor variation.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88767546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282486
Dongyu Xu, Dingshuo Luo, Zhihong Wang, Wenzhan Zhou, Zhanyuan Hu
Lithography patterning is controlled by aerial images and photoresist behaviors. The projected aerial images could be changed by the reflectivity of material and topography. The photoresist process can be affected by baking, development, and local thickness changes. In this paper, we report a study of the optical contribution and the photoresist local/global loading effect from topography, showing a substantial influence on CD (critical dimension) control. Therefore the consideration of photoresist thickness and the refection from underlayers is a must when patterns locate on a complicated topographical environment.
{"title":"The Topography Effect on the Lithography Patterning Control for Implatation Layers","authors":"Dongyu Xu, Dingshuo Luo, Zhihong Wang, Wenzhan Zhou, Zhanyuan Hu","doi":"10.1109/CSTIC49141.2020.9282486","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282486","url":null,"abstract":"Lithography patterning is controlled by aerial images and photoresist behaviors. The projected aerial images could be changed by the reflectivity of material and topography. The photoresist process can be affected by baking, development, and local thickness changes. In this paper, we report a study of the optical contribution and the photoresist local/global loading effect from topography, showing a substantial influence on CD (critical dimension) control. Therefore the consideration of photoresist thickness and the refection from underlayers is a must when patterns locate on a complicated topographical environment.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"61 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85194298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper analyzed the special failure pattern in the wafer center region of 65nm NOR flash. By circuit and failure checking, confirmed the root cause is that the low read current from the big resistance induced by photo residues in self-align-source (SAS) area. The voltage non -uniformity and check-board yield failure were ascribed to the silicon dislocation in SAS active area induced by SAS loop implant. Additional anneal, and higher temperature of rapid thermal oxide, can improve these issue by repairing the dislocation. Decreasing resistance of SAS by dose can also improve yield loss corresponding to erasing cell. All above know-hows helped us to comprehend the new clue and orientation to optimize failure induced by erase failure, and provided the experience for continuous shrinkage of floating NOR flash cell.
{"title":"Study of Related Yield Loss and Mechanism of NOR Flash Self-Align-Source","authors":"Tian Zhi, Y. Qin, Gu Zhen, Juanjuan Li, Qiwei Wang, Haoyu Chen","doi":"10.1109/CSTIC49141.2020.9282516","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282516","url":null,"abstract":"This paper analyzed the special failure pattern in the wafer center region of 65nm NOR flash. By circuit and failure checking, confirmed the root cause is that the low read current from the big resistance induced by photo residues in self-align-source (SAS) area. The voltage non -uniformity and check-board yield failure were ascribed to the silicon dislocation in SAS active area induced by SAS loop implant. Additional anneal, and higher temperature of rapid thermal oxide, can improve these issue by repairing the dislocation. Decreasing resistance of SAS by dose can also improve yield loss corresponding to erasing cell. All above know-hows helped us to comprehend the new clue and orientation to optimize failure induced by erase failure, and provided the experience for continuous shrinkage of floating NOR flash cell.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"48 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83266548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282573
Yibo Lin, D. Pan, Haoxing Ren, Brucek Khailany
Modern backend design flow for very-large-scale-integrated (VLSI) circuits consists of many complicated stages and requires long turn-around time. Among these stages, VLSI placement plays a fundamental role in determining the physical locations of standard cells. Due to increasingly large design sizes, placement algorithms usually require long execution time to achieve high-quality solutions. Meanwhile, developing a placer often needs huge coding effort and tedius tuning, raising the bar of further researches. In this work, we present an open-source placement framework, DREAMPlace 2.01, with deep learning toolkit-enabled GPU acceleration for both global and detailed placement optimization to tackle the issues of efficiency and development overhead.
{"title":"DREAMPlace 2.0: Open-Source GPU-Accelerated Global and Detailed Placement for Large-Scale VLSI Designs","authors":"Yibo Lin, D. Pan, Haoxing Ren, Brucek Khailany","doi":"10.1109/CSTIC49141.2020.9282573","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282573","url":null,"abstract":"Modern backend design flow for very-large-scale-integrated (VLSI) circuits consists of many complicated stages and requires long turn-around time. Among these stages, VLSI placement plays a fundamental role in determining the physical locations of standard cells. Due to increasingly large design sizes, placement algorithms usually require long execution time to achieve high-quality solutions. Meanwhile, developing a placer often needs huge coding effort and tedius tuning, raising the bar of further researches. In this work, we present an open-source placement framework, DREAMPlace 2.01, with deep learning toolkit-enabled GPU acceleration for both global and detailed placement optimization to tackle the issues of efficiency and development overhead.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"11 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91515886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282569
Baotong Zhang, Xiaokang Li, Yuancheng Yang, Haixia Li, Ru Huang, Ming Li, Peimin Lu
In this work, the performance of HfOx-based RRAM with 30nm nanopillar-type electrode was investigated. Experiment results show that the novel device has lower operation voltages and higher resistance ratio than conventional flat electrode RRAM. The underlying physical mechanism is attributed to the enhanced electric field by the nanopillar electrode. This research will provide a valuable guidance for future scaling of oxide-based RRAM.
{"title":"Impact of Nanopillar-Type Electrode on HFOx -Based RRAM Performance","authors":"Baotong Zhang, Xiaokang Li, Yuancheng Yang, Haixia Li, Ru Huang, Ming Li, Peimin Lu","doi":"10.1109/CSTIC49141.2020.9282569","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282569","url":null,"abstract":"In this work, the performance of HfOx-based RRAM with 30nm nanopillar-type electrode was investigated. Experiment results show that the novel device has lower operation voltages and higher resistance ratio than conventional flat electrode RRAM. The underlying physical mechanism is attributed to the enhanced electric field by the nanopillar electrode. This research will provide a valuable guidance for future scaling of oxide-based RRAM.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"39 3 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90901076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As a typical representative of two-dimensional (2D) materials, recently Mos2 was considered as the candidate to the development of electronic synaptic devices due to its ultrathin thickness and special properties. However, dual-terminal artificial synapse devices still exit the challenges about the simulation of biological synapses, which is hard for two-terminal devices to update and read the synaptic weight at the same time. In this work, Mos2 films were grown by chemical vapor deposition (the sample's largest single triangular size is about 83µm), and three-terminal synaptic devices based on back-gate FETs on Si/SiO2 substrate were fabricated. MoS2 sample's morphology and device's structure were characterized by Raman spectroscopy and optical microscope (OM). The memtransistor has excellent resistive switching (RS) behavior. By optimizing the pulse, the memtransistor showed a better conductivity linearity, and typical synaptic characteristics were mimicked, such as short-term/long-term plasticity (STP/LTP), excitatory post-synaptic current (EPSC)/inhibitory post-synaptic current (IPSC) and paired-pulse facilitation (PPF).
{"title":"Gate Tunable Memtransistor based on Monolayer Molybdenum Disulfide","authors":"Meng Yan, F. Wang, Jiaqiang Shen, Xichao Di, Xin Lin, Huanhuan Di, Wei Mi, Kailiang Zhang","doi":"10.1109/CSTIC49141.2020.9282520","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282520","url":null,"abstract":"As a typical representative of two-dimensional (2D) materials, recently Mos2 was considered as the candidate to the development of electronic synaptic devices due to its ultrathin thickness and special properties. However, dual-terminal artificial synapse devices still exit the challenges about the simulation of biological synapses, which is hard for two-terminal devices to update and read the synaptic weight at the same time. In this work, Mos2 films were grown by chemical vapor deposition (the sample's largest single triangular size is about 83µm), and three-terminal synaptic devices based on back-gate FETs on Si/SiO2 substrate were fabricated. MoS2 sample's morphology and device's structure were characterized by Raman spectroscopy and optical microscope (OM). The memtransistor has excellent resistive switching (RS) behavior. By optimizing the pulse, the memtransistor showed a better conductivity linearity, and typical synaptic characteristics were mimicked, such as short-term/long-term plasticity (STP/LTP), excitatory post-synaptic current (EPSC)/inhibitory post-synaptic current (IPSC) and paired-pulse facilitation (PPF).","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"13 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84186574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282547
Jiantao Wang, Junfeng Yu, Yuming Sun, Cong Zhang, Xiaobo Guo, Biqiu Liu, Song Gao, Shuo Liu, Jun Huang, Yu Zhang
Overlay (OVL) is a key index in lithography, which will determine product quality, and its measurement is affected by many factors, such as measurement tool, measurement strategy, OVL mark and STI CMP, etc. For some layers used thick Photoresist(PR), OVL results are out of control due to worse PR profile, especially for asymmetric profile which will cause inaccurate mark signal reading, so it is difficult to guarantee to get actual OVL performance. In this paper, we take some of investigations to optimize OVL measurement accuracy of layer with thick PR, and the corresponding mechanism is also analyzed.
{"title":"Litho Process Optimization to Improve Overlay Measurement in Thick PR Layer","authors":"Jiantao Wang, Junfeng Yu, Yuming Sun, Cong Zhang, Xiaobo Guo, Biqiu Liu, Song Gao, Shuo Liu, Jun Huang, Yu Zhang","doi":"10.1109/CSTIC49141.2020.9282547","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282547","url":null,"abstract":"Overlay (OVL) is a key index in lithography, which will determine product quality, and its measurement is affected by many factors, such as measurement tool, measurement strategy, OVL mark and STI CMP, etc. For some layers used thick Photoresist(PR), OVL results are out of control due to worse PR profile, especially for asymmetric profile which will cause inaccurate mark signal reading, so it is difficult to guarantee to get actual OVL performance. In this paper, we take some of investigations to optimize OVL measurement accuracy of layer with thick PR, and the corresponding mechanism is also analyzed.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"64 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84414004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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