Sapphire substrate is the most commonly used material in semiconductor industry for GaN-based light emitting diodes (LEDs). Chemical mechanical polishing (CMP) is one of the most effective methods to achieve atomic-scale smooth surface. The effect of potassium salts on the CMP removal rate and surface roughness of sapphire substrate was investigated. In this paper, KNO3, KCl and K2S2O8 were used as an additive in sapphire slurry, respectively. From the result, it is found potassium salts can significantly improve the removal rate of sapphire substrate. Meanwhile, K2S2O8 is slightly better than the other two in the same condition. Furthermore, the removal mechanism of potassium salts for sapphire CMP was analyzed briefly.
{"title":"Effect of Potassium Salts on the Chemical Mechanical Polishing Efficiency of Sapphire Substrate","authors":"Yanan Lu, X. Niu, Yaqi Cui, Xin Zhao, Zhaoqing Huo, Chenghui Yang","doi":"10.1109/CSTIC49141.2020.9282406","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282406","url":null,"abstract":"Sapphire substrate is the most commonly used material in semiconductor industry for GaN-based light emitting diodes (LEDs). Chemical mechanical polishing (CMP) is one of the most effective methods to achieve atomic-scale smooth surface. The effect of potassium salts on the CMP removal rate and surface roughness of sapphire substrate was investigated. In this paper, KNO3, KCl and K2S2O8 were used as an additive in sapphire slurry, respectively. From the result, it is found potassium salts can significantly improve the removal rate of sapphire substrate. Meanwhile, K2S2O8 is slightly better than the other two in the same condition. Furthermore, the removal mechanism of potassium salts for sapphire CMP was analyzed briefly.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"31 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88536005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282485
Kai Zhou, Tianyu Zhang, Xurong Cao, Yanyan Chang
Jitter Measurement is an important part of High Speed test. With customer's test requirement rapidly growing, result only include RJ and DJ is not acceptable. The solution of test specific kinds of jitter (such as DDJ, DCD, ISI...) to verify the IC transform performance is strongly demanded by customers. So far, the industry of existing jitter measurement method include strobe method and Time-stamp method on TMU. However, the limitations are either complex or just measure several types of jitter. An industry leading solution of high accuracy jitter measurement by TMU directly sampling with new PRBS pattern reconstruction method is proposed in this paper. All types of jitter can be skillfully tested with the condition of no cost increase.
{"title":"New Precision Jitter Measurement Solution on TMU -- Challenge on PRBS Reconstruction","authors":"Kai Zhou, Tianyu Zhang, Xurong Cao, Yanyan Chang","doi":"10.1109/CSTIC49141.2020.9282485","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282485","url":null,"abstract":"Jitter Measurement is an important part of High Speed test. With customer's test requirement rapidly growing, result only include RJ and DJ is not acceptable. The solution of test specific kinds of jitter (such as DDJ, DCD, ISI...) to verify the IC transform performance is strongly demanded by customers. So far, the industry of existing jitter measurement method include strobe method and Time-stamp method on TMU. However, the limitations are either complex or just measure several types of jitter. An industry leading solution of high accuracy jitter measurement by TMU directly sampling with new PRBS pattern reconstruction method is proposed in this paper. All types of jitter can be skillfully tested with the condition of no cost increase.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"4 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88863617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282499
Qiang Wu, Yanli Li, Yushu Yang, Shoumian Chen
The introduction of Extremely Ultra-Violet (EUV) lithography in the photolithographic process can simplify process flow at 7 nm or more advanced technology nodes, which includes good linewidth and overlay budget control and reduction of hard mask layers. In a typical 5 nm logic process, the Contact-Poly Pitch (CPP) is 44–50 nm, the Minimum Metal Pitch (MPP) is 30–32 nm. And the overlay budget is estimated to be 2.5 nm (On Product Overlay, OPO). We have studied the process window of the 5 nm lithographic process with a self-developed RCWA algorithm based EUV simulation program and will present our results on process window and defectivity.
在光刻工艺中引入极紫外(EUV)光刻技术可以简化7纳米或更先进的技术节点的工艺流程，其中包括良好的线宽和覆盖预算控制以及减少硬掩模层。在典型的5nm逻辑工艺中，接触-聚节距(CPP)为44 - 50nm，最小金属节距(MPP)为30 - 32nm。覆盖预算估计为2.5 nm (On Product overlay, OPO)。我们利用自主开发的基于RCWA算法的EUV仿真程序对5nm光刻工艺的工艺窗口进行了研究，并将给出工艺窗口和缺陷的研究结果。
{"title":"A Study of Image Contrast, Stochastic Defectivity, and Optical Proximity Effect in EUV Photolithographic Process Under Typical 5 nm Logic Design Rules","authors":"Qiang Wu, Yanli Li, Yushu Yang, Shoumian Chen","doi":"10.1109/CSTIC49141.2020.9282499","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282499","url":null,"abstract":"The introduction of Extremely Ultra-Violet (EUV) lithography in the photolithographic process can simplify process flow at 7 nm or more advanced technology nodes, which includes good linewidth and overlay budget control and reduction of hard mask layers. In a typical 5 nm logic process, the Contact-Poly Pitch (CPP) is 44–50 nm, the Minimum Metal Pitch (MPP) is 30–32 nm. And the overlay budget is estimated to be 2.5 nm (On Product Overlay, OPO). We have studied the process window of the 5 nm lithographic process with a self-developed RCWA algorithm based EUV simulation program and will present our results on process window and defectivity.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"1 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76097456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282529
X. Shi, Yuhang Zhao, Shoumian Chen, Chen Li
Machine learning based computational lithography is intended to accelerate the speed of the solutions significantly. There are three critical aspects of AI computational lithography: (1). The feature vector design, (2). The approximate mapping function construction, (3). The model training scheme. Approximate mapping function construction can be realized using forward neural network architecture in theory, model training is an art with the help of mathematical understanding, while feature vector design must achieve optimal resolution, sufficiency and efficiency simultaneously. To pave the way of successful AI computational lithography implementation, we have designed physics based optimal feature vector for AI computational lithography. By combining this feature vector design method with deep neural network architecture, a universal machine learning based computational lithography framework can be established.
{"title":"AI Computational Lithography","authors":"X. Shi, Yuhang Zhao, Shoumian Chen, Chen Li","doi":"10.1109/CSTIC49141.2020.9282529","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282529","url":null,"abstract":"Machine learning based computational lithography is intended to accelerate the speed of the solutions significantly. There are three critical aspects of AI computational lithography: (1). The feature vector design, (2). The approximate mapping function construction, (3). The model training scheme. Approximate mapping function construction can be realized using forward neural network architecture in theory, model training is an art with the help of mathematical understanding, while feature vector design must achieve optimal resolution, sufficiency and efficiency simultaneously. To pave the way of successful AI computational lithography implementation, we have designed physics based optimal feature vector for AI computational lithography. By combining this feature vector design method with deep neural network architecture, a universal machine learning based computational lithography framework can be established.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"624 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77464567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282394
Chien Wang, Chengyu Xu
Wear leveling techniques have been successfully used in increasing the useful life of NAND flash devices. Although Phase-change Memory's endurance is much higher than NAND, and can reach up to a range from 106 to 109, it still lacks the endurance needed for use as system main memory such as DRAM, which has nearly ~1014 rewrite endurance. In this paper, we propose and have developed a novel statistical and hierarchical wear-leveling technique to be used in a 4Gb DRAM-like PCM chip. The technique uses real-time memory address statistics to compute the physical-to-device address mapping using an embedded CPU. The CPU automatically adjust for different system workloads based on current address statistics. Results from system simulations shows the techniques to be effective in our tile-based memory architecture while requiring relatively low computational overhead.
{"title":"Statistical Wear-Leveling for Phase Change Memory","authors":"Chien Wang, Chengyu Xu","doi":"10.1109/CSTIC49141.2020.9282394","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282394","url":null,"abstract":"Wear leveling techniques have been successfully used in increasing the useful life of NAND flash devices. Although Phase-change Memory's endurance is much higher than NAND, and can reach up to a range from 106 to 109, it still lacks the endurance needed for use as system main memory such as DRAM, which has nearly ~1014 rewrite endurance. In this paper, we propose and have developed a novel statistical and hierarchical wear-leveling technique to be used in a 4Gb DRAM-like PCM chip. The technique uses real-time memory address statistics to compute the physical-to-device address mapping using an embedded CPU. The CPU automatically adjust for different system workloads based on current address statistics. Results from system simulations shows the techniques to be effective in our tile-based memory architecture while requiring relatively low computational overhead.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"35 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79712484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282503
Yiling Sun, Jihong Zhang, Yu Jiang, F. Qiao, Keqiang He, Zhigang Zhang, K. Huang, Yushan
Due to the continuing improvements of CMOS image sensor (CIS) technology, the back side-illumination (BSI) structure was involved to overcome optical characteristics deterioration in smaller pixels. In BSI structure, bonding loop is necessary to adhere two wafers. However, multiple dielectric and metal layer on the bevel of the device wafer possibly to be the source of defect as it is so loose that peeling particles will fall on the wafer after trimming step and bubble defect will formed at last. The main objective of the work is to improve peeling particle performance. After insertion of bevel etch, the number of peeling particles was reduced to less than 5ea compared with more than 300ea without bevel etch. Ultimately, no more bubble defect was found due to peeling particles clear off. What's more, we also discuss the mechanism of peeling particles and bubble defect forming. And the roles of different components of the gas mixtures in the bevel etch process.
{"title":"Application of a Bevel Etch Process for Improving Particle Performance in CMOS Image Sensor Manufacture","authors":"Yiling Sun, Jihong Zhang, Yu Jiang, F. Qiao, Keqiang He, Zhigang Zhang, K. Huang, Yushan","doi":"10.1109/CSTIC49141.2020.9282503","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282503","url":null,"abstract":"Due to the continuing improvements of CMOS image sensor (CIS) technology, the back side-illumination (BSI) structure was involved to overcome optical characteristics deterioration in smaller pixels. In BSI structure, bonding loop is necessary to adhere two wafers. However, multiple dielectric and metal layer on the bevel of the device wafer possibly to be the source of defect as it is so loose that peeling particles will fall on the wafer after trimming step and bubble defect will formed at last. The main objective of the work is to improve peeling particle performance. After insertion of bevel etch, the number of peeling particles was reduced to less than 5ea compared with more than 300ea without bevel etch. Ultimately, no more bubble defect was found due to peeling particles clear off. What's more, we also discuss the mechanism of peeling particles and bubble defect forming. And the roles of different components of the gas mixtures in the bevel etch process.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"339 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77595985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Deep power down leakage is a very key requirement for IC chip, especially for the MCU chips with battery power supply. In this paper, we studied the deep power down mode chip leakage caused pocket shadowing effect due to poly L-shape layout. And we tried to optimize the layout and process to reduce the leakage.
{"title":"Deep Power Down Leakage Study Caused by Poly L-sbape Pattern","authors":"Chong Huang, M. Zhang, Fangce Sun, Steam Cao, Guanghua Yang, Susanna Zheng","doi":"10.1109/CSTIC49141.2020.9282454","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282454","url":null,"abstract":"Deep power down leakage is a very key requirement for IC chip, especially for the MCU chips with battery power supply. In this paper, we studied the deep power down mode chip leakage caused pocket shadowing effect due to poly L-shape layout. And we tried to optimize the layout and process to reduce the leakage.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"61 11","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91498701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282482
Weiwei Li, Zhilin Zhao, Zhen Liang, Yunqian Sun
The properties of nano-silica colloid prepared by different processes in silicon wafer chemical mechanical polishing (CMP) were studied. The different principles of preparing nano-silica colloid by ion exchange, silica hydrolysis and hydrolytic of TEOS were analyzed respectively. The differences in structure, dispersion, density, and surface morphology were compared. Under the same CMP process parameters, silica colloids prepared by three different processes were used for polishing experiments. The results demonstrate that the hydrolysis of TEOS silica colloid is not suitable for CMP due to the network structure, which made the silica colloid as abrasive can not imply sufficient mechanical friction. The colloidal particles prepared by silica hydrolysis are denser, more uniform, with better dispersion and rough surface. The polishing rate of it is higher than that of ion exchange silica in a certain particle size range, and as the diameter increases, the growth increases.
{"title":"Study on the Properties of Silica Colloid Prepared by Different Processes in Silicon Wafer CMP","authors":"Weiwei Li, Zhilin Zhao, Zhen Liang, Yunqian Sun","doi":"10.1109/CSTIC49141.2020.9282482","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282482","url":null,"abstract":"The properties of nano-silica colloid prepared by different processes in silicon wafer chemical mechanical polishing (CMP) were studied. The different principles of preparing nano-silica colloid by ion exchange, silica hydrolysis and hydrolytic of TEOS were analyzed respectively. The differences in structure, dispersion, density, and surface morphology were compared. Under the same CMP process parameters, silica colloids prepared by three different processes were used for polishing experiments. The results demonstrate that the hydrolysis of TEOS silica colloid is not suitable for CMP due to the network structure, which made the silica colloid as abrasive can not imply sufficient mechanical friction. The colloidal particles prepared by silica hydrolysis are denser, more uniform, with better dispersion and rough surface. The polishing rate of it is higher than that of ion exchange silica in a certain particle size range, and as the diameter increases, the growth increases.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"124 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91297919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282531
Jiang Linpeng, Zhuma YiZheng, Lu Lian, Li Quanbo, Huang Jun, Zhang Yu
The BARC as a lower cost structure material is widely used in IC manufacture. For I4nm technology node, it is used to determined ion implantation area. However, the ideal BRAC profile is hard to achieve since its soft material characteristic. This deeply restricts its application. In our study, the idealized vertical BARC profile is obtained by variety of BARC profile learning on ICP etcher, with the physical structure evaluated by SEM. In addition, the analysis of radicals and ions processing on the BARC etching and related profile shaped mechanism is proposed. The result induced PR profile plays very important roles in BARC profile develop.
{"title":"Well CD Control and Vertical Profile BARC Etch Development and Related Theory Research","authors":"Jiang Linpeng, Zhuma YiZheng, Lu Lian, Li Quanbo, Huang Jun, Zhang Yu","doi":"10.1109/CSTIC49141.2020.9282531","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282531","url":null,"abstract":"The BARC as a lower cost structure material is widely used in IC manufacture. For I4nm technology node, it is used to determined ion implantation area. However, the ideal BRAC profile is hard to achieve since its soft material characteristic. This deeply restricts its application. In our study, the idealized vertical BARC profile is obtained by variety of BARC profile learning on ICP etcher, with the physical structure evaluated by SEM. In addition, the analysis of radicals and ions processing on the BARC etching and related profile shaped mechanism is proposed. The result induced PR profile plays very important roles in BARC profile develop.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"15 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86916871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282450
Y. Meng, Lei Zhang, Yibin Li, Wei Zhang, Haifeng Zhou, J. Fang
Shallow trench isolation chemical mechanical polishing (STI CMP) technology has been widely applied in the fabrication of ultra large scale integrated (ULSI). In STI CMP, the defect, topography control, thickness uniformity and so on are all so critical, especially, scratch defect is the major problem. Pad, disk, agglomerated slurry particles and incoming particles are the main sources of the tiny scratch. In this paper, we conducted a detailed study on the influence of one-step AA pull back process on the bevel region of wafer, which led to the introduction of incoming particles and ultimately led to the increase of STI CMP scratch. It was find that by adding a brush bevel process before STI CMP can reduce the scratch by 66%.
{"title":"Impact of Bevel Condition on STI CMP Scratch","authors":"Y. Meng, Lei Zhang, Yibin Li, Wei Zhang, Haifeng Zhou, J. Fang","doi":"10.1109/CSTIC49141.2020.9282450","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282450","url":null,"abstract":"Shallow trench isolation chemical mechanical polishing (STI CMP) technology has been widely applied in the fabrication of ultra large scale integrated (ULSI). In STI CMP, the defect, topography control, thickness uniformity and so on are all so critical, especially, scratch defect is the major problem. Pad, disk, agglomerated slurry particles and incoming particles are the main sources of the tiny scratch. In this paper, we conducted a detailed study on the influence of one-step AA pull back process on the bevel region of wafer, which led to the introduction of incoming particles and ultimately led to the increase of STI CMP scratch. It was find that by adding a brush bevel process before STI CMP can reduce the scratch by 66%.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"15 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87022896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：