Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282594
C. Prawoto, Ying Xiao, M. Chan
This paper described two approaches using structured voids in the dielectric among the interconnect metals to achieve low interlayer and intralayer capacitance while maintaining sufficient mechanical strength to withstand the CMP process. The first approach is to use vertically aligned voids and experimental results show that it can be used to achieve very high porosity with much stronger mechanical strength than conventional structures. To further reduce the intralayer dielectric constant, air-gap technology with large void-to-solid ratio has been proposed. The fabrication method and measurement results are presented.
{"title":"Mechanically Stable Ultra-Low-K Dielectric and Air-Gap Technology","authors":"C. Prawoto, Ying Xiao, M. Chan","doi":"10.1109/CSTIC49141.2020.9282594","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282594","url":null,"abstract":"This paper described two approaches using structured voids in the dielectric among the interconnect metals to achieve low interlayer and intralayer capacitance while maintaining sufficient mechanical strength to withstand the CMP process. The first approach is to use vertically aligned voids and experimental results show that it can be used to achieve very high porosity with much stronger mechanical strength than conventional structures. To further reduce the intralayer dielectric constant, air-gap technology with large void-to-solid ratio has been proposed. The fabrication method and measurement results are presented.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"41 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87201320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282541
Tao Zhou, Chen Li, J. Duan, Xuan Zeng, Yuhang Zhao
An effective algorithm is designed for incorporating in a 3D stacked CMOS image sensor for image denoising in ultra-low light conditions. The algorithm originates from sparsity-prior of image and non-locally clustered sparse representation. The simulation results of the CIS image signal processing (ISP) demonstrate high-performance at intense noise level of ultra-low light images, which reveal a great potential of the CIS design in various applications such as night shot, security monitoring, machine-state inspection, medical imaging, biophysics detection, etc.
{"title":"Effective Sparsity-Prior Image Denoising Algorithm for CMOS Image Sensor in Ultra-Low Light Imaging Applications","authors":"Tao Zhou, Chen Li, J. Duan, Xuan Zeng, Yuhang Zhao","doi":"10.1109/CSTIC49141.2020.9282541","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282541","url":null,"abstract":"An effective algorithm is designed for incorporating in a 3D stacked CMOS image sensor for image denoising in ultra-low light conditions. The algorithm originates from sparsity-prior of image and non-locally clustered sparse representation. The simulation results of the CIS image signal processing (ISP) demonstrate high-performance at intense noise level of ultra-low light images, which reveal a great potential of the CIS design in various applications such as night shot, security monitoring, machine-state inspection, medical imaging, biophysics detection, etc.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"167 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87493573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282583
Wei Yu, Xu Chen, Jing-fen Lu, Zhengying Wei
We show the feasibility of this algorithm in finding tool commonality with N=10. Actually, we have experimented on different values of N. The value of each parameter is shown in Table I. Specially, we fixed β to be 1.0 in this section. As shown in Table II and Fig. 3, the performance actually gets better when we repeated the model for more times. However, the improvement is not significant. With the increase of N, the number of true positive alarms is steady while the number of false positive alarms decreased a little bit. To be specific, when N inclines from 5 to 10, the number of false positive alarms declines from 3 to 2, which, in turn, results in a slight increase of F1 score. There is no variation when N changes from 10 to 15. The trend when N grows from 15 to 20 is similar to the trend from 5 to 10. Taking the cost of computation into consideration, we finally chose N to be 10.
{"title":"An Application of Adaptive Genetic Algorithm Combining Monte Carlo Method","authors":"Wei Yu, Xu Chen, Jing-fen Lu, Zhengying Wei","doi":"10.1109/CSTIC49141.2020.9282583","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282583","url":null,"abstract":"We show the feasibility of this algorithm in finding tool commonality with N=10. Actually, we have experimented on different values of N. The value of each parameter is shown in Table I. Specially, we fixed β to be 1.0 in this section. As shown in Table II and Fig. 3, the performance actually gets better when we repeated the model for more times. However, the improvement is not significant. With the increase of N, the number of true positive alarms is steady while the number of false positive alarms decreased a little bit. To be specific, when N inclines from 5 to 10, the number of false positive alarms declines from 3 to 2, which, in turn, results in a slight increase of F1 score. There is no variation when N changes from 10 to 15. The trend when N grows from 15 to 20 is similar to the trend from 5 to 10. Taking the cost of computation into consideration, we finally chose N to be 10.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"14 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84081621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282550
Yurong Cao, Hu Li, Zhe Feng, Zujun Ji, Zhengyuan Zhao, Jessie Y.C. Chen, Youfeng Xu, Xiang Peng, Feng Ji
The causes and improving methods of chipping were studied from CMP (Chemical Mechanical Polishing) and Trim1 (First Trimming process before bonding) perspectives. Chipping is caused by worse wafer edge bonding quality which is impacted by wafer edge pattern step-height and edge profile. Increasing CMP remove amount could reduce step-height and improve chipping performance. Bias of carrier wafer WEE (Wafer Edge Exposure) and Trim1 width should be fixed for better extreme edge bonding quality, which brings better chipping performance.
{"title":"A Study of Causes and Improving Methods of Chipping in BSI Process","authors":"Yurong Cao, Hu Li, Zhe Feng, Zujun Ji, Zhengyuan Zhao, Jessie Y.C. Chen, Youfeng Xu, Xiang Peng, Feng Ji","doi":"10.1109/CSTIC49141.2020.9282550","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282550","url":null,"abstract":"The causes and improving methods of chipping were studied from CMP (Chemical Mechanical Polishing) and Trim1 (First Trimming process before bonding) perspectives. Chipping is caused by worse wafer edge bonding quality which is impacted by wafer edge pattern step-height and edge profile. Increasing CMP remove amount could reduce step-height and improve chipping performance. Bias of carrier wafer WEE (Wafer Edge Exposure) and Trim1 width should be fixed for better extreme edge bonding quality, which brings better chipping performance.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"162 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85974134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Two-dimensional (2D) heterostructures based on transition metal dichalcogenides have sparked significant attention due to their excellent electrical and optical properties. However, synthesis of heterojunction is still a challenge. In this work, Mos2/ws2vertical heterostructure was achieved on SiO2/Si substrate via transferring CVD-grown Mos2 onto WS2. The morphology and structure properties of the Mos2/ws2heterostructure were characterized by optical microscope (OM), atomic force microscope (AFM), scanning electron microscope (SEM), Raman spectroscopy. Compared with individual Mos2 or WS2, the slight offset of the Raman peaks in the Mos2/ws2heterostructure was observed, which implies the charge transfer of the heterojunction. A photodetector based on Mos2/ws2heterostructure was fabricated with a channel length of 2μm. High on/off ratio (>107) and electron mobility of 10 cm2V−1S−1 of the photodetector were achieved. This work plays an active role in the development of photoelectronic devices based on 2D heterostructures.
{"title":"Synthesis of Mos2/ws2Vertical Heterostructure and Its Photoelectric Properties","authors":"Xin Lin, F. Wang, Jiaqiang Shen, Xichao Di, Huanhuan Di, Meng Yan, Kailiang Zhang","doi":"10.1109/CSTIC49141.2020.9282575","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282575","url":null,"abstract":"Two-dimensional (2D) heterostructures based on transition metal dichalcogenides have sparked significant attention due to their excellent electrical and optical properties. However, synthesis of heterojunction is still a challenge. In this work, Mos2/ws2vertical heterostructure was achieved on SiO2/Si substrate via transferring CVD-grown Mos2 onto WS2. The morphology and structure properties of the Mos2/ws2heterostructure were characterized by optical microscope (OM), atomic force microscope (AFM), scanning electron microscope (SEM), Raman spectroscopy. Compared with individual Mos2 or WS2, the slight offset of the Raman peaks in the Mos2/ws2heterostructure was observed, which implies the charge transfer of the heterojunction. A photodetector based on Mos2/ws2heterostructure was fabricated with a channel length of 2μm. High on/off ratio (>107) and electron mobility of 10 cm2V−1S−1 of the photodetector were achieved. This work plays an active role in the development of photoelectronic devices based on 2D heterostructures.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"11 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82093374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282566
K. Xiao, J. Liu, J. Deng, Y. Jiang, W. Bao, A. Zaslavsky, S. Cristoloveanu, X. Gong, J. Wan
In this work, we review our recent studies on several novel devices built on silicon-on-insulator (SOI) substrates. The sharp-switching Z2-FET, based on a feedback mechanism, has been demonstrated as suitable for many applications. The PISD, capable of in-situ photoelectron sensing, has been used as a one-transistor active pixel sensor (1T-APS). Furthermore, an SOI/MoS2 heterojunction FET has been demonstrated as both a photodetector with a dynamic response spectrum and as a novel one-transistor wavelength detector (1T-WD) with an output signal sensitive to the variation of wavelength rather than intensity.
{"title":"Novel Semiconductor devices Based on SOL Substrate","authors":"K. Xiao, J. Liu, J. Deng, Y. Jiang, W. Bao, A. Zaslavsky, S. Cristoloveanu, X. Gong, J. Wan","doi":"10.1109/CSTIC49141.2020.9282566","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282566","url":null,"abstract":"In this work, we review our recent studies on several novel devices built on silicon-on-insulator (SOI) substrates. The sharp-switching Z2-FET, based on a feedback mechanism, has been demonstrated as suitable for many applications. The PISD, capable of in-situ photoelectron sensing, has been used as a one-transistor active pixel sensor (1T-APS). Furthermore, an SOI/MoS2 heterojunction FET has been demonstrated as both a photodetector with a dynamic response spectrum and as a novel one-transistor wavelength detector (1T-WD) with an output signal sensitive to the variation of wavelength rather than intensity.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81186238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282533
Jianrong Xu
In this paper, a wafer level current testing method is presented. The proposed method gives a pre-testing on wafer level before packaging test. By a simple current testing, which can shorten the period of the process development and verification. Detailed procedure and advantages of the WAT test algorithm are given. the method is detecting the static current of the output signal (IBIAS module), which can check whether the function can be acted. Also the same data can be used for predicting the characteristics of dynamic power circuit.
{"title":"A Simple Current Test Method on Wafer Level to Pre-Verify Circuit Function","authors":"Jianrong Xu","doi":"10.1109/CSTIC49141.2020.9282533","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282533","url":null,"abstract":"In this paper, a wafer level current testing method is presented. The proposed method gives a pre-testing on wafer level before packaging test. By a simple current testing, which can shorten the period of the process development and verification. Detailed procedure and advantages of the WAT test algorithm are given. the method is detecting the static current of the output signal (IBIAS module), which can check whether the function can be acted. Also the same data can be used for predicting the characteristics of dynamic power circuit.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"56 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90516925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282493
I. Kashkoush, D. Waugh, Gim S. Chen
The effect of in-situ process cleaning before epitaxial deposition was studied. The process includes using dissolved ozone to remove organics from the wafers' surface. In addition, the process was conducted in-situ without transferring the wafers from process to rinse tanks as is traditionally done. Results show that the dissolved ozone has significantly improved the yield results when compared to a process without using dissolved ozone as a surface treatment. The results also showed that dilute chemicals and in-situ HF/Drying are key factors required in wafer processing for successful film deposition in advanced IC manufacturing.
{"title":"Effect of Dissolved Ozone and In-Situ Wafer Cleaning on Pre-Epitaxial Deposition for Next Generation Semiconductor Devices","authors":"I. Kashkoush, D. Waugh, Gim S. Chen","doi":"10.1109/CSTIC49141.2020.9282493","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282493","url":null,"abstract":"The effect of in-situ process cleaning before epitaxial deposition was studied. The process includes using dissolved ozone to remove organics from the wafers' surface. In addition, the process was conducted in-situ without transferring the wafers from process to rinse tanks as is traditionally done. Results show that the dissolved ozone has significantly improved the yield results when compared to a process without using dissolved ozone as a surface treatment. The results also showed that dilute chemicals and in-situ HF/Drying are key factors required in wafer processing for successful film deposition in advanced IC manufacturing.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"15 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90770262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282601
Y. Zhang, J. Chong, C. Wang, Q. Xie, D. Li
This paper illustrated Quasi-Atomic Layer Etching (Q-ALE) process, based on Inductively Coupled Plasma (ICP) etching technology. Q-ALE process could solve several conventional plasma etching issues, for instance, Aspect Ratio Dependent Etching (ARDE) effect. Furthermore, Q-ALE process could achieve relatively high etching uniformity with low surface roughness and low etching damage for silicon and compound semiconductors etching applications.
{"title":"Quasi-Atomic Layer Etching Technology for High Uniformity Etching Applications","authors":"Y. Zhang, J. Chong, C. Wang, Q. Xie, D. Li","doi":"10.1109/CSTIC49141.2020.9282601","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282601","url":null,"abstract":"This paper illustrated Quasi-Atomic Layer Etching (Q-ALE) process, based on Inductively Coupled Plasma (ICP) etching technology. Q-ALE process could solve several conventional plasma etching issues, for instance, Aspect Ratio Dependent Etching (ARDE) effect. Furthermore, Q-ALE process could achieve relatively high etching uniformity with low surface roughness and low etching damage for silicon and compound semiconductors etching applications.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"54 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91367817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282549
Baoli Peng, V. Pavlidis, Yuanqing Cheng
Monolithic 3D integration can approach ultra-high device density compared to TSV -based integration owing to the sequential process. So it can effectively sustain Moore's law without resorting to costly technology shrinking. Nevertheless, heat dissipation problem in M3D ICs poses a big challenge, and is different from TSV -based counterparts due to close thermal coupling between neighboring tiers, which requires further investigations. In this work, we compare the thermal characteristics of M3D ICs to those of 2D ICs in 45nm technology node with a thermal model based on the finite element method. Experimental results show that the average and maximum temperature of M3D ICs is higher. We expect this work can invoke more research interests in thermal modeling and thermal aware physical design of M3D ICs.
{"title":"Thermal Modeling of Monolithic 3D ICs","authors":"Baoli Peng, V. Pavlidis, Yuanqing Cheng","doi":"10.1109/CSTIC49141.2020.9282549","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282549","url":null,"abstract":"Monolithic 3D integration can approach ultra-high device density compared to TSV -based integration owing to the sequential process. So it can effectively sustain Moore's law without resorting to costly technology shrinking. Nevertheless, heat dissipation problem in M3D ICs poses a big challenge, and is different from TSV -based counterparts due to close thermal coupling between neighboring tiers, which requires further investigations. In this work, we compare the thermal characteristics of M3D ICs to those of 2D ICs in 45nm technology node with a thermal model based on the finite element method. Experimental results show that the average and maximum temperature of M3D ICs is higher. We expect this work can invoke more research interests in thermal modeling and thermal aware physical design of M3D ICs.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"22 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81441655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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