Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282498
Wei Liu, Haibo Lei, Xuejiao Wang
This paper presents a new SiGe profile of 28nm CMOS technology using conventional poly gate and SiON gate dielectric (Poly/SiON) with best-in-the-class 27nm pFET transistor. PFET Drive current of 431 μA/μm at off current 7.5×l0−10A/μm were achieved at Vd = -1.05V, which performance is 12% higher than standard SiGe structure. TCAD simulation reveals that compressive stress intensity of modified SiGe is ~3% higher than that of standard SiGe. The effective mobility curves are obtained by split CV method, the mobility peak value of modified SiGe is also higher. This reveals compressive stress induced in the channel and decreasing parasitic resistance in SD region by modified SiGe structure are shown to be the major source of the observed performance enhancement. This research about pFET performance boosting through SiGe profile modification has given an optimized direction for mass production in 28nm platform.
{"title":"Optimization of embedded SiGe process to enhance PFET performance on 28nm low power platform","authors":"Wei Liu, Haibo Lei, Xuejiao Wang","doi":"10.1109/CSTIC49141.2020.9282498","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282498","url":null,"abstract":"This paper presents a new SiGe profile of 28nm CMOS technology using conventional poly gate and SiON gate dielectric (Poly/SiON) with best-in-the-class 27nm pFET transistor. PFET Drive current of 431 μA/μm at off current 7.5×l0−10A/μm were achieved at Vd = -1.05V, which performance is 12% higher than standard SiGe structure. TCAD simulation reveals that compressive stress intensity of modified SiGe is ~3% higher than that of standard SiGe. The effective mobility curves are obtained by split CV method, the mobility peak value of modified SiGe is also higher. This reveals compressive stress induced in the channel and decreasing parasitic resistance in SD region by modified SiGe structure are shown to be the major source of the observed performance enhancement. This research about pFET performance boosting through SiGe profile modification has given an optimized direction for mass production in 28nm platform.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"42 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82057223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282521
M. Wang, Hungling Chen, Yin Long, Hao Guo
The systematic defect in the CT holes of the wafer edge are always observed in the advanced semiconductor process, which will directly result in chip yield loss or reliability issue. In this study, the novel bright field inspection (BFI) and electron-beam inspection (EBI) were applied to enhance the monitoring of the inline CT defect, including CT open, over polish and W_pits, so that the process window and stability can be verified and examined instantly. Furthermore, a series of process evaluation were carried out, and the results showed that the failure mode contained the poor uniformity of CT hole CD and film thickness. Interestingly, the processes were related to each other during ILD~CTW loop, but meanwhile they exhibited weak stability in the wafer edge and narrow window in the advanced process, as shown in Figure 1. On the basis of this reason, the root cause of these defects was very intricately. Therefore, the corresponding improvement actions for removing these CT defects were executed through a comprehensive and deep discussion of the defects formation mechanism. In detail, the W_pits was fixed by optimizing the uniformity of CT hole CD and controlling the uniformity of film thickness, which were impacted by photo and etch process, chemical and mechanical polish (CMP) process, respectively. Meanwhile, the CT open defect in the wafer edge were improved significantly based on plenty of CT etch split experiments.
{"title":"The Inspection and Solution of Inline CT Defect for 28NM Process Improvement","authors":"M. Wang, Hungling Chen, Yin Long, Hao Guo","doi":"10.1109/CSTIC49141.2020.9282521","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282521","url":null,"abstract":"The systematic defect in the CT holes of the wafer edge are always observed in the advanced semiconductor process, which will directly result in chip yield loss or reliability issue. In this study, the novel bright field inspection (BFI) and electron-beam inspection (EBI) were applied to enhance the monitoring of the inline CT defect, including CT open, over polish and W_pits, so that the process window and stability can be verified and examined instantly. Furthermore, a series of process evaluation were carried out, and the results showed that the failure mode contained the poor uniformity of CT hole CD and film thickness. Interestingly, the processes were related to each other during ILD~CTW loop, but meanwhile they exhibited weak stability in the wafer edge and narrow window in the advanced process, as shown in Figure 1. On the basis of this reason, the root cause of these defects was very intricately. Therefore, the corresponding improvement actions for removing these CT defects were executed through a comprehensive and deep discussion of the defects formation mechanism. In detail, the W_pits was fixed by optimizing the uniformity of CT hole CD and controlling the uniformity of film thickness, which were impacted by photo and etch process, chemical and mechanical polish (CMP) process, respectively. Meanwhile, the CT open defect in the wafer edge were improved significantly based on plenty of CT etch split experiments.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"37 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85160862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282418
Jun Hu, Zhaozhao Xu, Wenting Duan, Ziquan Fang, Donghua Liu, W. Qian
In the traditional CMOS manufacturing process, we often use the IV curve to evaluate the characteristics of the transistor, and sometimes the IdVg curves of the transistor will appear double hump, especially for the NMOS. This paper analyzes mechanism of the double hump phenomenon of the IdVg curve. There are two main causes, one is due to the segregation effect of impurities, and the other is due to the manufacturing process of STI. This article also shares ways to improve this phenomenon.
{"title":"Study of MOSFET IDVG Curve Double Hump Effect","authors":"Jun Hu, Zhaozhao Xu, Wenting Duan, Ziquan Fang, Donghua Liu, W. Qian","doi":"10.1109/CSTIC49141.2020.9282418","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282418","url":null,"abstract":"In the traditional CMOS manufacturing process, we often use the IV curve to evaluate the characteristics of the transistor, and sometimes the IdVg curves of the transistor will appear double hump, especially for the NMOS. This paper analyzes mechanism of the double hump phenomenon of the IdVg curve. There are two main causes, one is due to the segregation effect of impurities, and the other is due to the manufacturing process of STI. This article also shares ways to improve this phenomenon.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"35 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85511129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282564
W. Lau
Two important key modifications of theory of leakage current mechanisms for MIM capacitors will be proposed. The first modification is the proposal of a new unified theory for the image force dielectric constant used in the Schottky emission and Poole-Frenkel equations. The second modification is that when the leakage current mechanism is Schottky emission modified by tunneling, a different approach has to be used to evaluate the Schottky barrier height. They are important, for example, for 4.6 nm ZAZ MIM capacitors used in DRAM technology.
{"title":"Some Key Modifications of Theory Required to Understand the Leakage Current Mechanisms for MIM Capacitors used in Dram Technology","authors":"W. Lau","doi":"10.1109/CSTIC49141.2020.9282564","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282564","url":null,"abstract":"Two important key modifications of theory of leakage current mechanisms for MIM capacitors will be proposed. The first modification is the proposal of a new unified theory for the image force dielectric constant used in the Schottky emission and Poole-Frenkel equations. The second modification is that when the leakage current mechanism is Schottky emission modified by tunneling, a different approach has to be used to evaluate the Schottky barrier height. They are important, for example, for 4.6 nm ZAZ MIM capacitors used in DRAM technology.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"42 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80822269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282536
Kainan Wang, Yingxuan Zhu, C.-Z. Chen
In artificial neural network (ANN), the basic perceptron algorithm plays a significant role in supervised machine learning due to its simple structure. Though it cannot solve some non-linear problems like XOR, however, this feature offers a possibility to build perceptron on a hardware design. Due to high efficiency and defect tolerant, researchers have proposed some ANN accelerators with complicated memory units and specific registers. In this work, we focus on a simplest perceptron and accomplish its hardware design using Verilog HDL. The design module includes one core for learning and four memory units for storing the training data. The study shows that the proximate floating -point simulation of the simple perceptron design can replace the defect-tolerant registers and the simple memory units, thus to make the accelerator a tiny scale, it also demonstrates that the accuracy rate on test set achieved at 98% and the total area cost is only 0.0078 mm2.
{"title":"Perceptron Algorithm and Its Verilog Design","authors":"Kainan Wang, Yingxuan Zhu, C.-Z. Chen","doi":"10.1109/CSTIC49141.2020.9282536","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282536","url":null,"abstract":"In artificial neural network (ANN), the basic perceptron algorithm plays a significant role in supervised machine learning due to its simple structure. Though it cannot solve some non-linear problems like XOR, however, this feature offers a possibility to build perceptron on a hardware design. Due to high efficiency and defect tolerant, researchers have proposed some ANN accelerators with complicated memory units and specific registers. In this work, we focus on a simplest perceptron and accomplish its hardware design using Verilog HDL. The design module includes one core for learning and four memory units for storing the training data. The study shows that the proximate floating -point simulation of the simple perceptron design can replace the defect-tolerant registers and the simple memory units, thus to make the accelerator a tiny scale, it also demonstrates that the accuracy rate on test set achieved at 98% and the total area cost is only 0.0078 mm2.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"52 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77804472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282419
S. Lin, Frank Yong
As a process node is getting smaller, the types of failure mechanisms are increasing. New EFA technologies and methods are constantly development. One of the main changes EFA analyses is an enhancement of dynamic EFA in circuit failed in functional test. We propose a technique for advanced Electrical Failure Analysis (EFA) tool with a Picosecond Imaging Circuit Analysis (PICA) detector with enhanced sensitivity for discussing Time Resolved Emission (TRE). The key applications where the time-resolved imaging capability is very effective in reducing the debug time and improving the understanding the failure behaviors of VLSI chip for fault characteristics
{"title":"Low Voltage Time-Resolved Emission (TRE) Measurements of VLSI Circuit","authors":"S. Lin, Frank Yong","doi":"10.1109/CSTIC49141.2020.9282419","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282419","url":null,"abstract":"As a process node is getting smaller, the types of failure mechanisms are increasing. New EFA technologies and methods are constantly development. One of the main changes EFA analyses is an enhancement of dynamic EFA in circuit failed in functional test. We propose a technique for advanced Electrical Failure Analysis (EFA) tool with a Picosecond Imaging Circuit Analysis (PICA) detector with enhanced sensitivity for discussing Time Resolved Emission (TRE). The key applications where the time-resolved imaging capability is very effective in reducing the debug time and improving the understanding the failure behaviors of VLSI chip for fault characteristics","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90219275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282565
M. Hang, Lili Jia, Fang Li, Jun Huang, Wenyan Liu
With the development of integrated circuit technology, the application of new materials and new process in integrated circuit process also brings new challenges. This paper reported some improvement research for round convex residue (oxide residue) in dual gate layer which may result in low yield. Improvement research include change wet clean process condition before thick gate oxidation, add wet clean process post thick gate oxidation, change lithography process conditions and change thick gate growth mode. The results show that oxide residue can be effectively removed by these methods, and which can improve yield about 20%.
{"title":"Improvement Research of Round Convex Residue in Dual Gate Layer","authors":"M. Hang, Lili Jia, Fang Li, Jun Huang, Wenyan Liu","doi":"10.1109/CSTIC49141.2020.9282565","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282565","url":null,"abstract":"With the development of integrated circuit technology, the application of new materials and new process in integrated circuit process also brings new challenges. This paper reported some improvement research for round convex residue (oxide residue) in dual gate layer which may result in low yield. Improvement research include change wet clean process condition before thick gate oxidation, add wet clean process post thick gate oxidation, change lithography process conditions and change thick gate growth mode. The results show that oxide residue can be effectively removed by these methods, and which can improve yield about 20%.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"52 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89813523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282401
Lin Chen, Zhufei Chu
Memristive circuits natively perform material implication (IMPLY) operation, IMPLY together with FALSE (by setting a signal of the IMPLY to ‘0’) is a complete set of operators. As one promising approach for in-memory computing, memristive circuits allow for both data-storing and logic-operation. Logic synthesis is essential for the design of emerging technologies. Instead of using well-known logic synthesis data structures to derive an implication logic network, the paper presents an exact synthesis method to obtain an optimal IMPLY logic network, which is a dedicated homogeneous network by using IMPLY as its only logic primitives. By synthesizing all the 256 three-input Boolean functions, the experimental results show 74 of these have better size compared with one-to-one mapping from optimal And-Inverter Graph (AIG) representations.
{"title":"Towards Optimal Logic Representations for Implication-Based Memristive Circuits","authors":"Lin Chen, Zhufei Chu","doi":"10.1109/CSTIC49141.2020.9282401","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282401","url":null,"abstract":"Memristive circuits natively perform material implication (IMPLY) operation, IMPLY together with FALSE (by setting a signal of the IMPLY to ‘0’) is a complete set of operators. As one promising approach for in-memory computing, memristive circuits allow for both data-storing and logic-operation. Logic synthesis is essential for the design of emerging technologies. Instead of using well-known logic synthesis data structures to derive an implication logic network, the paper presents an exact synthesis method to obtain an optimal IMPLY logic network, which is a dedicated homogeneous network by using IMPLY as its only logic primitives. By synthesizing all the 256 three-input Boolean functions, the experimental results show 74 of these have better size compared with one-to-one mapping from optimal And-Inverter Graph (AIG) representations.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"15 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89879038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282510
Xiaoxu Kang, Ruoxi Shen, Xiaolan Zhong
Graphene Oxide (GO) has the two-dimensional (2D) layered structure with lots of oxygen containing groups. In this work, GO thin film was coated on substrate with carefully prepared GO dispersion. The GO film was thermally treated by different process condition, and characterized by surface analysis methods to get the optimized process condition. After that, GO based capacitive humidity sensor structure was designed and fabricated, and the capacitance of the sensor structure was increased about seven times from ~22.5% RH% to ~85% RH%, which shows excellent sensitivity performance.
{"title":"Surface Analysis and Post Thermal Treatment Process Optimization of Graphene Oxide Thin Film for Humidity Sensor Application","authors":"Xiaoxu Kang, Ruoxi Shen, Xiaolan Zhong","doi":"10.1109/CSTIC49141.2020.9282510","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282510","url":null,"abstract":"Graphene Oxide (GO) has the two-dimensional (2D) layered structure with lots of oxygen containing groups. In this work, GO thin film was coated on substrate with carefully prepared GO dispersion. The GO film was thermally treated by different process condition, and characterized by surface analysis methods to get the optimized process condition. After that, GO based capacitive humidity sensor structure was designed and fabricated, and the capacitance of the sensor structure was increased about seven times from ~22.5% RH% to ~85% RH%, which shows excellent sensitivity performance.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"126 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88133498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282444
Yu Shirui, Cheng Yanpeng, Wan Dan, Deng Guogui, Huang Yidan
Hole layer mask with small corner-to-corner space is usually been limited by mask rule check in OPC. For 28nm and below node, via or contact layer square pattern edges need not fragmentation in general. This paper investigates fragmentations of hole layer square mask with small corner-to-corner space to make contour critical dimension on target. The potential risks of fragmentations and limit conditions of fragments movement are also been discussed. Comparison of square pattern mask with or without fragments ADI results is also been studied in this paper.
{"title":"Fragmentation of Square Pattern Mask with Small Corner-to-Corner Space","authors":"Yu Shirui, Cheng Yanpeng, Wan Dan, Deng Guogui, Huang Yidan","doi":"10.1109/CSTIC49141.2020.9282444","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282444","url":null,"abstract":"Hole layer mask with small corner-to-corner space is usually been limited by mask rule check in OPC. For 28nm and below node, via or contact layer square pattern edges need not fragmentation in general. This paper investigates fragmentations of hole layer square mask with small corner-to-corner space to make contour critical dimension on target. The potential risks of fragmentations and limit conditions of fragments movement are also been discussed. Comparison of square pattern mask with or without fragments ADI results is also been studied in this paper.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"23 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86841130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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