Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282467
Jin-Goo Park, Heon-Yul Ryu, Tae-Gon Kim, Nagendra Prasad Yerriboina, Y. Wada, Satomi Hamada, Hirokuni Hiyama
Corrosion inhibitor plays a key role during Chemical mechanical planarization (CMP) of metal surfaces during semiconductor processing. Strong metal-inhibitor passivation formation during the CMP process and its easy removal during post-CMP cleaning are highly required. However, there are no studies available explaining this phenomenon. In this work, passivation changes of copper (Cu) and cobalt (Co) surfaces during CMP and post CMP cleaning by adsorption and removal of benzotriazole (BTA), was characterized using a new sequential electrochemical impedance spectroscopy (EIS) technique. It was found that stable Cu/Co-BTA complex (metal-inhibitor passivation) was formed when each metal surface was exposed to BTA solution. However, it was found that adsorbed BTA on Co surface could be removed just by de-ionized (DI) water rinsing while BTA on Cu surface was not removed.
{"title":"The Adsorption and Removal of Corrosion Inhibitors During Metal CMP","authors":"Jin-Goo Park, Heon-Yul Ryu, Tae-Gon Kim, Nagendra Prasad Yerriboina, Y. Wada, Satomi Hamada, Hirokuni Hiyama","doi":"10.1109/CSTIC49141.2020.9282467","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282467","url":null,"abstract":"Corrosion inhibitor plays a key role during Chemical mechanical planarization (CMP) of metal surfaces during semiconductor processing. Strong metal-inhibitor passivation formation during the CMP process and its easy removal during post-CMP cleaning are highly required. However, there are no studies available explaining this phenomenon. In this work, passivation changes of copper (Cu) and cobalt (Co) surfaces during CMP and post CMP cleaning by adsorption and removal of benzotriazole (BTA), was characterized using a new sequential electrochemical impedance spectroscopy (EIS) technique. It was found that stable Cu/Co-BTA complex (metal-inhibitor passivation) was formed when each metal surface was exposed to BTA solution. However, it was found that adsorbed BTA on Co surface could be removed just by de-ionized (DI) water rinsing while BTA on Cu surface was not removed.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"29 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87022152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282490
Toru Fujimori
Extreme ultraviolet (EUV) lithography is almost ready for realize 7nm generation manufacturing and beyond. A key factor for the realization of EUV lithography is the choices of EUV resist materials that are capable of resolving below 15nm half pitch with high sensitivity. However, the performances of EUV resist materials are still not enough for the true HVM requirements. One critical issue is ‘Chemical stochastic’, which will be become ‘defectivity’. We report herein how to improve ‘Chemical Stochastic’.
{"title":"How to Improve ‘Chemical Stochastic’ in EUV Lithography ?","authors":"Toru Fujimori","doi":"10.1109/CSTIC49141.2020.9282490","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282490","url":null,"abstract":"Extreme ultraviolet (EUV) lithography is almost ready for realize 7nm generation manufacturing and beyond. A key factor for the realization of EUV lithography is the choices of EUV resist materials that are capable of resolving below 15nm half pitch with high sensitivity. However, the performances of EUV resist materials are still not enough for the true HVM requirements. One critical issue is ‘Chemical stochastic’, which will be become ‘defectivity’. We report herein how to improve ‘Chemical Stochastic’.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"28 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87596088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282398
Xiao-bo Ren, Wei Xiong, Hualun Chen
P+ to Pwell and N+ to Nwell leakage are the most basic leakage components in VLSI circuit and had been received many technologies to be reduced. In each technology, trade off must be made to keep low P+ to Pwell or N+ to Nwell leakage while do not degrade the other characteristic of the circuit. We found that a thin SIN layer post STI Liner OX was able to reduce the B project range at the interface of Active and STI OX, hence reduce P+ to Pwell leakage in Ultro Low Leakage Huge Volume SRAM. As a result, increased P+ diffusion resistance caused by reducing P+ implant energy can be avoided.
{"title":"Improved Standby Leakage of Huge Volume SRAM by Thin SIN Film of STI Liner","authors":"Xiao-bo Ren, Wei Xiong, Hualun Chen","doi":"10.1109/CSTIC49141.2020.9282398","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282398","url":null,"abstract":"P+ to Pwell and N+ to Nwell leakage are the most basic leakage components in VLSI circuit and had been received many technologies to be reduced. In each technology, trade off must be made to keep low P+ to Pwell or N+ to Nwell leakage while do not degrade the other characteristic of the circuit. We found that a thin SIN layer post STI Liner OX was able to reduce the B project range at the interface of Active and STI OX, hence reduce P+ to Pwell leakage in Ultro Low Leakage Huge Volume SRAM. As a result, increased P+ diffusion resistance caused by reducing P+ implant energy can be avoided.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"39 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88273913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282554
Jun Liu, Lei Zhang, Jianmin Wang, Qinghua Liu, Di Lou
As 8 inch fab moves to 0.13µm process and beyond, backend Aluminum line width also shrinks to 0.14µm or below with much tightened overlay spec. Low temperature Al sputter process shows very smooth metal surface, which significantly improves overly mark recognition. Thus cold Al is preferred. Meanwhile Cold Al electromigration lifetime is worse than that of hot Al due to smaller aluminum grain size. Cold Al EM must be well controlled for production. In this article, we study the backend HDP oxide deposition temperature and its influence on Metal-1 EM lifetime based on fab 0.13µm process, and a strong correlation has been found. From which, a suitable HDP temp control can be set for cold Al mass production.
{"title":"A Study of Low Temperature Al Sputter Process Electromigration Lifetime","authors":"Jun Liu, Lei Zhang, Jianmin Wang, Qinghua Liu, Di Lou","doi":"10.1109/CSTIC49141.2020.9282554","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282554","url":null,"abstract":"As 8 inch fab moves to 0.13µm process and beyond, backend Aluminum line width also shrinks to 0.14µm or below with much tightened overlay spec. Low temperature Al sputter process shows very smooth metal surface, which significantly improves overly mark recognition. Thus cold Al is preferred. Meanwhile Cold Al electromigration lifetime is worse than that of hot Al due to smaller aluminum grain size. Cold Al EM must be well controlled for production. In this article, we study the backend HDP oxide deposition temperature and its influence on Metal-1 EM lifetime based on fab 0.13µm process, and a strong correlation has been found. From which, a suitable HDP temp control can be set for cold Al mass production.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"90 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83898879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282545
Yijiang Shen, Xiaopeng Wang
In this paper, a distance level-set regularized reformulation of mask synthesis is developed to secure a simple and straightforward construction of the narrow band and provide the nonlinear diffusion term for implicit difference schemes. Subsequently, the mask update is performed only in the vicinity of the zero level set thereby reducing optimization dimensionality; moreover, the semi-implicit discretization is applied to circumvent the stability constraints enabling sufficiently large stepsize improving convergence with much less iteration numbers. Additive operator splits the mask update with respect to coordinate axes to solving multiple comparatively small scale linear systems of equations with Thomas method. Simulation results merit the superiority of the proposed approach with improved convergence by overcoming the stability constraints and reduced optimization dimensionality.
{"title":"Narrow-Band Mask Synthesis with Semi-Implicit Difference","authors":"Yijiang Shen, Xiaopeng Wang","doi":"10.1109/CSTIC49141.2020.9282545","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282545","url":null,"abstract":"In this paper, a distance level-set regularized reformulation of mask synthesis is developed to secure a simple and straightforward construction of the narrow band and provide the nonlinear diffusion term for implicit difference schemes. Subsequently, the mask update is performed only in the vicinity of the zero level set thereby reducing optimization dimensionality; moreover, the semi-implicit discretization is applied to circumvent the stability constraints enabling sufficiently large stepsize improving convergence with much less iteration numbers. Additive operator splits the mask update with respect to coordinate axes to solving multiple comparatively small scale linear systems of equations with Thomas method. Simulation results merit the superiority of the proposed approach with improved convergence by overcoming the stability constraints and reduced optimization dimensionality.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"77 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83976908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/cstic49141.2020.9282452
C. Sun
With the advancement of VLSI technology and the continuous development of metal oxide semiconductor field effect transistors (MOSFET), process nodes are constantly improving, integrated circuit package precision requirements are also increasing, and the difficulty of controlling bonding quality and reliability is increasing, the crystal of the pad on the surface of the aluminum (Al) pad has become a real problem in the semiconductor industry. When doing a shear test, this kind of defect will cause the package to fail[Fig. 1]. The essay proposes that different products have different cover transmission rate, which will affect the degree of pad crystal a degree of influence of different cover T/R on the crystal of the pad and the solution to provide a strong evidence for the subsequent solution of the pad crystal problem. The experimental results show that the product cover T/R is the smaller, the greater the chances crystal of the pad.
{"title":"Investigation of Bond PAD Crystal Defect for Different Cover Transmission Rate","authors":"C. Sun","doi":"10.1109/cstic49141.2020.9282452","DOIUrl":"https://doi.org/10.1109/cstic49141.2020.9282452","url":null,"abstract":"With the advancement of VLSI technology and the continuous development of metal oxide semiconductor field effect transistors (MOSFET), process nodes are constantly improving, integrated circuit package precision requirements are also increasing, and the difficulty of controlling bonding quality and reliability is increasing, the crystal of the pad on the surface of the aluminum (Al) pad has become a real problem in the semiconductor industry. When doing a shear test, this kind of defect will cause the package to fail[Fig. 1]. The essay proposes that different products have different cover transmission rate, which will affect the degree of pad crystal a degree of influence of different cover T/R on the crystal of the pad and the solution to provide a strong evidence for the subsequent solution of the pad crystal problem. The experimental results show that the product cover T/R is the smaller, the greater the chances crystal of the pad.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"16 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89344371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282602
Han Xiaojing
This paper introduces a new kind of calibration structure for MOSFET gate oxide capacitance. This new calibration structure is used to remove the parasitic interconnect capacitance from the gate oxide capacitor when calculate the gate oxide capacitance. By processing measured data of gate oxide capacitance and this new capacitance calibration structure, we can get the value of gate oxide capacitance more accurately, which provides a more accurate guarantee for SPICE model and circuit design.
{"title":"One New Calibration Structure of Mosfet Gate Oxide Capacitor","authors":"Han Xiaojing","doi":"10.1109/CSTIC49141.2020.9282602","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282602","url":null,"abstract":"This paper introduces a new kind of calibration structure for MOSFET gate oxide capacitance. This new calibration structure is used to remove the parasitic interconnect capacitance from the gate oxide capacitor when calculate the gate oxide capacitance. By processing measured data of gate oxide capacitance and this new capacitance calibration structure, we can get the value of gate oxide capacitance more accurately, which provides a more accurate guarantee for SPICE model and circuit design.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"22 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88485148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282435
Fengjia Pan, Hungling Chen, Yin Long, Kai Wang, Hao Guo
A novel inspection method is proposed for checking the integration of FEOL (front-end-of-line) device fabrication. As the designed electron-beam (as e-beam in the following text) inspection methodology applies to the last step of FEOL device and prior to MEOL interconnection fabrication, the capability of both voltage contrast and physical feature detection discovered the surface and underneath defects in the very narrow space of Nickel Silicide formation. Experiments showed the variation of multiplex parameters involving poly critical dimension, spacer and SMT film thickness with dry, wet, furnace and plasma ashing processes would lead to invisible change of Nickel Silicide formation and can be detected by the designed inspection. Defect count would be high while those majority pre-steps process windows being marginal. After all, the cumulative effect would lead to electrical failures of the device.
{"title":"Investigation and Discovery of the Integration of FEOL Process by Electron Beam Inspections","authors":"Fengjia Pan, Hungling Chen, Yin Long, Kai Wang, Hao Guo","doi":"10.1109/CSTIC49141.2020.9282435","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282435","url":null,"abstract":"A novel inspection method is proposed for checking the integration of FEOL (front-end-of-line) device fabrication. As the designed electron-beam (as e-beam in the following text) inspection methodology applies to the last step of FEOL device and prior to MEOL interconnection fabrication, the capability of both voltage contrast and physical feature detection discovered the surface and underneath defects in the very narrow space of Nickel Silicide formation. Experiments showed the variation of multiplex parameters involving poly critical dimension, spacer and SMT film thickness with dry, wet, furnace and plasma ashing processes would lead to invisible change of Nickel Silicide formation and can be detected by the designed inspection. Defect count would be high while those majority pre-steps process windows being marginal. After all, the cumulative effect would lead to electrical failures of the device.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"19 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78578413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282578
P. Zhou, Y. Zhu, Tao Sun
The mechanical removal mechanism of silicon carbide crystal is investigated by Molecular Dynamics (MD) simulation in a fixed abrasive polishing. Special attention is paid to the effect of the sub-nano scratching depth on the mechanical removal behavior. It was found that only the amorphous phase transition occurs in SiC. The temperature, subsurface damage depth and removal rate of SiC substrates increase with the increase of scratching depth. Furthermore, the result shows that the scratching force increases as the scratching depth increases.
{"title":"Molecular Dynamics Study on Sub-Nanoscale Removal Mechanism of 3C-SIC in a Fixed Abrasive Polishing","authors":"P. Zhou, Y. Zhu, Tao Sun","doi":"10.1109/CSTIC49141.2020.9282578","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282578","url":null,"abstract":"The mechanical removal mechanism of silicon carbide crystal is investigated by Molecular Dynamics (MD) simulation in a fixed abrasive polishing. Special attention is paid to the effect of the sub-nano scratching depth on the mechanical removal behavior. It was found that only the amorphous phase transition occurs in SiC. The temperature, subsurface damage depth and removal rate of SiC substrates increase with the increase of scratching depth. Furthermore, the result shows that the scratching force increases as the scratching depth increases.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"18 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74039829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-26DOI: 10.1109/CSTIC49141.2020.9282478
Liping Peng, Hong Li, Tiantuo Sun, Xing Gao, Qin Sun
Polysilazane (PSZ) curing has been introduced for 19nm NAND Flash to ensure void free Shallow Trench Isolation (STI) gap fill. PSZ film was converted into oxide mainly depending on temperature and water vapor. The high temperature PSZ curing would give rise to Si dislocation and PSZ crack. However, lowering curing temperature would lead to an insufficient conversion of PSZ film and even generate voids. As a result, wet oxidation was utilized between curing 1 and curing 2 to improve conversion rate of PSZ film. The TEM images showed good gap fill performance of PSZ curing by using low temperature/wet oxidation method.
{"title":"Study of Shallow Trench Isolation Gap Fill for 19nm NAND Flash","authors":"Liping Peng, Hong Li, Tiantuo Sun, Xing Gao, Qin Sun","doi":"10.1109/CSTIC49141.2020.9282478","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282478","url":null,"abstract":"Polysilazane (PSZ) curing has been introduced for 19nm NAND Flash to ensure void free Shallow Trench Isolation (STI) gap fill. PSZ film was converted into oxide mainly depending on temperature and water vapor. The high temperature PSZ curing would give rise to Si dislocation and PSZ crack. However, lowering curing temperature would lead to an insufficient conversion of PSZ film and even generate voids. As a result, wet oxidation was utilized between curing 1 and curing 2 to improve conversion rate of PSZ film. The TEM images showed good gap fill performance of PSZ curing by using low temperature/wet oxidation method.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"29 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85185861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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