Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583280
Jie-Fei Zhu, Hong Jin, Min-bo Zhou, Xin-Ping Zhang
In the present study, several conventional dicarboxylic acids (e.g., oxalic acid, malonic acid, succinic acid, adipic acid and glutaric acid) are selected to modify electrically conductive adhesives (ECAs) filled with micro-sized silver flakes, and so-designed ECAs have been prepared. In so-designed and prepared ECAs, dicarboxylic acids take in effect through in-situ replacement of surfactant so as to improve the contact of silver flakes and their distribution and consequently to enhance the electrical property of the ECAs. The curing behavior of the prepared ECAs with adding different dicarboxylic acids is characterized by a differential scanning calorimeter, the bulk resistivity of the ECAs is evaluated by a high-speed programmable micro-ohmmeter and the morphologies of the ECAs are analyzed by SEM. The results show that adipic acid can be a very good additive not only facilitating the curing with an obvious increase of the reaction heat, but also improving the electrical property of the ECAs with a significant reduction of the bulk resistivity.
{"title":"Electrical property of electrically conductive adhesives filled with micro-sized Ag flakes and modified by dicarboxylic acids","authors":"Jie-Fei Zhu, Hong Jin, Min-bo Zhou, Xin-Ping Zhang","doi":"10.1109/ICEPT.2016.7583280","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583280","url":null,"abstract":"In the present study, several conventional dicarboxylic acids (e.g., oxalic acid, malonic acid, succinic acid, adipic acid and glutaric acid) are selected to modify electrically conductive adhesives (ECAs) filled with micro-sized silver flakes, and so-designed ECAs have been prepared. In so-designed and prepared ECAs, dicarboxylic acids take in effect through in-situ replacement of surfactant so as to improve the contact of silver flakes and their distribution and consequently to enhance the electrical property of the ECAs. The curing behavior of the prepared ECAs with adding different dicarboxylic acids is characterized by a differential scanning calorimeter, the bulk resistivity of the ECAs is evaluated by a high-speed programmable micro-ohmmeter and the morphologies of the ECAs are analyzed by SEM. The results show that adipic acid can be a very good additive not only facilitating the curing with an obvious increase of the reaction heat, but also improving the electrical property of the ECAs with a significant reduction of the bulk resistivity.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"45 1","pages":"923-926"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89702768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583354
Jiang Xie, Q. Shi, Yue Gao
This paper introduces an evaluation method of integrated circuit port protection structure burn-out mechanism basing on transmission line pulse test (TLP). Based on the analysis of a variety of typical ESD protection circuit structures of integrated circuit, the design procedure of TLP test scheme is provided. By establishing functional relation between I/V characteristic curves and the ESD damage failure of protection circuit, the level and consequence of integrated circuit ESD failure can be quantified precisely, the root causes also can be confirmed. With a failure analysis case of a typical clamp protection structure of 0.18μm process verifies the feasibility of the technique.
{"title":"Integrated circuit ESD protection structure failure analysis based on TLP technique","authors":"Jiang Xie, Q. Shi, Yue Gao","doi":"10.1109/ICEPT.2016.7583354","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583354","url":null,"abstract":"This paper introduces an evaluation method of integrated circuit port protection structure burn-out mechanism basing on transmission line pulse test (TLP). Based on the analysis of a variety of typical ESD protection circuit structures of integrated circuit, the design procedure of TLP test scheme is provided. By establishing functional relation between I/V characteristic curves and the ESD damage failure of protection circuit, the level and consequence of integrated circuit ESD failure can be quantified precisely, the root causes also can be confirmed. With a failure analysis case of a typical clamp protection structure of 0.18μm process verifies the feasibility of the technique.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"6 1","pages":"1267-1271"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86853260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583203
Jian Gu, Y. Lei, Jian Lin, H. Fu, Zhong-wei Wu
the reliability of solder joint under drop impact is a crucial research area due to the smaller and higher density. The test standard for board level has been published by JEDEC in detail. Based on JEDEC board level drop test standard, the square board with four symmetry component is designed in this paper. The structure size of test board is 0.5mm×121mm×121mm. The distance of the center component to the center of test board is 15mm. The first six modal frequency is 23.56Hz, 136.37Hz, 138.53Hz, 165.98Hz, 346.35Hz and 394.56Hz respectively. This Design benefits for the board level drop life of solder joint statistics analysis. And the 0.5mm thickness design can be used as replacement test board to analyze the failure mechanism of solder joint under relative high drop impact level.
{"title":"Design of the printed circuit board for board level drop impact base on the JEDEC standard","authors":"Jian Gu, Y. Lei, Jian Lin, H. Fu, Zhong-wei Wu","doi":"10.1109/ICEPT.2016.7583203","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583203","url":null,"abstract":"the reliability of solder joint under drop impact is a crucial research area due to the smaller and higher density. The test standard for board level has been published by JEDEC in detail. Based on JEDEC board level drop test standard, the square board with four symmetry component is designed in this paper. The structure size of test board is 0.5mm×121mm×121mm. The distance of the center component to the center of test board is 15mm. The first six modal frequency is 23.56Hz, 136.37Hz, 138.53Hz, 165.98Hz, 346.35Hz and 394.56Hz respectively. This Design benefits for the board level drop life of solder joint statistics analysis. And the 0.5mm thickness design can be used as replacement test board to analyze the failure mechanism of solder joint under relative high drop impact level.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"64 1","pages":"588-591"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85279358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583096
Dandong Ge, Xue Ming, Wenjie Shen, Zhao Yun
Moisture absorption of epoxy mold compounds (EMC) from IC packages is a serious concern especially for their reliability performance during stress tests. Numerous studies reported the popcorn cracking delamination due to moisture absorption of packaging materials during solder reflow [I]. Though no pop-corn delamination or other EMC to die pad delamination happened at time zero, current leakage may be still observed even if moisture absorption properties changed slightly. This paper reports properties, especially moisture absorption properties, of EMCs that were characterized to identify the failure causes. Also described is a new methodology to detect the moisture absorption amount at EMC to die pad and EMC to leadframe interfaces. To differentiate the moisture absorption amount between EMC and interfaces will give failure analysis a great clue to find the failure root cause. EMCs with same resin type but different resin concentration were selected to build same type of packages with different die sizes. Moisture absorption and desorption tests were conducted to characterize the moisture absorption behaviors of EMC in packages. Scanning Acoustic Tomography (SAT) and Electric test were recorded at Time zero and various stress test durations. Results showed that packages with higher resin content of EMC are prone to current leakage. In order to prevent the moisture absorption related failure, resin contents need to be controlled and monitored carefully. Furthermore, package design, e.g. die size and lead to die pad distance etc. need to be optimized together with acceptable EMC resin specification for production.
{"title":"Effect of moisture related properties of mold compound on the reliability of power packages","authors":"Dandong Ge, Xue Ming, Wenjie Shen, Zhao Yun","doi":"10.1109/ICEPT.2016.7583096","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583096","url":null,"abstract":"Moisture absorption of epoxy mold compounds (EMC) from IC packages is a serious concern especially for their reliability performance during stress tests. Numerous studies reported the popcorn cracking delamination due to moisture absorption of packaging materials during solder reflow [I]. Though no pop-corn delamination or other EMC to die pad delamination happened at time zero, current leakage may be still observed even if moisture absorption properties changed slightly. This paper reports properties, especially moisture absorption properties, of EMCs that were characterized to identify the failure causes. Also described is a new methodology to detect the moisture absorption amount at EMC to die pad and EMC to leadframe interfaces. To differentiate the moisture absorption amount between EMC and interfaces will give failure analysis a great clue to find the failure root cause. EMCs with same resin type but different resin concentration were selected to build same type of packages with different die sizes. Moisture absorption and desorption tests were conducted to characterize the moisture absorption behaviors of EMC in packages. Scanning Acoustic Tomography (SAT) and Electric test were recorded at Time zero and various stress test durations. Results showed that packages with higher resin content of EMC are prone to current leakage. In order to prevent the moisture absorption related failure, resin contents need to be controlled and monitored carefully. Furthermore, package design, e.g. die size and lead to die pad distance etc. need to be optimized together with acceptable EMC resin specification for production.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"20 1","pages":"88-93"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87427604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583108
R. Qian, Y. Liu
This paper studies the traditional thin and large die pick up process by finite element simulation. A complicated transient dynamic model is developed to simulate the die pick up process by ANSYS/LS-DYNA. Multiple 3D contact pairs are set up between collet and die, die and tape, tape and die holder, tape and eject pins in simulation. The modeling of the adhesive de-bonding process is critical to the thin/large die crack. A de-bonding criterion for die surface and tape is studied to show the die separation process from tape. A transient dynamic process of die pick up from tape is simulated. Die tensile stress is recorded during the whole process. Parametric models with different die sizes, different collet dimensions, different eject pin dimensions, different tape materials are investigated. Through the simulation, we wish to understand better how the traditional die pick up process could impact the die stress and its reliability.
{"title":"Thin and large die assembly pick up process optimization by dynamic modeling","authors":"R. Qian, Y. Liu","doi":"10.1109/ICEPT.2016.7583108","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583108","url":null,"abstract":"This paper studies the traditional thin and large die pick up process by finite element simulation. A complicated transient dynamic model is developed to simulate the die pick up process by ANSYS/LS-DYNA. Multiple 3D contact pairs are set up between collet and die, die and tape, tape and die holder, tape and eject pins in simulation. The modeling of the adhesive de-bonding process is critical to the thin/large die crack. A de-bonding criterion for die surface and tape is studied to show the die separation process from tape. A transient dynamic process of die pick up from tape is simulated. Die tensile stress is recorded during the whole process. Parametric models with different die sizes, different collet dimensions, different eject pin dimensions, different tape materials are investigated. Through the simulation, we wish to understand better how the traditional die pick up process could impact the die stress and its reliability.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"30 1","pages":"147-152"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82993598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583377
Guangjie Yuan, Ning Wang, Shirong Huang, Johan Liu
Atomic layer deposition (ALD) and atomic layer etching (ALE) are two important techniques in the semiconductor processing, which focus ultra-thin film deposition and etching, respectively. Both of them have the self-limiting surface behavior, and could realize the atomic-scale fidelity in the deposition and etching processes. Unlike traditional chemical vapor deposition (CVD) and physical vapor deposition (PVD), ALD has good step coverage, atomic-scale thickness controllability, and composition uniformity at low growth temperature. Compared with traditional continuous-wave plasma etching, ALE has smooth surface, excellent depth uniformity and atomic-scale thickness controllability. In this review, their fundamental and applications have been discussed.
{"title":"A brief overview of atomic layer deposition and etching in the semiconductor processing","authors":"Guangjie Yuan, Ning Wang, Shirong Huang, Johan Liu","doi":"10.1109/ICEPT.2016.7583377","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583377","url":null,"abstract":"Atomic layer deposition (ALD) and atomic layer etching (ALE) are two important techniques in the semiconductor processing, which focus ultra-thin film deposition and etching, respectively. Both of them have the self-limiting surface behavior, and could realize the atomic-scale fidelity in the deposition and etching processes. Unlike traditional chemical vapor deposition (CVD) and physical vapor deposition (PVD), ALD has good step coverage, atomic-scale thickness controllability, and composition uniformity at low growth temperature. Compared with traditional continuous-wave plasma etching, ALE has smooth surface, excellent depth uniformity and atomic-scale thickness controllability. In this review, their fundamental and applications have been discussed.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"27 1","pages":"1365-1368"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81004928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583240
G. Wang, L. Yin, Z. Yao, Jinzhao Wang
The effects of thermal aging and electromigration on the tensile strength and microstructure of SnAgCu micro-interconnection solder joints with different volume were discussed in this paper. The experimental results show that isothermal aging results in coarsening of the microstructure in the solder joint, and electromigration leads to micro-hole or micro-crack in the cathode interface, which bring about obvious degradation of tensile strength to the joints. The smaller volume of the micro-interconnection joint is, the less degradation of tensile strength for it, this is caused by the increasing mechanical constraint in the solder joints.
{"title":"Effects of thermal aging and electromigration on tensile strength of SnAgCu solder joints with different volume","authors":"G. Wang, L. Yin, Z. Yao, Jinzhao Wang","doi":"10.1109/ICEPT.2016.7583240","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583240","url":null,"abstract":"The effects of thermal aging and electromigration on the tensile strength and microstructure of SnAgCu micro-interconnection solder joints with different volume were discussed in this paper. The experimental results show that isothermal aging results in coarsening of the microstructure in the solder joint, and electromigration leads to micro-hole or micro-crack in the cathode interface, which bring about obvious degradation of tensile strength to the joints. The smaller volume of the micro-interconnection joint is, the less degradation of tensile strength for it, this is caused by the increasing mechanical constraint in the solder joints.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"11 1","pages":"753-756"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90012322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583119
Yougen Hu, T. Zhao, Pengli Zhu, Xianwen Liang, Yu Zhu, H. Su, R. Sun, C. Wong
Flexible electronics has emerged as an independent field and matured over the past decades due to they can provide a lot of benefits as compared with traditional rigid printed circuit boards, such as better durability, lighter weight, higher space efficiency, and improved comfort. Graphene-based electronics provide new opportunities for flexible electronics because of their superior properties including high electrical conductivity, high mechanical flexibility, high carrier mobility, and so forth. In this work, a water-dispersible graphene paste (WGP) was used as raw materials to fabricate flexible conductive patterns and films on various substrates. The water dispersions have noteworthy advantages over those obtained in organic solvents, such as low cost, absence of solvent toxicity and capacity for green chemistry compatibility with hydrophilic substrates, also avoiding post-reduction of graphene oxide (GO) to obtain electrical conductivity. The microstructures and rheological properties of the WGP were firstly studied. Then, the WGP with a high concentration of 20 mg mL-1 was directly printed on flexible substrates such as paper and PET film by a simple and low-cost stencil printing method to obtain various printed patterns. The electrical properties and durability of the printed patterns were investigated under different deformations such as bending and folding. The printed conductive patterns show a good conductivity and which can be visually demonstrated by lighting a LED bulb with a 3 V power source. The WGP conductive line on paper exhibits excellent electrical stability (~5% of relative change of resistance) after 1500 bending cycles. Moreover, after dilution of the WGP to a low concentration of 2 mg mL-1, it can be used to fabricate a flexible conductive film on PET substrate by spray coating technology, and which shows a low sheet resistance of ~14.33 Ω sq-1 at a thickness of ~5 μm. The results reveal that the WGP possess outstanding electronic properties and have great potential for the convenient fabrication of flexible and low-cost graphene based electronics on various substrates including flexible paper and plastics, by using a simple stencil printing method or spray printing technology.
{"title":"Water-dispersible graphene paste for flexible conductive patterns and films","authors":"Yougen Hu, T. Zhao, Pengli Zhu, Xianwen Liang, Yu Zhu, H. Su, R. Sun, C. Wong","doi":"10.1109/ICEPT.2016.7583119","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583119","url":null,"abstract":"Flexible electronics has emerged as an independent field and matured over the past decades due to they can provide a lot of benefits as compared with traditional rigid printed circuit boards, such as better durability, lighter weight, higher space efficiency, and improved comfort. Graphene-based electronics provide new opportunities for flexible electronics because of their superior properties including high electrical conductivity, high mechanical flexibility, high carrier mobility, and so forth. In this work, a water-dispersible graphene paste (WGP) was used as raw materials to fabricate flexible conductive patterns and films on various substrates. The water dispersions have noteworthy advantages over those obtained in organic solvents, such as low cost, absence of solvent toxicity and capacity for green chemistry compatibility with hydrophilic substrates, also avoiding post-reduction of graphene oxide (GO) to obtain electrical conductivity. The microstructures and rheological properties of the WGP were firstly studied. Then, the WGP with a high concentration of 20 mg mL-1 was directly printed on flexible substrates such as paper and PET film by a simple and low-cost stencil printing method to obtain various printed patterns. The electrical properties and durability of the printed patterns were investigated under different deformations such as bending and folding. The printed conductive patterns show a good conductivity and which can be visually demonstrated by lighting a LED bulb with a 3 V power source. The WGP conductive line on paper exhibits excellent electrical stability (~5% of relative change of resistance) after 1500 bending cycles. Moreover, after dilution of the WGP to a low concentration of 2 mg mL-1, it can be used to fabricate a flexible conductive film on PET substrate by spray coating technology, and which shows a low sheet resistance of ~14.33 Ω sq-1 at a thickness of ~5 μm. The results reveal that the WGP possess outstanding electronic properties and have great potential for the convenient fabrication of flexible and low-cost graphene based electronics on various substrates including flexible paper and plastics, by using a simple stencil printing method or spray printing technology.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"40 1","pages":"200-205"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90937147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583347
Lilin Liu, Kun Sun, Xiangying Zhang, Dongdong Teng, Gang Wang
Active matrix organic light emitting diode (AMOLED) displays based on amorphous indium-gallium-zinc oxide thin-film transistor (a-IGZO TFT) pixel circuit encounter problems as instability of threshold voltage (VT) under gate voltage bias-stress, the non-uniformity of mobility (μ) resulting from the large area TFT scale fabrication, and OLED degradation, etc. In this paper, we proposed a current compensation method. An improved current mirror is designed to overcome the channel length modulation effect of TFTs. The SPICE simulation results show that the proposed scheme not only effectively compensates for non-uniformity related with deviations of VT and μ in a-IGZO TFTs, the OLED degradation, but also guarantees a good linearity between IDATA and IOLED.
{"title":"An a-IGZO TFT pixel circuit with improved current mirror for active matrix organic light emitting diode displays","authors":"Lilin Liu, Kun Sun, Xiangying Zhang, Dongdong Teng, Gang Wang","doi":"10.1109/ICEPT.2016.7583347","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583347","url":null,"abstract":"Active matrix organic light emitting diode (AMOLED) displays based on amorphous indium-gallium-zinc oxide thin-film transistor (a-IGZO TFT) pixel circuit encounter problems as instability of threshold voltage (VT) under gate voltage bias-stress, the non-uniformity of mobility (μ) resulting from the large area TFT scale fabrication, and OLED degradation, etc. In this paper, we proposed a current compensation method. An improved current mirror is designed to overcome the channel length modulation effect of TFTs. The SPICE simulation results show that the proposed scheme not only effectively compensates for non-uniformity related with deviations of VT and μ in a-IGZO TFTs, the OLED degradation, but also guarantees a good linearity between IDATA and IOLED.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"43 4","pages":"1235-1239"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91472501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Size effect of solder balls on the interfacial reaction and microstructural evolution of BGA structure Cu/Sn3.0Ag0.5Cu-ball/Sn3.0Ag0.5Cu-paste/Cu joints during isothermal aging at 125 °C was systematically investigated. Results show that a large amount of bulk Cu6Sn5 phase distributes in the solder matrix of joints with large solder ball size, resulting from larger outflux Cu atoms from the interface to the molten solder and the low solubility of Cu in the solder matrix. The solder ball size has a significant influence on the interfacial Cu6Sn5 layer thickness at the Sn3.0Ag0.5Cu-ball/Cu interface, which increases with decreasing solder ball size, while showing less effect on that at the Sn3.0Ag0.5Cu-paste/Cu interface. The grain size of Ag3Sn phase in joints decreases with decreasing solder ball size. During isothermal aging, the growth of interfacial IMC layers at both Sn3.0Ag0.5Cu-ball/Cu and Sn3.0Ag0.5Cu-paste/Cu interfaces of joints is mainly controlled by bulk diffusion.
{"title":"Size effect on the interfacial reactions and microstructural evolution of Cu/Sn3.0Ag0.5Cu-ball/Sn3.0Ag0.5Cu-paste/Cu joints in flip-chip on BGA packaging","authors":"Jia-Qiang Huang, Min-bo Zhou, Wang-yun Li, Xin-Ping Zhang","doi":"10.1109/ICEPT.2016.7583298","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583298","url":null,"abstract":"Size effect of solder balls on the interfacial reaction and microstructural evolution of BGA structure Cu/Sn3.0Ag0.5Cu-ball/Sn3.0Ag0.5Cu-paste/Cu joints during isothermal aging at 125 °C was systematically investigated. Results show that a large amount of bulk Cu6Sn5 phase distributes in the solder matrix of joints with large solder ball size, resulting from larger outflux Cu atoms from the interface to the molten solder and the low solubility of Cu in the solder matrix. The solder ball size has a significant influence on the interfacial Cu6Sn5 layer thickness at the Sn3.0Ag0.5Cu-ball/Cu interface, which increases with decreasing solder ball size, while showing less effect on that at the Sn3.0Ag0.5Cu-paste/Cu interface. The grain size of Ag3Sn phase in joints decreases with decreasing solder ball size. During isothermal aging, the growth of interfacial IMC layers at both Sn3.0Ag0.5Cu-ball/Cu and Sn3.0Ag0.5Cu-paste/Cu interfaces of joints is mainly controlled by bulk diffusion.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"1 1","pages":"1010-1014"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91544364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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