The objective of this paper is to investigate the effect of rapid thermal cycling on microstructure and optical property (luminous flux and luminous efficiency) of high power light emitting diode (LED) by thermal fatigue testing from -40 to 125. Under an application of thermal fatigue device as a heating source, the specimens that were being non-operating and thermal fatigue testing in the experiment were rapidly heated and cooled based on a control system that employs a fuzzy logic algorithm, respectively. The optical performances, including luminous flux, luminous efficiency, radiant power and color temperature (CCT) of LED specimens were tested and analyzed. It was found that the rapid thermal cycling have similar evident influence on them. The results showed that the color purity of LED was also descended, the correlated color temperature (CCT) was also risen, but their changing rate and extents are different. The high and low temperature distribution in LED chip was simulated by finite element modeling which is helpful for the failure analysis and design of the reliability of the LED packaging. The microstructures of LED chips are analyzed after different rapid thermal cycling time. The results are showed that rapid thermal cycling can affect greatly the LED properties and interface microstructures. All the results indicate that this approach to rapid thermal cycling by using rapid heating source is feasible to investigate the optical performance of high power LED, so it can also effectively verify the reliability of LED devices.
{"title":"A comparative study of properties and microstructures on thermal fatigue testing of a high-power LED","authors":"Jibing Chen, Nong Wan, Juying Li, Zhanwen He, Yiping Wu","doi":"10.1109/ICEPT.2016.7583200","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583200","url":null,"abstract":"The objective of this paper is to investigate the effect of rapid thermal cycling on microstructure and optical property (luminous flux and luminous efficiency) of high power light emitting diode (LED) by thermal fatigue testing from -40 to 125. Under an application of thermal fatigue device as a heating source, the specimens that were being non-operating and thermal fatigue testing in the experiment were rapidly heated and cooled based on a control system that employs a fuzzy logic algorithm, respectively. The optical performances, including luminous flux, luminous efficiency, radiant power and color temperature (CCT) of LED specimens were tested and analyzed. It was found that the rapid thermal cycling have similar evident influence on them. The results showed that the color purity of LED was also descended, the correlated color temperature (CCT) was also risen, but their changing rate and extents are different. The high and low temperature distribution in LED chip was simulated by finite element modeling which is helpful for the failure analysis and design of the reliability of the LED packaging. The microstructures of LED chips are analyzed after different rapid thermal cycling time. The results are showed that rapid thermal cycling can affect greatly the LED properties and interface microstructures. All the results indicate that this approach to rapid thermal cycling by using rapid heating source is feasible to investigate the optical performance of high power LED, so it can also effectively verify the reliability of LED devices.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"120 1","pages":"576-579"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87847644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583195
Y. Guan, Qinghua Zeng, J. Chen, Wei Meng, Yufeng Jin, Shengli Ma
TSV has emerged as a promising technique for three dimensional packaging. Square TSV is employed for some special type SRAM and DRAM memories, which are usually fabricated at individual advanced IC foundries. The profile- preserving property are usually very important and there is close relationship between the related process condition and the profile-preserving property. In this paper, parametric study of related deep reactive ion etching process for square TSV are conducted, and high density square TSV with 10000 pins per square centimeter is fabricated employed the optimized process.
{"title":"Parametric study of DRIE process for enhancing the profile-preserving property of square through silicon via","authors":"Y. Guan, Qinghua Zeng, J. Chen, Wei Meng, Yufeng Jin, Shengli Ma","doi":"10.1109/ICEPT.2016.7583195","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583195","url":null,"abstract":"TSV has emerged as a promising technique for three dimensional packaging. Square TSV is employed for some special type SRAM and DRAM memories, which are usually fabricated at individual advanced IC foundries. The profile- preserving property are usually very important and there is close relationship between the related process condition and the profile-preserving property. In this paper, parametric study of related deep reactive ion etching process for square TSV are conducted, and high density square TSV with 10000 pins per square centimeter is fabricated employed the optimized process.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"16 1","pages":"555-557"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87952136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Through Silicon Via(TSVs) technology is one of the most prominent feature in future microelectronic devices packaging. Since TSVs contain the interfaces of heterogeneous materials that have high CTE mismatch, and would hence produce large thermal stresses under temperature loading, often leading to mechanical failure. A failure stress mathematical model is established and the algorithm of mathematical model is prepared by using subroutine and fracture failure modeling of Cu/SiO2 interface in TSV using finite element method (FEM) with cohesive zone model as well as stiffness degradation evaluation criterion was employed. Numerical simulation results show that large thermal stresses induced by the unique feature of TSV structure and the high mismatch of CTE between silicon substrate, dielectric layer and copper core, would lead to Cu/SiO2 interface delamination and the failure mode of the interface is shear stress predominantly. The phase angle at the tip of interfacial crack is almost 80 degrees when the interface was about to crack and then it will decrease as the crack grows gradually. However, the value of phase angle is always more than 45 degrees. Additionally, the fracture analysis to the damage process of interfacial crack under mixed-mode loading has been derived based on power law of energy criterion. It is noted that the temperature cracking of the interface is reduced and the crack propagation of Cu/SiO2 will difficult as the fracture energy of cohesive elements increases.
{"title":"Failure analysis on the mechanical property of Through-Silicon Vias interface using a cohesive zone model","authors":"Ganglong Li, Zhuo Chen, Sen Cao, Honglong Luo, Liulu Jiang, Wenhui Zhu","doi":"10.1109/ICEPT.2016.7583372","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583372","url":null,"abstract":"Through Silicon Via(TSVs) technology is one of the most prominent feature in future microelectronic devices packaging. Since TSVs contain the interfaces of heterogeneous materials that have high CTE mismatch, and would hence produce large thermal stresses under temperature loading, often leading to mechanical failure. A failure stress mathematical model is established and the algorithm of mathematical model is prepared by using subroutine and fracture failure modeling of Cu/SiO2 interface in TSV using finite element method (FEM) with cohesive zone model as well as stiffness degradation evaluation criterion was employed. Numerical simulation results show that large thermal stresses induced by the unique feature of TSV structure and the high mismatch of CTE between silicon substrate, dielectric layer and copper core, would lead to Cu/SiO2 interface delamination and the failure mode of the interface is shear stress predominantly. The phase angle at the tip of interfacial crack is almost 80 degrees when the interface was about to crack and then it will decrease as the crack grows gradually. However, the value of phase angle is always more than 45 degrees. Additionally, the fracture analysis to the damage process of interfacial crack under mixed-mode loading has been derived based on power law of energy criterion. It is noted that the temperature cracking of the interface is reduced and the crack propagation of Cu/SiO2 will difficult as the fracture energy of cohesive elements increases.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"41 1","pages":"1341-1345"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87969725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583404
Shuaige Qiao, L. Tao, T. Ren, Zhao-Lin Liu
In semiconductor manufacturing processing, IC chips need to be shipped or transferred to EOL (End of Line), SMT (Surface Mounted Technology) or customers after assembly processing and final test. Before these processes, the dry packing is necessary which is also required by JEDEC (Joint Electron Device Engineering Council) standard. Generally, Tape & Reel packing is a typical method among lots of packing methods. This packing method has more advantages than others such as easier carry, easier transfer and lower cost. However, it also has more challenges due to its carry quality and capacity. It has to meet packing quality in transfer process and also meet packing performance in EOL procedure; If the packing quality is poor, the device may drop down and be damaged during transferring, which will cause a lot of troubles between supplier and customer. So packing ability and verification is very important. This paper introduced a method to control sealing ability for Tape and Reel packing process.
在半导体制造加工过程中，IC芯片需要在组装加工和最终测试后发货或转移到EOL (End of Line)， SMT (Surface Mounted Technology)或客户。在这些工艺之前，必须进行干燥包装，这也是JEDEC(联合电子器件工程委员会)标准的要求。在众多的包装方法中，卷筒包装是一种典型的包装方法。这种包装方法比其他包装方法更容易携带，更容易转移，成本更低。然而，由于其承载质量和承载能力，它也面临着更多的挑战。在传递过程中满足包装质量要求，在EOL过程中满足包装性能要求;如果包装质量不好，设备在运输过程中可能会掉落损坏，给供应商和客户之间带来很多麻烦。因此包装能力和验证是非常重要的。介绍了卷筒带包装过程中密封性能的控制方法。
{"title":"Tape & Reel single side peel force test verification","authors":"Shuaige Qiao, L. Tao, T. Ren, Zhao-Lin Liu","doi":"10.1109/ICEPT.2016.7583404","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583404","url":null,"abstract":"In semiconductor manufacturing processing, IC chips need to be shipped or transferred to EOL (End of Line), SMT (Surface Mounted Technology) or customers after assembly processing and final test. Before these processes, the dry packing is necessary which is also required by JEDEC (Joint Electron Device Engineering Council) standard. Generally, Tape & Reel packing is a typical method among lots of packing methods. This packing method has more advantages than others such as easier carry, easier transfer and lower cost. However, it also has more challenges due to its carry quality and capacity. It has to meet packing quality in transfer process and also meet packing performance in EOL procedure; If the packing quality is poor, the device may drop down and be damaged during transferring, which will cause a lot of troubles between supplier and customer. So packing ability and verification is very important. This paper introduced a method to control sealing ability for Tape and Reel packing process.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"74 1","pages":"1483-1486"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85919448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583362
Nanbo Li, Zaifu Cui, Han Lu, Xuanyou Chen, J. Wei, M. Cai, Ping Zhang, Daoguo Yang
Light-emitting diode (LED) is a promising semiconductor optoelectronic device, which has small size, long life, environmental protection and many other advantages. Due to its nanosecond time response of luminescence, LED can achieve high-speed modulation of information. Indoor LED lighting source is regarded as communication base station, through high frequency flashing of the lighting source to pass on information, downstream data link with a wireless transmission protocol complementary is provided and lighting and communication integration is implemented. In the aspect of electromagnetic radiation, communication efficiency and safety, it has a lot of advantages over radio frequency (RF), which is a new high-speed data transmission mode. In this paper, by using the advantage of short response time of LED, a visible light communication system based on On-Off Keying (OOK) modulation and demodulation technique is designed, which can improve lighting quality and adaptation to the environment without changing the lighting LED spectral components. By using software and hardware combination, video transmission between the two devices is complemented by optical communication. The prototype of the test platform is constructed, and then debugging and analyzing is conducted. The video transmission is further tested, and the feasibility of the scheme is verified, which meets expected goals. This system provides a method for information transmission and has theoretical and practical guidance for LED optical communication.
{"title":"Design and analysis of video information transmission system based on visible LED light communication","authors":"Nanbo Li, Zaifu Cui, Han Lu, Xuanyou Chen, J. Wei, M. Cai, Ping Zhang, Daoguo Yang","doi":"10.1109/ICEPT.2016.7583362","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583362","url":null,"abstract":"Light-emitting diode (LED) is a promising semiconductor optoelectronic device, which has small size, long life, environmental protection and many other advantages. Due to its nanosecond time response of luminescence, LED can achieve high-speed modulation of information. Indoor LED lighting source is regarded as communication base station, through high frequency flashing of the lighting source to pass on information, downstream data link with a wireless transmission protocol complementary is provided and lighting and communication integration is implemented. In the aspect of electromagnetic radiation, communication efficiency and safety, it has a lot of advantages over radio frequency (RF), which is a new high-speed data transmission mode. In this paper, by using the advantage of short response time of LED, a visible light communication system based on On-Off Keying (OOK) modulation and demodulation technique is designed, which can improve lighting quality and adaptation to the environment without changing the lighting LED spectral components. By using software and hardware combination, video transmission between the two devices is complemented by optical communication. The prototype of the test platform is constructed, and then debugging and analyzing is conducted. The video transmission is further tested, and the feasibility of the scheme is verified, which meets expected goals. This system provides a method for information transmission and has theoretical and practical guidance for LED optical communication.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"110 1","pages":"1301-1306"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75993978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583254
W. Tian, Hao Cui
To guarantee the heat reliability of electronic devices, heat analysis is absolutely necessary hence the success of thermal design becomes the key to the physical design of the equipment. In this paper, a simplification method of solder joints based on mathematical derivation and heat transfer theory was proposed. In added underfill and without underfill both cases, with different diameter and solder pitch, ANSYS Workbench software was used for steady- state thermal simulation and analysis of the error of equivalent method as well. Conclusions are made that the equivalent error will be less than ± 1.0% in Z direction and ± 30.0% in X or Y direction, respectively.
{"title":"A simplification method of solder joints for thermal analysis in 3D packages","authors":"W. Tian, Hao Cui","doi":"10.1109/ICEPT.2016.7583254","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583254","url":null,"abstract":"To guarantee the heat reliability of electronic devices, heat analysis is absolutely necessary hence the success of thermal design becomes the key to the physical design of the equipment. In this paper, a simplification method of solder joints based on mathematical derivation and heat transfer theory was proposed. In added underfill and without underfill both cases, with different diameter and solder pitch, ANSYS Workbench software was used for steady- state thermal simulation and analysis of the error of equivalent method as well. Conclusions are made that the equivalent error will be less than ± 1.0% in Z direction and ± 30.0% in X or Y direction, respectively.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"20 1","pages":"812-815"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78881535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583111
Jie Shen, Wei-Xiong Luo, Wenhao Dong, Ming Li, Liming Gao
The competitive adsorption between suppressor and accelerator is the crucial behavior to achieve void-free filling of TSV during electrodeposition. Convective velocity and potential on the reactive electrode surface are two important factors for adsorption of additives. In this paper, a method of calculating the competitively adsorptive parameter Kads is found to quantize the effect of these factors based on investigating the distribution of potential and convective velocity in via. And a special competitively adsorptive parameter value as threshold value K0 is defined to estimate which represents the leading function between suppressor and accelerator in competitive adsorption, and the value of K0 is calculated as 1.631×10-7m/s. Furthermore, TSV filling model with diverse diameter is built, and the simulation results are consistent with that of experiment.
{"title":"Numerical model with competitively adsorptive mechanism for copper electrodeposition of TSV","authors":"Jie Shen, Wei-Xiong Luo, Wenhao Dong, Ming Li, Liming Gao","doi":"10.1109/ICEPT.2016.7583111","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583111","url":null,"abstract":"The competitive adsorption between suppressor and accelerator is the crucial behavior to achieve void-free filling of TSV during electrodeposition. Convective velocity and potential on the reactive electrode surface are two important factors for adsorption of additives. In this paper, a method of calculating the competitively adsorptive parameter Kads is found to quantize the effect of these factors based on investigating the distribution of potential and convective velocity in via. And a special competitively adsorptive parameter value as threshold value K0 is defined to estimate which represents the leading function between suppressor and accelerator in competitive adsorption, and the value of K0 is calculated as 1.631×10-7m/s. Furthermore, TSV filling model with diverse diameter is built, and the simulation results are consistent with that of experiment.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"25 1","pages":"162-165"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79181955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583083
Haiyan Liu, Yadong Wei, Jianhong Wang, Sean Xu
Wafer with thicker metal is very challenge for mechanical dicing, especially the SGPC pattern in saw street. The chipping and peeling are easily happening on the SGPC pattern. In recent years, there are many effort spent on traditional sawing to process thick metal wafer. The current advanced mechanical dicing method for wafer with thick metal and narrower saw street is step cut. But the step cut UPH is lower than single cut, and it will be cost adder for two blade dicing. In this study, single cut is investigated. Topside chipping/Peeling is key challenge. The wafer tech used in this study is LFET with 3.6um metal thickness. Blade evaluation and dicing parameter optimization is discussed in this paper. High power optical microscope, SEM, FIB were the inspection tools used to evaluate the dicing performance. Die topside chipping and die edge quality were investigated. This die was packaged into a 54LD SOIC package. Post assembly, CSAM and electrical test were performed on the assembled parts at TO, post MSL3/260degree C, post 264h UHST (llOoC/85%RH), and post TC500cycles (-65°C to 150°C). With optimized parameter, a good dicing quality was get, without metal burr, metal peeling, micro cracks on side wall etc. The packaged sample had passed all stress. No mechanical dicing defect related fail. It is concluded that the single cut mechanical dicing is a good solution for thick metal wafer dicing.
{"title":"Investigation of single cut process in mechanical dicing for thick metal wafer","authors":"Haiyan Liu, Yadong Wei, Jianhong Wang, Sean Xu","doi":"10.1109/ICEPT.2016.7583083","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583083","url":null,"abstract":"Wafer with thicker metal is very challenge for mechanical dicing, especially the SGPC pattern in saw street. The chipping and peeling are easily happening on the SGPC pattern. In recent years, there are many effort spent on traditional sawing to process thick metal wafer. The current advanced mechanical dicing method for wafer with thick metal and narrower saw street is step cut. But the step cut UPH is lower than single cut, and it will be cost adder for two blade dicing. In this study, single cut is investigated. Topside chipping/Peeling is key challenge. The wafer tech used in this study is LFET with 3.6um metal thickness. Blade evaluation and dicing parameter optimization is discussed in this paper. High power optical microscope, SEM, FIB were the inspection tools used to evaluate the dicing performance. Die topside chipping and die edge quality were investigated. This die was packaged into a 54LD SOIC package. Post assembly, CSAM and electrical test were performed on the assembled parts at TO, post MSL3/260degree C, post 264h UHST (llOoC/85%RH), and post TC500cycles (-65°C to 150°C). With optimized parameter, a good dicing quality was get, without metal burr, metal peeling, micro cracks on side wall etc. The packaged sample had passed all stress. No mechanical dicing defect related fail. It is concluded that the single cut mechanical dicing is a good solution for thick metal wafer dicing.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"11 1","pages":"26-30"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79206737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583177
Qianqian Liu, Pengli Zhu, Gang Li, Q. Guo, X. Shuai, R. Sun, C. Wong
Aluminum-doped ZnO (AZO) nanoparticles with different Al doping levels were synthesized using a microwave-assisted method. The synthesized AZO crystal structure and shape were characterized by X-ray diffraction (XRD) and scanning electron microscopy (SEM). XRD results show that the produced nanoparticles can be fully assigned to the hexagonal wurtzite ZnO crystalline structure. SEM results showed that the morphologies of the AZO samples were spherical-like structure, and the crystalline size of the samples decreased with the increasing Al doping levels. The doping level of the synthesized nanoparticles were analyzed by Energy Dispersive X-ray Detector (EDX), and the result showed that Al element was successfully incorporated into ZnO crystal lattice. The optical properties and electrical properties of AZO samples were researched by UV-Vis spectroscopy and four-point probe, respectively. The optical spectra show that the band of the samples are affected by Al doping levels. The resistivity of the AZO samples first decreased and then increased with increasing the Al doping content due to the changes in the electron and dopant concentrations. AZO exhibited the smallest electrical resistivity with Al doping content at 3.0 at.%.
{"title":"A microwave-assisted solvothermal process to synthesize Al-doped ZnO powders and its optical and electrical properties","authors":"Qianqian Liu, Pengli Zhu, Gang Li, Q. Guo, X. Shuai, R. Sun, C. Wong","doi":"10.1109/ICEPT.2016.7583177","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583177","url":null,"abstract":"Aluminum-doped ZnO (AZO) nanoparticles with different Al doping levels were synthesized using a microwave-assisted method. The synthesized AZO crystal structure and shape were characterized by X-ray diffraction (XRD) and scanning electron microscopy (SEM). XRD results show that the produced nanoparticles can be fully assigned to the hexagonal wurtzite ZnO crystalline structure. SEM results showed that the morphologies of the AZO samples were spherical-like structure, and the crystalline size of the samples decreased with the increasing Al doping levels. The doping level of the synthesized nanoparticles were analyzed by Energy Dispersive X-ray Detector (EDX), and the result showed that Al element was successfully incorporated into ZnO crystal lattice. The optical properties and electrical properties of AZO samples were researched by UV-Vis spectroscopy and four-point probe, respectively. The optical spectra show that the band of the samples are affected by Al doping levels. The resistivity of the AZO samples first decreased and then increased with increasing the Al doping content due to the changes in the electron and dopant concentrations. AZO exhibited the smallest electrical resistivity with Al doping content at 3.0 at.%.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"37 1","pages":"468-472"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77110960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/ICEPT.2016.7583109
Jiawei Zhang, Guoping Zhang, R. Sun, S. Lee, C. Wong
A low-dielectric-constant organosilica was developed for interlayer dielectric, introducing adamantane which possesses low polarity and unique rigid structure. Novel organosilane precursor, adamantane-bridged organosilane precursor, was synthesized and characterized. Precursor was mixed with porogen P123, acid and ethanol to prepare coating solution, and the novel periodic mesoporous organosilica (PMO) thin film was prepared via evaporation-induced self-assembly method. The PMO thin film presents ultra-low dielectric constants (1.56@1 MHz) and high Young's modulus (6.69±0.54 GPa) via optimizing the porogen content, besides it shows order structure and hydrophobic property.
{"title":"Low-dielectric-constant novel periodic mesoporous organosilica thin film for interlayer dielectric","authors":"Jiawei Zhang, Guoping Zhang, R. Sun, S. Lee, C. Wong","doi":"10.1109/ICEPT.2016.7583109","DOIUrl":"https://doi.org/10.1109/ICEPT.2016.7583109","url":null,"abstract":"A low-dielectric-constant organosilica was developed for interlayer dielectric, introducing adamantane which possesses low polarity and unique rigid structure. Novel organosilane precursor, adamantane-bridged organosilane precursor, was synthesized and characterized. Precursor was mixed with porogen P123, acid and ethanol to prepare coating solution, and the novel periodic mesoporous organosilica (PMO) thin film was prepared via evaporation-induced self-assembly method. The PMO thin film presents ultra-low dielectric constants (1.56@1 MHz) and high Young's modulus (6.69±0.54 GPa) via optimizing the porogen content, besides it shows order structure and hydrophobic property.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"498 1","pages":"153-156"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86137314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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