IEEE open journal of circuits and systems最新文献

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Editorial IEEE Open Journal of Circuits and Systems: Special Section on Advanced Power Electronics Techniques for Smart Grid Applications IEEE电路与系统开放杂志:智能电网应用的先进电力电子技术专题

Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE open journal of circuits and systems

Pub Date : 2022-11-23 DOI: 10.1109/OJCAS.2022.3218914

Mengqi Wang;Xiu Yao

The Advent of modern power electronics has brought tremendous impact on emerging power systems. In an emerging smart grid, as the number of inverter- and converter-based devices increases to more than hundreds of thousands, it is rather intuitive that the state-of-the-art technical solutions and industry practices will no longer be sustainable. The combination of power electronics and advanced control technologies serve as the key enabler of a wide range of smart grid applications. While tremendous progress has been made in advancing the standalone power electronics technologies, much less attention has been paid to bridging the gap between traditionally disjoint research areas – power electronics, power systems, and intelligent control – ultimately facilitating the vision of 100% carbonneutral energy systems come to fruition. There is a growing interest in the concepts of power electronics-enabled power systems around the world. This special section includes two high-quality papers, which cover the trending topic on the control strategy for inverters that are essential for Smart Grid applications.

现代电力电子技术的出现给新兴的电力系统带来了巨大的影响。在新兴的智能电网中，随着基于逆变器和转换器的设备数量增加到数十万台以上，人们很直观地看到，最先进的技术解决方案和行业实践将不再可持续。电力电子技术和先进控制技术的结合是广泛智能电网应用的关键推动者。尽管在推进独立的电力电子技术方面取得了巨大进展，但人们对弥合传统上脱节的研究领域——电力电子、电力系统和智能控制——之间的差距却关注得更少，最终推动了100%碳中和能源系统的愿景实现。世界各地对电力电子系统的概念越来越感兴趣。本专题部分包括两篇高质量的论文，涵盖了智能电网应用中必不可少的逆变器控制策略的趋势主题。

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引用次数: 0

Understanding Canadians' knowledge, attitudes and practices related to antimicrobial resistance and antibiotic use: Results from public opinion research. 了解加拿大人对抗菌药耐药性和抗生素使用的认识、态度和做法：民意调查结果。

Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE open journal of circuits and systems

Pub Date : 2022-11-03 DOI: 10.14745/ccdr.v48i1112a08

Anna-Louise Crago, Stéphanie Alexandre, Kahina Abdesselam, Denise Gravel Tropper, Michael Hartmann, Glenys Smith, Tanya Lary

Background: Antimicrobial resistance is a current and pressing issue in Canada. Population-level antibiotic consumption is a key driver. The Public Health Agency of Canada undertook a comprehensive assessment of the Canadian public's knowledge, attitudes and practices in relation to antimicrobial resistance and antibiotic use, to help inform the implementation of public awareness and knowledge mobilization.

Methods: Data were collected in three phases: 1) six in-person focus groups (53 participants) to help frame the survey; 2) nationwide survey administration to 1,515 Canadians 18 years and older via cell phone and landline; and 3) 12 online focus groups to analyze survey responses. Survey data is descriptive.

Results: A third (33.9%) of survey respondents reported using antibiotics at least once in the previous 12 months, 15.8% more than twice and 4.6% more than five times. Antibiotic use was reported more among 1) those with a household income below $60,000, 2) those with a medical condition, 3) those without a university education and 4) among the youngest adults (18-24 years of age) and (25-34 years of age). Misinformation about antibiotics was common: 32.5% said antibiotics "can kill viruses"; 27.9% said they are "effective against colds and flu"; and 45.8% said they are "effective in treating fungal infections". Inaccurate information was reported more often by those 1) aged 18-24 years, 2) with a high school degree or less and 3) with a household income below $60,000. In focus groups, the time/money trade-offs involved in accessing medical care were reported to contribute to pushing for a prescription or using unprescribed antibiotics, particularly in more remote contexts, while the cost of a prescription contributed to sharing and using old antibiotics. A large majority, across all demographic groups, followed the advice of medical professionals in making health decisions.

Conclusion: High trust in medical professionals presents an important opportunity for knowledge mobilization. Delayed prescriptions may alleviate concerns about the time/money constraints of accessing future care. Consideration should be given to prioritizing access to appropriate diagnostic and other technology for northern and/or remote communities and/or medical settings serving many young children to alleviate concerns of needing a prescription or of needing to return later.

背景：抗菌药耐药性是加拿大当前面临的一个紧迫问题。人口层面的抗生素消费是一个关键驱动因素。加拿大公共卫生署对加拿大公众在抗菌药耐药性和抗生素使用方面的知识、态度和做法进行了全面评估，以帮助提高公众意识和知识动员：方法：分三个阶段收集数据：1）6 个面对面焦点小组（53 人参加），帮助制定调查框架；2）通过手机和座机对 1,515 名 18 岁及以上加拿大人进行全国范围的调查；3）12 个在线焦点小组，分析调查回复。调查数据为描述性数据：三分之一（33.9%）的受访者表示在过去 12 个月中至少使用过一次抗生素，15.8% 的受访者使用过两次以上，4.6% 的受访者使用过五次以上。在以下人群中使用抗生素的比例较高：1）家庭收入低于 60,000 美元者；2）患有疾病者；3）未受过大学教育者；4）最年轻的成年人（18-24 岁）和（25-34 岁）。关于抗生素的错误信息很常见：32.5%的人说抗生素 "可以杀死病毒"；27.9%的人说抗生素 "对感冒和流感有效"；45.8%的人说抗生素 "对治疗真菌感染有效"。1) 年龄在 18-24 岁；2) 高中或以下学历；3) 家庭收入低于 60,000 美元的人群更常报告信息不准确。据报道，在焦点小组中，就医过程中的时间/金钱权衡促使人们去开处方或使用未开具处方的抗生素，尤其是在较偏远的地区，而处方的费用则促使人们分享和使用旧的抗生素。在所有人群中，大多数人在做出健康决定时都会听从医疗专业人员的建议：结论：对医疗专业人员的高度信任为知识动员提供了重要机会。延迟处方可减轻对未来获得医疗服务的时间/金钱限制的担忧。应考虑优先为北部和/或偏远社区和/或为许多幼儿提供服务的医疗机构提供适当的诊断和其他技术，以减轻对需要处方或需要稍后返回的担忧。

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引用次数: 0

Wang Algebra: From Theory to Practice 王代数:从理论到实践

Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE open journal of circuits and systems

Pub Date : 2022-10-26 DOI: 10.1109/OJCAS.2022.3217065

Bob Ross;Cong Ling

Wang algebra was initiated by Ki-Tung Wang as a short-cut method for the analysis of electrical networks. It was later popularized by Duffin and has since found numerous applications in electrical engineering and graph theory. This is a semi-tutorial paper on Wang algebra, its history, and modern applications. We expand Duffin’s historic notes on Wang algebra to give a full account of Ki-Tung Wang’s life. A short proof of Wang algebra using group theory is presented. We exemplify the usefulness of Wang algebra in the design of T-coils. Bridged T-coils give a significant advantage in bandwidth, and were widely adopted in Tektronix oscilloscopes, but design details were guarded as a trade secret. The derivation presented in this paper, based on Wang algebra, is more general and simpler than those reported in literature. This novel derivation has not been shared with the public before.

王代数是由王开创的一种分析电网的捷径方法。它后来被Duffin推广，并在电气工程和图论中得到了许多应用。这是一篇关于王代数及其历史和现代应用的半教程论文。我们扩展了达夫关于王代数的历史笔记，以全面描述王的生平。利用群论给出了王代数的一个简短证明。我们举例说明王代数在T-线圈设计中的有用性。桥接T型线圈在带宽方面具有显著优势，并被广泛用于Tektronix示波器，但设计细节被视为商业秘密。本文在王代数的基础上提出的推导比文献中报道的推导更一般、更简单。这种新颖的派生方法以前从未与公众分享过。

引用次数: 0

Loop Dynamics Analysis of PAM-4 Mueller–Muller Clock and Data Recovery System PAM-4 Mueller-Muller时钟及数据恢复系统的环动力学分析

Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE open journal of circuits and systems

Pub Date : 2022-10-04 DOI: 10.1109/OJCAS.2022.3211844

Kunal Yadav;Ping-Hsuan Hsieh;Anthony Chan Carusone

This paper provides a framework for analyzing the loop dynamics of the clock and data recovery (CDR) system of ADC-based PAM-4 receivers, which will assist in extending the timing recovery loop bandwidth. This paper formulates an accurate linear model of linear and signed Mueller–Muller phase detector for baud-rate clock recovery. Different equalization configurations of continuous-time linear equalizer (CTLE) and feed-forward equalizer (FFE) are evaluated from a phase detector performance perspective to enable high CDR loop bandwidth. The impact of loop latency on the timing recovery of ADC-based PAM-4 receivers is also analyzed and demonstrated using accurate behavioral simulations. The analysis and behavioral results show that, to achieve high CDR loop bandwidth with a good jitter tolerance, the phase detector gain to noise ratio should be maximized, and CDR loop latency should be minimized.

本文提供了一个分析基于adc的PAM-4接收机时钟和数据恢复(CDR)系统的环路动力学的框架，这将有助于扩展时序恢复环路带宽。本文建立了用于波特率时钟恢复的线性和签名穆勒-穆勒鉴相器的精确线性模型。从鉴相性能的角度对连续时间线性均衡器(CTLE)和前馈均衡器(FFE)的不同均衡配置进行了评估，以实现高CDR环路带宽。环路延迟对基于adc的PAM-4接收机时序恢复的影响也进行了分析，并通过精确的行为模拟进行了验证。分析和行为结果表明，为了获得高的CDR环路带宽和良好的抗抖动能力，应该最大化鉴相器的增益噪声比，最小化CDR环路延迟。

引用次数: 2

UP-GDBF: A 19.3 Gbps Error Floor Free 4KB LDPC Decoder for NAND Flash Applications UP-GDBF:用于NAND闪存应用的19.3 Gbps无错误层4KB LDPC解码器

Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE open journal of circuits and systems

Pub Date : 2022-09-26 DOI: 10.1109/OJCAS.2022.3209152

Li-Wei Liu;Yen-Chin Liao;Hsie-Chia Chang

An error floor phenomenon, decoding performance, and throughput are three major concerns for LDPC decoders in NAND Flash applications. With a penalty method and an active iteration mechanism, we present a Unified Penalty Gradient Descent Bit Flipping (UP-GDBF) decoding algorithm, which not only possesses error-floor free property but also improves convergence speed in decoding performance. To fulfill the high-throughput requirement while maintaining reliable error correction capability, we propose an energy-based backtracking scheme to reduce 40% latency with a negligible 0.8% area overhead. Implemented in TSMC 16nm process, the proposed 4KB LDPC decoder can achieve a throughput of 19.3 Gbps with 0.120 mm2 area to satisfy ONFI 5.0 throughput requirement. Compared to existing approaches, our decoder architecture provides superior data rate and decoding performance in both 1KB and 4KB LDPC codes.

错误层现象、解码性能和吞吐量是NAND闪存应用中LDPC解码器的三个主要关注点。采用惩罚方法和主动迭代机制，提出了一种统一惩罚梯度下降位翻转(UP-GDBF)译码算法，该算法不仅具有无错层的特性，而且提高了译码性能的收敛速度。为了满足高吞吐量需求，同时保持可靠的纠错能力，我们提出了一种基于能量的回溯方案，以微不足道的0.8%的面积开销减少40%的延迟。采用台积电16nm制程实现的4KB LDPC解码器，在0.120 mm2的面积上实现19.3 Gbps的吞吐量，满足ONFI 5.0吞吐量要求。与现有方法相比，我们的解码器架构在1KB和4KB LDPC码中都提供了更高的数据速率和解码性能。

引用次数: 1

Demonstrating Analog Inference on the BrainScaleS-2 Mobile System 在brainscale -2移动系统上演示模拟推理

Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE open journal of circuits and systems

Pub Date : 2022-09-21 DOI: 10.1109/OJCAS.2022.3208413

Yannik Stradmann;Sebastian Billaudelle;Oliver Breitwieser;Falk Leonard Ebert;Arne Emmel;Dan Husmann;Joscha Ilmberger;Eric Müller;Philipp Spilger;Johannes Weis;Johannes Schemmel

We present the BrainScaleS-2 mobile system as a compact analog inference engine based on the BrainScaleS-2 ASIC and demonstrate its capabilities at classifying a medical electrocardiogram dataset. The analog network core of the ASIC is utilized to perform the multiply-accumulate operations of a convolutional deep neural network. At a system power consumption of 5.6W, we measure a total energy consumption of

$mathrm {192 ~mu text {J} }$

for the ASIC and achieve a classification time of 276

$mu$

s per electrocardiographic patient sample. Patients with atrial fibrillation are correctly identified with a detection rate of (93.7 ± 0.7)% at (14.0 ± 1.0)% false positives. The system is directly applicable to edge inference applications due to its small size, power envelope, and flexible I/O capabilities. It has enabled the BrainScaleS-2 ASIC to be operated reliably outside a specialized lab setting. In future applications, the system allows for a combination of conventional machine learning layers with online learning in spiking neural networks on a single neuromorphic platform.

我们介绍了BrainScaleS-2移动系统作为一个基于BrainScaleS-2 ASIC的紧凑型模拟推理引擎，并展示了其对医学心电图数据集进行分类的能力。ASIC的模拟网络核心用于执行卷积深度神经网络的乘法累加运算。在5.6W的系统功耗下，我们测量了ASIC的总能耗$mathrm｛192~mutext｛J｝｝$，并实现了每个心电图患者样本276$mu$s的分类时间。心房颤动患者被正确识别，假阳性率为（14.0±1.0）%，检测率为（93.7±0.7）%。由于其体积小、功率包络和灵活的I/O功能，该系统可直接应用于边缘推理应用。它使BrainScaleS-2 ASIC能够在专业实验室环境之外可靠运行。在未来的应用中，该系统允许将传统的机器学习层与单个神经形态平台上的尖峰神经网络中的在线学习相结合。

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引用次数: 7

SEKV-E: Parameter Extractor of Simplified EKV I-V Model for Low-Power Analog Circuits SEKV-E:用于低功耗模拟电路的简化EKV I-V模型的参数提取器

Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE open journal of circuits and systems

Pub Date : 2022-09-20 DOI: 10.1109/OJCAS.2022.3179046

Hung-Chi Han;Antonio D’Amico;Christian Enz

This paper presents the open-source Python-based parameter extractor (SEKV-E) for the simplified EKV (sEKV) model, which enables the modern low-power circuit designs with the inversion coefficient design methodology. The tool extracts the essential sEKV parameters automatically from the given

$I$

$V$

curves using the direct extraction and the multi-stage optimization process. It also handles the overfitting issue because of non-linear least squares. Moreover, this work demonstrates the SEKV-E as a universal tool by widely applying it to different silicon technologies, temperatures, dimensions, and back-gate voltages.

本文针对简化的EKV (sEKV)模型提出了基于python的开源参数提取器(sEKV - e)，使现代低功耗电路设计能够采用反转系数设计方法。该工具通过直接提取和多阶段优化过程，自动从给定的$I$ - $V$曲线中提取基本的sEKV参数。它还处理过拟合问题，因为非线性最小二乘。此外，这项工作通过广泛应用于不同的硅技术、温度、尺寸和后门电压，证明了SEKV-E是一种通用工具。

引用次数: 2

Peak-Power Aware Life-Time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems 容错混合临界系统的峰值功率感知全寿命可靠性改进

Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE open journal of circuits and systems

Pub Date : 2022-09-20 DOI: 10.1109/OJCAS.2022.3207598

Mozhgan Navardi;Behnaz Ranjbar;Nezam Rohbani;Alireza Ejlali;Akash Kumar

Mixed-Criticality Systems (MCSs) include tasks with multiple levels of criticality and different modes of operation. These systems bring benefits such as energy and resource saving while ensuring safe operation. However, management of available resources in order to achieve high utilization, low power consumption, and required reliability level is challenging in MCSs. In many cases, there is a trade-off between these goals. For instance, although using fault-tolerance techniques, such as replication, leads to improving the timing reliability, it increases power consumption and can threaten life-time reliability. In this work, we introduce an approach named

${mathbf {L}}ife-time ,,{mathbf {P}}eak ,,{mathbf {P}}{ower~management~in},,{mathbf {M}}{ixed}-{mathbf {C}}{riticality,, systems}$

(LPP-MC) to guarantee reliability, along with peak power reduction. This approach maps the tasks using a novel metric called Reliability-Power Metric (RPM). The LPP-MC approach uses this metric to balance the power consumption of different processor cores and to improve the life-time of a chip. Moreover, to guarantee the timing reliability of MCSs, a fault-tolerance technique, called task re-execution, is utilized in this approach. We evaluate the proposed approach by a real avionics task set, and various synthetic task sets. The experimental results show that the proposed approach mitigates the aging rate and reduces peak power by up to 20.6% and 17.6%, respectively, compared to state-of-the-art.

混合临界系统(mcs)包括具有多个临界级别和不同运行模式的任务。这些系统在保证安全运行的同时，带来了节能、节约资源等效益。然而，管理可用资源以实现高利用率、低功耗和所需的可靠性水平对mcs来说是一个挑战。在许多情况下，这两个目标之间存在权衡。例如，尽管使用容错技术(如复制)可以提高定时可靠性，但它会增加功耗，并可能威胁到生命周期的可靠性。在这项工作中，我们引入了一种名为${mathbf {L}} life -time ，，{mathbf {P}}eak ，，{mathbf {P}}{power ~management~ In}，，{mathbf {M}}{ixed}-{mathbf {C}}{criticality ，， systems}$ (LPP-MC)的方法来保证可靠性，同时降低峰值功率。这种方法使用一种称为可靠性-功率度量(RPM)的新度量来映射任务。LPP-MC方法使用这个指标来平衡不同处理器内核的功耗，并提高芯片的使用寿命。此外，为了保证mcs的定时可靠性，该方法还采用了任务重执行的容错技术。我们通过一个真实的航电任务集和各种合成任务集来评估所提出的方法。实验结果表明，与现有方法相比，该方法可降低老化率20.6%，峰值功率降低17.6%。

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引用次数: 2

IEEE Open Journal of Circuits and Systems: Special Section on ISICAS 2022 IEEE电路与系统开放杂志:ISICAS 2022特别部分

Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE open journal of circuits and systems

Pub Date : 2022-09-20 DOI: 10.1109/OJCAS.2022.3202588

Alison Burdett

The International Symposium on Integrated Circuits and Systems (ISICAS) is a forum for dissemination of original work with experimental results from integrated circuits and systems in the areas of analog, digital, power, energy, biomedical, sensor interfaces and communications. Papers accepted to be presented at the symposium are automatically published in special issues of leading IEEE Circuits and Systems Society (CASS) journals, namely Transactions on Circuits and Systems (TCAS) Parts I and II, Transactions on Biomedical Circuits and Systems (TBioCAS), and Open Journal of Circuits and Systems (OJCAS).

集成电路与系统国际研讨会(ISICAS)是一个传播模拟、数字、电力、能源、生物医学、传感器接口和通信领域集成电路和系统实验结果的原创作品的论坛。在研讨会上发表的论文将自动发表在IEEE电路与系统学会(CASS)主要期刊的特刊上，即《电路与系统学报》(TCAS)第一部分和第二部分、《生物医学电路与系统学报》(TBioCAS)和《电路与系统开放杂志》(OJCAS)。

引用次数: 0

Multichannel Many-Class Real-Time Neural Spike Sorting With Convolutional Neural Networks 基于卷积神经网络的多通道多类实时神经脉冲排序

Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE open journal of circuits and systems

Pub Date : 2022-09-20 DOI: 10.1109/OJCAS.2022.3184302

Jinho Yi;Jiachen Xu;Ethan Chen;Maysamreza Chamanzar;Vanessa Chen

Real-time in-sensor spike sorting is a forefront requirement in the development of brainmachine interfaces (BMIs). This work presents the characterization, design, and efficient implementation on a field-programmable gate array (FPGA) of a novel approach to neural spike sorting intended for implantable devices based on convolutional neural networks (CNNs). While the temporal features, the shape of the spike signals, could be highly mitigated from the ambient noise, the proposed classifier effectively extracts spatial features from the multi-channel neural signal to maintain high accuracy on the noisy data. The proposed classifier mechanism was tested on real data that is recorded from multi-channel electrodes, containing 27 neural units, and the classifier achieves 93.1% accuracy despite high temporal noise in the signal. For hardware synthesis, the CNN weights are quantized to reduce the model storage requirement by 93% compared to its floating point-precision version, and the model achieves an accuracy of 86.1%.

实时传感器内尖峰排序是脑机接口(bmi)发展的一个前沿要求。本文介绍了一种基于卷积神经网络(cnn)的植入式设备神经尖峰排序新方法的表征、设计和在现场可编程门阵列(FPGA)上的高效实现。同时，该分类器可以有效地从多通道神经信号中提取空间特征，以保持对噪声数据的高精度处理。在包含27个神经单元的多通道电极记录的真实数据上对所提出的分类器机制进行了测试，尽管信号中存在较高的时间噪声，但分类器的准确率仍达到93.1%。在硬件合成方面，对CNN权值进行量化，使模型的存储需求比浮点精度版本减少93%，模型的准确率达到86.1%。

引用次数: 0

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