Pub Date : 2024-03-02DOI: 10.1109/OJCAS.2024.3396336
Christian Hoyer;Jens Wagner;Frank Ellinger
This research analyzes the mutual self-organized synchronization of phase-locked loops (PLLs) in the presence of variations in the free-running frequency of a PLL. In contrast to traditional synchronization methods that rely on a reference signal, this study investigates the synchronization dynamics that arise solely from the interactions of PLL nodes within a network. Previous research has proposed theoretical frameworks that can predict the synchronized states of such designs. However, these frameworks do not account for the dynamic behavior that occurs during initial synchronization. To address this gap, this work proposes a constraint that refines the understanding of initial synchronization. The results of this analysis show that there is a maximum detuning between free-running frequencies up to which synchronization is possible. Furthermore, this analysis indicates that detuning not only affects the range of time delays at which stable synchronized states emerge between PLL nodes, but also limits the allowable range of initial phase differences for stable synchronization. In the cases studied, a frequency difference of 1.56% reduces the probability of achieving stable synchronized states through self-organized synchronization to 73.5%, while no stable synchronization can be achieved at a frequency difference greater than 2.65%. The study underscores the critical importance of operating ranges when implementing mutual coupling. In particular, all PLL nodes must have overlapping lock ranges to achieve stable synchronization. It also emphasizes the need for accurate analysis of hold and lock ranges in relation to the time delays between coupled PLL nodes.
{"title":"Impact of Frequency Heterogeneity on Mutually Synchronized Spatially Distributed 24 GHz PLLs","authors":"Christian Hoyer;Jens Wagner;Frank Ellinger","doi":"10.1109/OJCAS.2024.3396336","DOIUrl":"10.1109/OJCAS.2024.3396336","url":null,"abstract":"This research analyzes the mutual self-organized synchronization of phase-locked loops (PLLs) in the presence of variations in the free-running frequency of a PLL. In contrast to traditional synchronization methods that rely on a reference signal, this study investigates the synchronization dynamics that arise solely from the interactions of PLL nodes within a network. Previous research has proposed theoretical frameworks that can predict the synchronized states of such designs. However, these frameworks do not account for the dynamic behavior that occurs during initial synchronization. To address this gap, this work proposes a constraint that refines the understanding of initial synchronization. The results of this analysis show that there is a maximum detuning between free-running frequencies up to which synchronization is possible. Furthermore, this analysis indicates that detuning not only affects the range of time delays at which stable synchronized states emerge between PLL nodes, but also limits the allowable range of initial phase differences for stable synchronization. In the cases studied, a frequency difference of 1.56% reduces the probability of achieving stable synchronized states through self-organized synchronization to 73.5%, while no stable synchronization can be achieved at a frequency difference greater than 2.65%. The study underscores the critical importance of operating ranges when implementing mutual coupling. In particular, all PLL nodes must have overlapping lock ranges to achieve stable synchronization. It also emphasizes the need for accurate analysis of hold and lock ranges in relation to the time delays between coupled PLL nodes.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"199-210"},"PeriodicalIF":0.0,"publicationDate":"2024-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10517955","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140836500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-07DOI: 10.1109/OJCAS.2024.3358107
Nicole McFarlane
Welcome to the 5th volume of the Open Journal of Circuits and Systems (OJCAS). The Circuits and Systems Society’s Gold Open Access Journal is maturing, welcoming more submissions and getting our first impact factor score. I welcome our new Associate Editor in Chief, Alex James of Digital University Kerala in Trivandrum India to help mature the journal even more. As the journal matures, it is important to note that OJCAS covers all the topics of the society with the only exception being that it is open access. This means we hold submissions to the same quality standard as the other IEEE Journals. As soon as the paper is accepted, the paper is immediately available on IEEE Xplore and freely available to all researchers across the globe. In order to cover the cost of hosting the papers, as well as minimal editing and formatting, the article processing charges are indeed higher than traditional journals. Fortunately, many institutions have open access funds to cover this purpose and some funding agencies in certain countries mandate that research funded by those agencies be freely available to the public. In addition, IEEE has a waiver policy for authors from low and lower-middle income countries. More facts about open access for IEEE can be found at https://open.ieee.org/about/faqs/ .
{"title":"Welcome to the 5th Volume of the Open Journal of Circuits and Systems","authors":"Nicole McFarlane","doi":"10.1109/OJCAS.2024.3358107","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3358107","url":null,"abstract":"Welcome to the 5th volume of the Open Journal of Circuits and Systems (OJCAS). The Circuits and Systems Society’s Gold Open Access Journal is maturing, welcoming more submissions and getting our first impact factor score. I welcome our new Associate Editor in Chief, Alex James of Digital University Kerala in Trivandrum India to help mature the journal even more. As the journal matures, it is important to note that OJCAS covers all the topics of the society with the only exception being that it is open access. This means we hold submissions to the same quality standard as the other IEEE Journals. As soon as the paper is accepted, the paper is immediately available on IEEE Xplore and freely available to all researchers across the globe. In order to cover the cost of hosting the papers, as well as minimal editing and formatting, the article processing charges are indeed higher than traditional journals. Fortunately, many institutions have open access funds to cover this purpose and some funding agencies in certain countries mandate that research funded by those agencies be freely available to the public. In addition, IEEE has a waiver policy for authors from low and lower-middle income countries. More facts about open access for IEEE can be found at \u0000<uri>https://open.ieee.org/about/faqs/</uri>\u0000.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2024-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10423924","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139704434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The trade-off between decoding performance and hardware costs has been a long-standing challenge in Low-Density Parity Check (LDPC) decoding. Based on model-driven methodology, the Neural Network-Aided Variable Weight Min-Sum (NN-aided vwMS) algorithm is proposed to address this dilemma in this paper. Not only eliminating the second minimum value in the check node update process for reducing hardware complexity, our approach featuring a fast-convergent shuffled scheduling method proposed to enhance convergence speed can also maintain similar decoding performance as compared to the traditional normalized min-sum algorithm. Different from existing model-driven methodologies only suitable for short codes, a Globally-Coupled Like (GC-like) LDPC code construction is presented to enable efficient training with simplified neural networks for longer LDPC codes. To demonstrate the capability of the NN-aided vwMS algorithm with the fast-convergent shuffled scheduling method, a GC-like (9126,8197) LDPC decoder is implemented for NAND flash applications, achieving a 6.56 Gbps throughput with a core area of $0.58~mm^{2}$ under the 40-nm CMOS TSMC process, and average power consumption of 288 mW under the frame error rate of $2.64 times 10^{-5}$ at 4.5dB. Our decoder architecture achieves a superior normalized throughput-to-area ratio of $11.31~Gbps/mm^{2}$ , demonstrating a 2.4x improvement among previous works.
{"title":"GC-Like LDPC Code Construction and its NN-Aided Decoder Implementation","authors":"Yu-Lun Hsu;Li-Wei Liu;Yen-Chin Liao;Hsie-Chia Chang","doi":"10.1109/OJCAS.2024.3363043","DOIUrl":"10.1109/OJCAS.2024.3363043","url":null,"abstract":"The trade-off between decoding performance and hardware costs has been a long-standing challenge in Low-Density Parity Check (LDPC) decoding. Based on model-driven methodology, the Neural Network-Aided Variable Weight Min-Sum (NN-aided vwMS) algorithm is proposed to address this dilemma in this paper. Not only eliminating the second minimum value in the check node update process for reducing hardware complexity, our approach featuring a fast-convergent shuffled scheduling method proposed to enhance convergence speed can also maintain similar decoding performance as compared to the traditional normalized min-sum algorithm. Different from existing model-driven methodologies only suitable for short codes, a Globally-Coupled Like (GC-like) LDPC code construction is presented to enable efficient training with simplified neural networks for longer LDPC codes. To demonstrate the capability of the NN-aided vwMS algorithm with the fast-convergent shuffled scheduling method, a GC-like (9126,8197) LDPC decoder is implemented for NAND flash applications, achieving a 6.56 Gbps throughput with a core area of \u0000<inline-formula> <tex-math>$0.58~mm^{2}$ </tex-math></inline-formula>\u0000 under the 40-nm CMOS TSMC process, and average power consumption of 288 mW under the frame error rate of \u0000<inline-formula> <tex-math>$2.64 times 10^{-5}$ </tex-math></inline-formula>\u0000 at 4.5dB. Our decoder architecture achieves a superior normalized throughput-to-area ratio of \u0000<inline-formula> <tex-math>$11.31~Gbps/mm^{2}$ </tex-math></inline-formula>\u0000, demonstrating a 2.4x improvement among previous works.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"189-198"},"PeriodicalIF":0.0,"publicationDate":"2024-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10423290","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139956583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-30DOI: 10.1109/OJCAS.2024.3360257
Kamilya Smagulova;Mohammed E. Fouda;Ahmed Eltawil
The high speed, scalability, and parallelism offered by ReRAM crossbar arrays foster the development of ReRAM-based next-generation AI accelerators. At the same time, the sensitivity of ReRAM to temperature variations decreases $text{R}_{ON}/text{R}_{OFF}$ ratio and negatively affects the achieved accuracy and reliability of the hardware. Various works on temperature-aware optimization and remapping in ReRAM crossbar arrays reported up to 58% improvement in accuracy and $2.39times $ ReRAM lifetime enhancement. This paper classifies the challenges caused by thermal heat, starting from constraints in ReRAM cells’ dimensions and characteristics to their placement in the architecture. In addition, it reviews the available solutions designed to mitigate the impact of these challenges, including emerging temperature-resilient Deep Neural Network (DNN) training methods. Our work also provides a summary of the techniques and their advantages and limitations.
{"title":"Thermal Heating in ReRAM Crossbar Arrays: Challenges and Solutions","authors":"Kamilya Smagulova;Mohammed E. Fouda;Ahmed Eltawil","doi":"10.1109/OJCAS.2024.3360257","DOIUrl":"https://doi.org/10.1109/OJCAS.2024.3360257","url":null,"abstract":"The high speed, scalability, and parallelism offered by ReRAM crossbar arrays foster the development of ReRAM-based next-generation AI accelerators. At the same time, the sensitivity of ReRAM to temperature variations decreases \u0000<inline-formula> <tex-math>$text{R}_{ON}/text{R}_{OFF}$ </tex-math></inline-formula>\u0000 ratio and negatively affects the achieved accuracy and reliability of the hardware. Various works on temperature-aware optimization and remapping in ReRAM crossbar arrays reported up to 58% improvement in accuracy and \u0000<inline-formula> <tex-math>$2.39times $ </tex-math></inline-formula>\u0000 ReRAM lifetime enhancement. This paper classifies the challenges caused by thermal heat, starting from constraints in ReRAM cells’ dimensions and characteristics to their placement in the architecture. In addition, it reviews the available solutions designed to mitigate the impact of these challenges, including emerging temperature-resilient Deep Neural Network (DNN) training methods. Our work also provides a summary of the techniques and their advantages and limitations.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"28-41"},"PeriodicalIF":0.0,"publicationDate":"2024-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10416883","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139942726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-27DOI: 10.1109/OJCAS.2023.3347544
Yu-Xin Liu;Shih-Jie Jihang;Yeong-Luh Ueng
For K-best multiple-input multiple-output (MIMO) detection using real-valued decomposition (RVD), we need to obtain the $K$ surviving candidates from $K sqrt {M}$ candidates, where $M$ is the modulation order. This paper presents a sorter-free detection algorithm, where the $K$ surviving nodes can be obtained in ${mathrm {log_{2}}} {K}$ iterations, which is independent of modulation size. The $K sqrt {M}$ candidates are arranged into a multiple-layer table using the proposed path metric discretization. A bisection-based search algorithm is used to obtain the locations of the $K$ surviving candidates. A low-complexity fully-pipelined architecture is devised in order to implement the proposed MIMO detection without the need to use any dividers. In addition, an efficient method for storing information from child nodes is proposed, which requires significantly less storage space compared to the conventional Schnorr Euchner (SE) enumeration approach. Implementation results show that the proposed K-best MIMO detector supports a 6.4Gb/s throughput that has a $0.32~boldsymbol{mu }text{s}$ latency in a 90 nm process for a 256-quadrature amplitude modulation (QAM) 4 $times $ 4 MIMO system. In addition, compared to the sorter-based baseline detector, the proposed detector improves the hardware efficiency by 77%.
{"title":"An Efficient K-Best MIMO Detector for Large Modulation Constellations","authors":"Yu-Xin Liu;Shih-Jie Jihang;Yeong-Luh Ueng","doi":"10.1109/OJCAS.2023.3347544","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3347544","url":null,"abstract":"For K-best multiple-input multiple-output (MIMO) detection using real-valued decomposition (RVD), we need to obtain the \u0000<inline-formula> <tex-math>$K$ </tex-math></inline-formula>\u0000 surviving candidates from \u0000<inline-formula> <tex-math>$K sqrt {M}$ </tex-math></inline-formula>\u0000 candidates, where \u0000<inline-formula> <tex-math>$M$ </tex-math></inline-formula>\u0000 is the modulation order. This paper presents a sorter-free detection algorithm, where the \u0000<inline-formula> <tex-math>$K$ </tex-math></inline-formula>\u0000 surviving nodes can be obtained in \u0000<inline-formula> <tex-math>${mathrm {log_{2}}} {K}$ </tex-math></inline-formula>\u0000 iterations, which is independent of modulation size. The \u0000<inline-formula> <tex-math>$K sqrt {M}$ </tex-math></inline-formula>\u0000 candidates are arranged into a multiple-layer table using the proposed path metric discretization. A bisection-based search algorithm is used to obtain the locations of the \u0000<inline-formula> <tex-math>$K$ </tex-math></inline-formula>\u0000 surviving candidates. A low-complexity fully-pipelined architecture is devised in order to implement the proposed MIMO detection without the need to use any dividers. In addition, an efficient method for storing information from child nodes is proposed, which requires significantly less storage space compared to the conventional Schnorr Euchner (SE) enumeration approach. Implementation results show that the proposed K-best MIMO detector supports a 6.4Gb/s throughput that has a \u0000<inline-formula> <tex-math>$0.32~boldsymbol{mu }text{s}$ </tex-math></inline-formula>\u0000 latency in a 90 nm process for a 256-quadrature amplitude modulation (QAM) 4\u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u00004 MIMO system. In addition, compared to the sorter-based baseline detector, the proposed detector improves the hardware efficiency by 77%.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"2-16"},"PeriodicalIF":0.0,"publicationDate":"2023-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10375268","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139704456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-19DOI: 10.1109/OJCAS.2023.3344094
Yu-Han Sun;Chiang Lo-Hsuan Lee;Tian-Sheuan Chang
Image prefiltering with just noticeable distortion (JND) improves coding efficiency in a visual lossless way by filtering the perceptually redundant information prior to compression. However, real JND cannot be well modeled with inaccurate masking equations in traditional approaches or image-level subject tests in deep learning approaches. Thus, this paper proposes a fine-grained JND prefiltering dataset guided by image quality assessment for accurate block-level JND modeling. The dataset is constructed from decoded images to include coding effects and is also perceptually enhanced with block overlap and edge preservation. Furthermore, based on this dataset, we propose a lightweight JND prefiltering network, IQNet, which can be applied directly to different quantization cases with the same model and only needs 3K parameters. The experimental results show that the proposed approach to Versatile Video Coding could yield maximum/average bitrate savings of 41%/15% and 53%/19% for all-intra and low-delay P configurations, respectively, with negligible subjective quality loss. Our method demonstrates higher perceptual quality and a model size that is an order of magnitude smaller than previous deep learning methods.
{"title":"IQNet: Image Quality Assessment Guided Just Noticeable Difference Prefiltering for Versatile Video Coding","authors":"Yu-Han Sun;Chiang Lo-Hsuan Lee;Tian-Sheuan Chang","doi":"10.1109/OJCAS.2023.3344094","DOIUrl":"10.1109/OJCAS.2023.3344094","url":null,"abstract":"Image prefiltering with just noticeable distortion (JND) improves coding efficiency in a visual lossless way by filtering the perceptually redundant information prior to compression. However, real JND cannot be well modeled with inaccurate masking equations in traditional approaches or image-level subject tests in deep learning approaches. Thus, this paper proposes a fine-grained JND prefiltering dataset guided by image quality assessment for accurate block-level JND modeling. The dataset is constructed from decoded images to include coding effects and is also perceptually enhanced with block overlap and edge preservation. Furthermore, based on this dataset, we propose a lightweight JND prefiltering network, IQNet, which can be applied directly to different quantization cases with the same model and only needs 3K parameters. The experimental results show that the proposed approach to Versatile Video Coding could yield maximum/average bitrate savings of 41%/15% and 53%/19% for all-intra and low-delay P configurations, respectively, with negligible subjective quality loss. Our method demonstrates higher perceptual quality and a model size that is an order of magnitude smaller than previous deep learning methods.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"17-27"},"PeriodicalIF":0.0,"publicationDate":"2023-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10365509","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138998504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-04DOI: 10.1109/OJCAS.2023.3338639
Onur Toker
In this paper, we consider the difficulty of cyberattack detection with $d$ sensors and $n$ observations, and derive performance bounds that are valid independent of the attack detection algorithm used. In other words, regardless of whether it is an artificial intelligence (AI) or sensor fusion based approach or it is derived using a completely new innovative idea, a cyberattack detector using multiple observations does have certain fundamental performance bounds that are independent of the algorithm used. Cyberattacks introduce different forms of anomalies that may be small or large, and given enough measured data, even tiny anomalies will become more noticeable and cyberattack detection problem will be easier provided that a carefully designed attack detection algorithm is used. For example, False Data Injection (FDI) attacks with small injected error may be harder to detect, but such attacks can cause major failures if continued over a long time period. A natural question to ask is to what degree the cyberattack detection problem becomes easier if more and more measurements acquired over a long time period are used for threat assessment, and the risk level reduction achieved for each new observation. For a cyberattack detector, the false alarm rate is the probability of triggering an alarm when there is no cyberattack, and the probability of miss is the probability of not detecting a cyberattack. The risk level of a cyberattack detector is defined as the sum of the probability of false alarm and the probability of miss. By using the notion of Hellinger distance and total variation norm between probability distributions, we derive upper and lower bounds for the minimum possible (achievable) risk level under multiple measurements, and study asymptotic properties of such bounds. These performance bounds are valid regardless of the cyberattack detection algorithm selection; they imply certain fundamental performance limits in cyberattack detection applications with given number of observations; and also help us to understand the number of observations needed for a given cyberattack detection performance level.
{"title":"Asymptotic Performance Limitations in Cyberattack Detection","authors":"Onur Toker","doi":"10.1109/OJCAS.2023.3338639","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3338639","url":null,"abstract":"In this paper, we consider the difficulty of cyberattack detection with \u0000<inline-formula> <tex-math>$d$ </tex-math></inline-formula>\u0000 sensors and \u0000<inline-formula> <tex-math>$n$ </tex-math></inline-formula>\u0000 observations, and derive performance bounds that are valid independent of the attack detection algorithm used. In other words, regardless of whether it is an artificial intelligence (AI) or sensor fusion based approach or it is derived using a completely new innovative idea, a cyberattack detector using multiple observations does have certain fundamental performance bounds that are independent of the algorithm used. Cyberattacks introduce different forms of anomalies that may be small or large, and given enough measured data, even tiny anomalies will become more noticeable and cyberattack detection problem will be easier provided that a carefully designed attack detection algorithm is used. For example, False Data Injection (FDI) attacks with small injected error may be harder to detect, but such attacks can cause major failures if continued over a long time period. A natural question to ask is to what degree the cyberattack detection problem becomes easier if more and more measurements acquired over a long time period are used for threat assessment, and the risk level reduction achieved for each new observation. For a cyberattack detector, the false alarm rate is the probability of triggering an alarm when there is no cyberattack, and the probability of miss is the probability of not detecting a cyberattack. The risk level of a cyberattack detector is defined as the sum of the probability of false alarm and the probability of miss. By using the notion of Hellinger distance and total variation norm between probability distributions, we derive upper and lower bounds for the minimum possible (achievable) risk level under multiple measurements, and study asymptotic properties of such bounds. These performance bounds are valid regardless of the cyberattack detection algorithm selection; they imply certain fundamental performance limits in cyberattack detection applications with given number of observations; and also help us to understand the number of observations needed for a given cyberattack detection performance level.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"336-346"},"PeriodicalIF":0.0,"publicationDate":"2023-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10339844","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139034311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-01DOI: 10.1109/OJCAS.2023.3338210
Yudhajit Ray;Shreyas Sen
Recent advancements in low power and low noise front-end amplifiers have made it possible to support high-speed data transmission within the deep roll-off regions of conventional wireline channels. Despite being primarily limited by inter-symbol-interference (ISI), these legacy channels also require power-consuming front-end amplifiers due to increased insertion-loss at high frequencies. Wireline-like broadband channels, such as proximity communication and human-body-communication (HBC), as well as multi-lane, densely-packed channels, are further constrained by their high loss and unique channel responses which cause the received signal to be noise-limited. To address these challenges, this paper proposes the use of a discrete-time integrating amplifier as a low power <1 pJ/b using 65nm CMOS up to 5-6 Gb/s) alternative to traditional continuous-time front-end amplifiers. Integrating amplifiers also reduce the effects of noise due to its inherent current integrating process. The paper provides a detailed mathematical analysis of gain of two conventional and three novel and improved integrating amplifiers, accurate input referred noise estimations, signal-to-noise ratio, and a comparison of the integrating amplifier’s performance with that of a low-noise amplifier. The analysis identifies the most optimum integrator architecture and provides comparison with simulated results. This paper also develops theoretical expressions and provides in-depth understanding of input referred noise, while supporting them by simulations using 65nm CMOS technology node. Finally, a comparative analysis between low-noise amplifier and discrete-time integrating amplifier is presented to demonstrate power and noise benefits for both legacy and wireline-like channels, while providing an easier design space as integrator provides two-dimensional controllability for gain.
{"title":"Analysis of Discrete-Time Integrating Amplifiers as an Alternative to Continuous-Time Amplifiers in Broadband Receivers","authors":"Yudhajit Ray;Shreyas Sen","doi":"10.1109/OJCAS.2023.3338210","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3338210","url":null,"abstract":"Recent advancements in low power and low noise front-end amplifiers have made it possible to support high-speed data transmission within the deep roll-off regions of conventional wireline channels. Despite being primarily limited by inter-symbol-interference (ISI), these legacy channels also require power-consuming front-end amplifiers due to increased insertion-loss at high frequencies. Wireline-like broadband channels, such as proximity communication and human-body-communication (HBC), as well as multi-lane, densely-packed channels, are further constrained by their high loss and unique channel responses which cause the received signal to be noise-limited. To address these challenges, this paper proposes the use of a discrete-time integrating amplifier as a low power <1 pJ/b using 65nm CMOS up to 5-6 Gb/s) alternative to traditional continuous-time front-end amplifiers. Integrating amplifiers also reduce the effects of noise due to its inherent current integrating process. The paper provides a detailed mathematical analysis of gain of two conventional and three novel and improved integrating amplifiers, accurate input referred noise estimations, signal-to-noise ratio, and a comparison of the integrating amplifier’s performance with that of a low-noise amplifier. The analysis identifies the most optimum integrator architecture and provides comparison with simulated results. This paper also develops theoretical expressions and provides in-depth understanding of input referred noise, while supporting them by simulations using 65nm CMOS technology node. Finally, a comparative analysis between low-noise amplifier and discrete-time integrating amplifier is presented to demonstrate power and noise benefits for both legacy and wireline-like channels, while providing an easier design space as integrator provides two-dimensional controllability for gain.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"347-362"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10337627","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139034346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-27DOI: 10.1109/OJCAS.2023.3335400
Ahmed Abdelaziz;Mohamed Ahmed;Tawfiq Musah
This paper proposes a hybrid phase detector for use in multilevel timing recovery systems. The proposed approach suppresses errant zero-crossings associated with multilevel baud rate phase detectors and ensures maximum signal swing in lock, with minimal hardware and power overhead. Analysis and simulation results in a 28nm CMOS process are used to explore the functionality of proposed phase detector and demonstrate its effectiveness in achieving superior performance to the conventional approach.Clock and data recovery (CDR) loop simulations show that the proposed phase detector enables $1.36times $ increase in vertical eye margin while maintaining similar steady-state RMS jitter and compared to the conventional approach. The simulations also show effective suppression of unwanted phase detector zero-crossing, while achieving comparable acquisition bandwidth to the conventional approach.
{"title":"Hybrid Timing Error Detector for Baud Rate Multilevel Clock and Data Recovery","authors":"Ahmed Abdelaziz;Mohamed Ahmed;Tawfiq Musah","doi":"10.1109/OJCAS.2023.3335400","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3335400","url":null,"abstract":"This paper proposes a hybrid phase detector for use in multilevel timing recovery systems. The proposed approach suppresses errant zero-crossings associated with multilevel baud rate phase detectors and ensures maximum signal swing in lock, with minimal hardware and power overhead. Analysis and simulation results in a 28nm CMOS process are used to explore the functionality of proposed phase detector and demonstrate its effectiveness in achieving superior performance to the conventional approach.Clock and data recovery (CDR) loop simulations show that the proposed phase detector enables \u0000<inline-formula> <tex-math>$1.36times $ </tex-math></inline-formula>\u0000 increase in vertical eye margin while maintaining similar steady-state RMS jitter and compared to the conventional approach. The simulations also show effective suppression of unwanted phase detector zero-crossing, while achieving comparable acquisition bandwidth to the conventional approach.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"324-335"},"PeriodicalIF":0.0,"publicationDate":"2023-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10329284","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138558174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-15DOI: 10.1109/OJCAS.2023.3332853
Hamza Al Maharmeh;Nabil J. Sarhan;Mohammed Ismail;Mohammad Alhawari
The increasing demand for high performance and energy efficiency in Artificial Neural Networks (ANNs) accelerators has driven a wide range of application-specific integrated circuits (ASICs). Besides, the rapid deployment of low-power IoT devices requires highly efficient computing, which as a result urges the need to explore low-power hardware implementations in different domains. This paper proposes a spatially unrolled time-domain accelerator that uses an ultra-low-power digital-to-time converter (DTC) while occupying an active area of 0.201 mm2. The proposed DTC is implemented using a Laddered, Inverter (LI) circuit, which consumes 3 $times $ less power than the conventional inverter-based DTC and provides reliable performance across different process corners, supply voltages, and temperature variations. Post-synthesis results in 65nm CMOS show that the proposed core achieves a superior energy efficiency of 116 TOPS/W, a throughput of 4 GOPS, and an area efficiency of 20 GOPS/mm2. The proposed core improves energy efficiency by 2.4 - 47 $times $ compared to prior time-domain accelerators.
{"title":"A 116 TOPS/W Spatially Unrolled Time-Domain Accelerator Utilizing Laddered-Inverter DTC for Energy-Efficient Edge Computing in 65 nm","authors":"Hamza Al Maharmeh;Nabil J. Sarhan;Mohammed Ismail;Mohammad Alhawari","doi":"10.1109/OJCAS.2023.3332853","DOIUrl":"10.1109/OJCAS.2023.3332853","url":null,"abstract":"The increasing demand for high performance and energy efficiency in Artificial Neural Networks (ANNs) accelerators has driven a wide range of application-specific integrated circuits (ASICs). Besides, the rapid deployment of low-power IoT devices requires highly efficient computing, which as a result urges the need to explore low-power hardware implementations in different domains. This paper proposes a spatially unrolled time-domain accelerator that uses an ultra-low-power digital-to-time converter (DTC) while occupying an active area of 0.201 mm2. The proposed DTC is implemented using a Laddered, Inverter (LI) circuit, which consumes 3\u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 less power than the conventional inverter-based DTC and provides reliable performance across different process corners, supply voltages, and temperature variations. Post-synthesis results in 65nm CMOS show that the proposed core achieves a superior energy efficiency of 116 TOPS/W, a throughput of 4 GOPS, and an area efficiency of 20 GOPS/mm2. The proposed core improves energy efficiency by 2.4 - 47\u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 compared to prior time-domain accelerators.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"308-323"},"PeriodicalIF":0.0,"publicationDate":"2023-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10318175","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135710807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：