Pub Date : 2022-03-12DOI: 10.1109/OJCAS.2022.3174632
Laura Falaschetti;Lorenzo Manoni;Claudio Turchetti
Real-time semantic segmentation on embedded devices has recently enjoyed significant gain in popularity, due to the increasing interest in smart vehicles and smart robots. In particular, with the emergence of autonomous driving, low latency and computation-intensive operations lead to new challenges for vehicles and robots, such as excessive computing power and energy consumption. The aim of this paper is to address semantic segmentation, one of the most critical tasks for the perception of the environment, and its implementation in a low power core, by preserving the required performance of accuracy and low complexity. To reach this goal a low-rank convolutional neural network (CNN) architecture for real-time semantic segmentation is proposed. The main contributions of this paper are: i) a tensor decomposition technique has been applied to the kernel of a generic convolutional layer, ii) three versions of an optimized architecture, that combines UNet and ResNet models, have been derived to explore the trade-off between model complexity and accuracy, iii) the low-rank CNN architectures have been implemented in a Raspberry Pi 4 and NVIDIA Jetson Nano 2 GB embedded platforms, as severe benchmarks to meet the low-power, low-cost requirements, and in the high-cost GPU NVIDIA Tesla P100 PCIe 16 GB to meet the best performance.
由于对智能车辆和智能机器人的兴趣日益浓厚，嵌入式设备上的实时语义分割最近得到了显著的普及。特别是，随着自动驾驶的出现，低延迟和计算密集型操作给车辆和机器人带来了新的挑战，例如过度的计算能力和能耗。本文的目的是解决语义分割，这是感知环境的最关键任务之一，并通过保持所需的准确性和低复杂性的性能，在低功耗核心中实现。为了实现这一目标，提出了一种用于实时语义分割的低秩卷积神经网络(CNN)架构。本文的主要贡献有:i)将张量分解技术应用于通用卷积层的内核;ii)导出了三个版本的优化架构，结合UNet和ResNet模型，以探索模型复杂性和准确性之间的权衡;iii)低秩CNN架构已在Raspberry Pi 4和NVIDIA Jetson Nano 2gb嵌入式平台上实现，作为满足低功耗，低成本要求的严格基准。而在高成本的GPU NVIDIA Tesla P100 PCIe 16gb满足最佳性能。
{"title":"A Low-Rank CNN Architecture for Real-Time Semantic Segmentation in Visual SLAM Applications","authors":"Laura Falaschetti;Lorenzo Manoni;Claudio Turchetti","doi":"10.1109/OJCAS.2022.3174632","DOIUrl":"10.1109/OJCAS.2022.3174632","url":null,"abstract":"Real-time semantic segmentation on embedded devices has recently enjoyed significant gain in popularity, due to the increasing interest in smart vehicles and smart robots. In particular, with the emergence of autonomous driving, low latency and computation-intensive operations lead to new challenges for vehicles and robots, such as excessive computing power and energy consumption. The aim of this paper is to address semantic segmentation, one of the most critical tasks for the perception of the environment, and its implementation in a low power core, by preserving the required performance of accuracy and low complexity. To reach this goal a low-rank convolutional neural network (CNN) architecture for real-time semantic segmentation is proposed. The main contributions of this paper are: \u0000<italic>i)</i>\u0000 a tensor decomposition technique has been applied to the kernel of a generic convolutional layer, \u0000<italic>ii)</i>\u0000 three versions of an optimized architecture, that combines UNet and ResNet models, have been derived to explore the trade-off between model complexity and accuracy, \u0000<italic>iii)</i>\u0000 the low-rank CNN architectures have been implemented in a Raspberry Pi 4 and NVIDIA Jetson Nano 2 GB embedded platforms, as severe benchmarks to meet the low-power, low-cost requirements, and in the high-cost GPU NVIDIA Tesla P100 PCIe 16 GB to meet the best performance.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9773325","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62852634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-03-12DOI: 10.1109/OJCAS.2022.3146994
Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
未来的作者被要求提交新的，未发表的手稿，包括在即将到来的事件中描述的这篇论文。
{"title":"IEEE Circuits and Systems Society","authors":"","doi":"10.1109/OJCAS.2022.3146994","DOIUrl":"https://doi.org/10.1109/OJCAS.2022.3146994","url":null,"abstract":"Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9774340","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138137912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-03-12DOI: 10.1109/OJCAS.2022.3174694
Christopher G. Daniel;Thomas P. Weldon
The recent discovery that the input impedance of digital impedance circuits is dependent on the external source impedance requires the development of new design procedures to address the significant complexity of this discovery. These circuits are of particular utility for the implementation of difficult non-Foster impedances such as negative capacitance. Therefore, a new digital impedance circuit design procedure is presented where stable digital filter coefficients are computed to provide desired digital impedance values at two chosen frequencies, given that a stable solution exists. The new design procedure explicitly addresses the aforementioned dependence on the external source impedance for digital impedance circuits with resistive sources. Lastly, simulation results from a negative capacitance design example are compared to the new theory to confirm the efficacy of the new design procedure.
{"title":"A Stable Digital Impedance Circuit Design Method for Resistive Source Impedances","authors":"Christopher G. Daniel;Thomas P. Weldon","doi":"10.1109/OJCAS.2022.3174694","DOIUrl":"10.1109/OJCAS.2022.3174694","url":null,"abstract":"The recent discovery that the input impedance of digital impedance circuits is dependent on the external source impedance requires the development of new design procedures to address the significant complexity of this discovery. These circuits are of particular utility for the implementation of difficult non-Foster impedances such as negative capacitance. Therefore, a new digital impedance circuit design procedure is presented where stable digital filter coefficients are computed to provide desired digital impedance values at two chosen frequencies, given that a stable solution exists. The new design procedure explicitly addresses the aforementioned dependence on the external source impedance for digital impedance circuits with resistive sources. Lastly, simulation results from a negative capacitance design example are compared to the new theory to confirm the efficacy of the new design procedure.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9773326","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62853192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-03-11DOI: 10.1109/OJCAS.2022.3173686
Mohammad Emami Meybodi;Hector Gomez;Yu-Chun Lu;Hossein Shakiba;Ali Sheikholeslami
This paper proposes a novel design for Maximum Likelihood Sequence Estimation (MLSE) used in ultra-high-speed wireline communication. We take advantage of the propagated errors caused by Decision-Feedback Equalizer (DFE) to activate and guide the MLSE, thereby reducing its complexity. The design is customized for a 4-PAM, 1 + D signaling system, and synthesized in 16nm FinFET TSMC Technology. For comparison purposes, a conventional MLSE is also synthesized in the same technology. The synthesis report confirms that the proposed design consumes 1/10 of the power and occupies 1/15 of the area required by the conventional MLSE while having a comparable bit error rate.
{"title":"Design and Implementation of an On-Demand Maximum-Likelihood Sequence Estimation (MLSE)","authors":"Mohammad Emami Meybodi;Hector Gomez;Yu-Chun Lu;Hossein Shakiba;Ali Sheikholeslami","doi":"10.1109/OJCAS.2022.3173686","DOIUrl":"10.1109/OJCAS.2022.3173686","url":null,"abstract":"This paper proposes a novel design for Maximum Likelihood Sequence Estimation (MLSE) used in ultra-high-speed wireline communication. We take advantage of the propagated errors caused by Decision-Feedback Equalizer (DFE) to activate and guide the MLSE, thereby reducing its complexity. The design is customized for a 4-PAM, 1 + D signaling system, and synthesized in 16nm FinFET TSMC Technology. For comparison purposes, a conventional MLSE is also synthesized in the same technology. The synthesis report confirms that the proposed design consumes 1/10 of the power and occupies 1/15 of the area required by the conventional MLSE while having a comparable bit error rate.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9772752","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62853002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-28DOI: 10.1109/OJCAS.2022.3152671
Federico Bizzarri;Paolo Nora;Angelo Brambilla
In this paper, we focus on instability issues of a wide-input-range Constant ON-Time buck converter. A transconductance stage in the control path that implements ripple compensation characterizes the architecture of this switching circuit. On the whole, decision rules, that heavily influence stability, govern the dynamical evolution of the converter. We show the onset of sub-harmonic oscillations and pulse-bursting caused by the presence of hysteresis in the regulation comparator. Operational boundaries are provided both in analytical and numerical form. They easily support the designer in choosing the converter parameter values. Theoretical results are verified against SIMetrix/SIMPLIS and MPLAB® Mindi™ simulations for a case study involving a commercial adjustable-frequency, synchronous buck regulator featuring an adaptive ON-time control architecture. A good agreement is obtained, as shown.
{"title":"Stability Boundaries of Wide-Input-Range COT Buck Converters With Ripple Compensation","authors":"Federico Bizzarri;Paolo Nora;Angelo Brambilla","doi":"10.1109/OJCAS.2022.3152671","DOIUrl":"10.1109/OJCAS.2022.3152671","url":null,"abstract":"In this paper, we focus on instability issues of a wide-input-range Constant ON-Time buck converter. A transconductance stage in the control path that implements ripple compensation characterizes the architecture of this switching circuit. On the whole, decision rules, that heavily influence stability, govern the dynamical evolution of the converter. We show the onset of sub-harmonic oscillations and pulse-bursting caused by the presence of hysteresis in the regulation comparator. Operational boundaries are provided both in analytical and numerical form. They easily support the designer in choosing the converter parameter values. Theoretical results are verified against SIMetrix/SIMPLIS and MPLAB® Mindi™ simulations for a case study involving a commercial adjustable-frequency, synchronous buck regulator featuring an adaptive ON-time control architecture. A good agreement is obtained, as shown.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9722359","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62852849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-25DOI: 10.1109/OJCAS.2022.3154062
Qingnan Yu;Tony Chan Carusone;Antonio Liscidini
Digital mismatch calibration for quantized analog (QA) signal processing is proposed for the first time. Since the proposed calibration mechanism does not require uniform QA slicer levels, non-uniform quantization can be applied to improve the system performance. We propose two methods utilizing the genetic algorithm and $mu $ -law to find non-uniform slicer levels offering superior performance compared to uniform levels. Simulations show that for a QA amplifier consisting of 32 slices, the signal-to-noise-and-distortion ratio (SNDR) under a multitone input can be doubled by adjusting only the quantization levels while maintaining the same structure and same power, compared to uniform quantization levels that provide 54 dB of SNDR.
{"title":"Optimization of Quantized Analog Signal Processing Using Genetic Algorithms and μ-Law","authors":"Qingnan Yu;Tony Chan Carusone;Antonio Liscidini","doi":"10.1109/OJCAS.2022.3154062","DOIUrl":"10.1109/OJCAS.2022.3154062","url":null,"abstract":"Digital mismatch calibration for quantized analog (QA) signal processing is proposed for the first time. Since the proposed calibration mechanism does not require uniform QA slicer levels, non-uniform quantization can be applied to improve the system performance. We propose two methods utilizing the genetic algorithm and \u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000-law to find non-uniform slicer levels offering superior performance compared to uniform levels. Simulations show that for a QA amplifier consisting of 32 slices, the signal-to-noise-and-distortion ratio (SNDR) under a multitone input can be doubled by adjusting only the quantization levels while maintaining the same structure and same power, compared to uniform quantization levels that provide 54 dB of SNDR.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9721424","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62852938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-17DOI: 10.1109/OJCAS.2022.3152399
Josh Goldsmith;Louise H. Crockett;Robert W. Stewart
We present a natively fixed-point filter design method that targets FPGA-based Reconfigurable Finite Impulse Response (RFIR) filters for Software Defined Radio applications. The Filter Designer is capable of reconfiguring cut-off frequencies on-the-fly at run-time; with other parameters, such as filter length and window type, configurable at compile-time. The ability to compute filter coefficients directly on FPGAs is compelling, as much lower latencies can be achieved when compared to RFIRs programmed with embedded processors. In this work we discuss several filter design techniques from the literature and investigate their suitability for implementation on FPGAs. A hybrid method combining window and frequency sampling methods is developed and implemented on a Xilinx Zynq-7000 SoC. We explore the limitations of designing filters in fixed-point arithmetic and consider the effects filter length and wordlength have on filter quality. Results show that the proposed algorithm generates good-quality filters that display stopband attenuation up to 88dB, transition bandwidths less than 1% of the sample rate, and low resource utilisation. Most notably, we found that our method is up to three orders of magnitude faster than an equivalent software implementation, with execution times as low as 2.52 $mu text{s}$ , enabling radio applications in which latency is a principal constraint.
{"title":"A Natively Fixed-Point Run-Time Reconfigurable FIR Filter Design Method for FPGA Hardware","authors":"Josh Goldsmith;Louise H. Crockett;Robert W. Stewart","doi":"10.1109/OJCAS.2022.3152399","DOIUrl":"10.1109/OJCAS.2022.3152399","url":null,"abstract":"We present a natively fixed-point filter design method that targets FPGA-based Reconfigurable Finite Impulse Response (RFIR) filters for Software Defined Radio applications. The Filter Designer is capable of reconfiguring cut-off frequencies on-the-fly at run-time; with other parameters, such as filter length and window type, configurable at compile-time. The ability to compute filter coefficients directly on FPGAs is compelling, as much lower latencies can be achieved when compared to RFIRs programmed with embedded processors. In this work we discuss several filter design techniques from the literature and investigate their suitability for implementation on FPGAs. A hybrid method combining window and frequency sampling methods is developed and implemented on a Xilinx Zynq-7000 SoC. We explore the limitations of designing filters in fixed-point arithmetic and consider the effects filter length and wordlength have on filter quality. Results show that the proposed algorithm generates good-quality filters that display stopband attenuation up to 88dB, transition bandwidths less than 1% of the sample rate, and low resource utilisation. Most notably, we found that our method is up to three orders of magnitude faster than an equivalent software implementation, with execution times as low as 2.52 \u0000<inline-formula> <tex-math>$mu text{s}$ </tex-math></inline-formula>\u0000, enabling radio applications in which latency is a principal constraint.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9716040","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62852595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-19DOI: 10.1109/OJCAS.2022.3142456
Gabriele Manganaro
Happy 2022 and welcome to the third volume of the IEEE Open Journal of Circuits and Systems (OJ-CAS).
2022年快乐，欢迎来到IEEE电路与系统开放期刊(OJ-CAS)第三卷。
{"title":"Editorial: Where Are We Now and Where Do We Go From Here","authors":"Gabriele Manganaro","doi":"10.1109/OJCAS.2022.3142456","DOIUrl":"10.1109/OJCAS.2022.3142456","url":null,"abstract":"Happy 2022 and welcome to the third volume of the IEEE Open Journal of Circuits and Systems (OJ-CAS).","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9684755","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80042251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study introduces a vision system that can acquire images at high speeds and high resolutions. Image sensors are used not only in digital still cameras but also in various applications that require capturing wide luminance differences beyond human perception. For example, fast, high-resolution object recognition, and motion tracking in automatic driving systems are essential, particularly in dark tunnels or the mid-summer sunshine. However, the resolution, frame rate, pixel size, and dynamic range should be traded off to achieve a high performance in capturing moving objects with a high contrast. We have developed a high-speed vision system with a readout operation of 1000 fps, resolution of 4K ${times },4text{K}$ , dynamic range of 110 dB, and fine pixels of $2.7~{mu }text{m}$ . These characteristics were achieved using several technologies such as 1) coded exposure (CE), which divides the image plane into smaller blocks and controls the exposure time of each block individually, 2) arrangement of analog-to-digital converters in parallel for each block, and 3) three-dimensional wafer stacking, which enables high-density integration of circuits and pixels. The proposed system can be applied in CE-based computational imaging in addition to high-dynamic-range applications for handling both the dark and bright areas in a scene.
{"title":"A Vision System With 1-inch 17-Mpixel 1000-fps Block-Controlled Coded-Exposure Stacked-CMOS Image Sensor for Computational Imaging and Adaptive Dynamic Range Control","authors":"Tomoki Hirata;Hironobu Murata;Taku Arii;Hideaki Matsuda;Hajime Yonemochi;Yojiro Tezuka;Shiro Tsunai","doi":"10.1109/OJCAS.2022.3213062","DOIUrl":"https://doi.org/10.1109/OJCAS.2022.3213062","url":null,"abstract":"This study introduces a vision system that can acquire images at high speeds and high resolutions. Image sensors are used not only in digital still cameras but also in various applications that require capturing wide luminance differences beyond human perception. For example, fast, high-resolution object recognition, and motion tracking in automatic driving systems are essential, particularly in dark tunnels or the mid-summer sunshine. However, the resolution, frame rate, pixel size, and dynamic range should be traded off to achieve a high performance in capturing moving objects with a high contrast. We have developed a high-speed vision system with a readout operation of 1000 fps, resolution of 4K ${times },4text{K}$ , dynamic range of 110 dB, and fine pixels of $2.7~{mu }text{m}$ . These characteristics were achieved using several technologies such as 1) coded exposure (CE), which divides the image plane into smaller blocks and controls the exposure time of each block individually, 2) arrangement of analog-to-digital converters in parallel for each block, and 3) three-dimensional wafer stacking, which enables high-density integration of circuits and pixels. The proposed system can be applied in CE-based computational imaging in addition to high-dynamic-range applications for handling both the dark and bright areas in a scene.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/9684754/09966408.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-01DOI: 10.1109/OJCAS.2022.3216780
Partha Sarathi Paul;Parker Hardy;Maisha Sadia;MD Sakib Hasan
In this paper, we have proposed the design of an analog two-dimensional (2D) discrete-time chaotic oscillator. 2D chaotic systems are studied because of their more complex chaotic behavior compared to one-dimensional (1D) chaotic systems. The already published works on 2D chaotic systems are mainly focused either on the complex analytical combinations of familiar 1D chaotic maps such as Sine map, Logistic map, Tent map, and so on, or off-the-shelf component-based analog circuits. Due to complex hardware requirements, neither of them is feasible for hardware-efficient integrated circuit (IC) implementations. To the best of our knowledge, this proposed work is the first-ever report of an analog 2D discrete-time chaotic oscillator design that is suitable for hardware-constrained IC implementations. The chaotic performance of the proposed design is analyzed with bifurcation plots, the transient response, 2D Lyapunov exponent, and correlation coefficient measurements. It is demonstrated that the proposed design exhibits promising chaotic behavior with low hardware cost. The real-world application of the proposed 2D chaotic oscillator is presented in a random number generator (RNG) design. The applicability of the RNG in cryptography is verified by passing the generated random sequence through four standard statistical tests namely, NIST, FIPS, TestU01, and Diehard.
{"title":"A 2D Chaotic Oscillator for Analog IC","authors":"Partha Sarathi Paul;Parker Hardy;Maisha Sadia;MD Sakib Hasan","doi":"10.1109/OJCAS.2022.3216780","DOIUrl":"https://doi.org/10.1109/OJCAS.2022.3216780","url":null,"abstract":"In this paper, we have proposed the design of an analog two-dimensional (2D) discrete-time chaotic oscillator. 2D chaotic systems are studied because of their more complex chaotic behavior compared to one-dimensional (1D) chaotic systems. The already published works on 2D chaotic systems are mainly focused either on the complex analytical combinations of familiar 1D chaotic maps such as Sine map, Logistic map, Tent map, and so on, or off-the-shelf component-based analog circuits. Due to complex hardware requirements, neither of them is feasible for hardware-efficient integrated circuit (IC) implementations. To the best of our knowledge, this proposed work is the first-ever report of an analog 2D discrete-time chaotic oscillator design that is suitable for hardware-constrained IC implementations. The chaotic performance of the proposed design is analyzed with bifurcation plots, the transient response, 2D Lyapunov exponent, and correlation coefficient measurements. It is demonstrated that the proposed design exhibits promising chaotic behavior with low hardware cost. The real-world application of the proposed 2D chaotic oscillator is presented in a random number generator (RNG) design. The applicability of the RNG in cryptography is verified by passing the generated random sequence through four standard statistical tests namely, NIST, FIPS, TestU01, and Diehard.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/9684754/09927335.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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