Pub Date : 2023-12-19DOI: 10.1109/OJCAS.2023.3344094
Yu-Han Sun;Chiang Lo-Hsuan Lee;Tian-Sheuan Chang
Image prefiltering with just noticeable distortion (JND) improves coding efficiency in a visual lossless way by filtering the perceptually redundant information prior to compression. However, real JND cannot be well modeled with inaccurate masking equations in traditional approaches or image-level subject tests in deep learning approaches. Thus, this paper proposes a fine-grained JND prefiltering dataset guided by image quality assessment for accurate block-level JND modeling. The dataset is constructed from decoded images to include coding effects and is also perceptually enhanced with block overlap and edge preservation. Furthermore, based on this dataset, we propose a lightweight JND prefiltering network, IQNet, which can be applied directly to different quantization cases with the same model and only needs 3K parameters. The experimental results show that the proposed approach to Versatile Video Coding could yield maximum/average bitrate savings of 41%/15% and 53%/19% for all-intra and low-delay P configurations, respectively, with negligible subjective quality loss. Our method demonstrates higher perceptual quality and a model size that is an order of magnitude smaller than previous deep learning methods.
{"title":"IQNet: Image Quality Assessment Guided Just Noticeable Difference Prefiltering for Versatile Video Coding","authors":"Yu-Han Sun;Chiang Lo-Hsuan Lee;Tian-Sheuan Chang","doi":"10.1109/OJCAS.2023.3344094","DOIUrl":"10.1109/OJCAS.2023.3344094","url":null,"abstract":"Image prefiltering with just noticeable distortion (JND) improves coding efficiency in a visual lossless way by filtering the perceptually redundant information prior to compression. However, real JND cannot be well modeled with inaccurate masking equations in traditional approaches or image-level subject tests in deep learning approaches. Thus, this paper proposes a fine-grained JND prefiltering dataset guided by image quality assessment for accurate block-level JND modeling. The dataset is constructed from decoded images to include coding effects and is also perceptually enhanced with block overlap and edge preservation. Furthermore, based on this dataset, we propose a lightweight JND prefiltering network, IQNet, which can be applied directly to different quantization cases with the same model and only needs 3K parameters. The experimental results show that the proposed approach to Versatile Video Coding could yield maximum/average bitrate savings of 41%/15% and 53%/19% for all-intra and low-delay P configurations, respectively, with negligible subjective quality loss. Our method demonstrates higher perceptual quality and a model size that is an order of magnitude smaller than previous deep learning methods.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"5 ","pages":"17-27"},"PeriodicalIF":0.0,"publicationDate":"2023-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10365509","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138998504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-04DOI: 10.1109/OJCAS.2023.3338639
Onur Toker
In this paper, we consider the difficulty of cyberattack detection with $d$ sensors and $n$ observations, and derive performance bounds that are valid independent of the attack detection algorithm used. In other words, regardless of whether it is an artificial intelligence (AI) or sensor fusion based approach or it is derived using a completely new innovative idea, a cyberattack detector using multiple observations does have certain fundamental performance bounds that are independent of the algorithm used. Cyberattacks introduce different forms of anomalies that may be small or large, and given enough measured data, even tiny anomalies will become more noticeable and cyberattack detection problem will be easier provided that a carefully designed attack detection algorithm is used. For example, False Data Injection (FDI) attacks with small injected error may be harder to detect, but such attacks can cause major failures if continued over a long time period. A natural question to ask is to what degree the cyberattack detection problem becomes easier if more and more measurements acquired over a long time period are used for threat assessment, and the risk level reduction achieved for each new observation. For a cyberattack detector, the false alarm rate is the probability of triggering an alarm when there is no cyberattack, and the probability of miss is the probability of not detecting a cyberattack. The risk level of a cyberattack detector is defined as the sum of the probability of false alarm and the probability of miss. By using the notion of Hellinger distance and total variation norm between probability distributions, we derive upper and lower bounds for the minimum possible (achievable) risk level under multiple measurements, and study asymptotic properties of such bounds. These performance bounds are valid regardless of the cyberattack detection algorithm selection; they imply certain fundamental performance limits in cyberattack detection applications with given number of observations; and also help us to understand the number of observations needed for a given cyberattack detection performance level.
{"title":"Asymptotic Performance Limitations in Cyberattack Detection","authors":"Onur Toker","doi":"10.1109/OJCAS.2023.3338639","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3338639","url":null,"abstract":"In this paper, we consider the difficulty of cyberattack detection with \u0000<inline-formula> <tex-math>$d$ </tex-math></inline-formula>\u0000 sensors and \u0000<inline-formula> <tex-math>$n$ </tex-math></inline-formula>\u0000 observations, and derive performance bounds that are valid independent of the attack detection algorithm used. In other words, regardless of whether it is an artificial intelligence (AI) or sensor fusion based approach or it is derived using a completely new innovative idea, a cyberattack detector using multiple observations does have certain fundamental performance bounds that are independent of the algorithm used. Cyberattacks introduce different forms of anomalies that may be small or large, and given enough measured data, even tiny anomalies will become more noticeable and cyberattack detection problem will be easier provided that a carefully designed attack detection algorithm is used. For example, False Data Injection (FDI) attacks with small injected error may be harder to detect, but such attacks can cause major failures if continued over a long time period. A natural question to ask is to what degree the cyberattack detection problem becomes easier if more and more measurements acquired over a long time period are used for threat assessment, and the risk level reduction achieved for each new observation. For a cyberattack detector, the false alarm rate is the probability of triggering an alarm when there is no cyberattack, and the probability of miss is the probability of not detecting a cyberattack. The risk level of a cyberattack detector is defined as the sum of the probability of false alarm and the probability of miss. By using the notion of Hellinger distance and total variation norm between probability distributions, we derive upper and lower bounds for the minimum possible (achievable) risk level under multiple measurements, and study asymptotic properties of such bounds. These performance bounds are valid regardless of the cyberattack detection algorithm selection; they imply certain fundamental performance limits in cyberattack detection applications with given number of observations; and also help us to understand the number of observations needed for a given cyberattack detection performance level.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"336-346"},"PeriodicalIF":0.0,"publicationDate":"2023-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10339844","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139034311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-01DOI: 10.1109/OJCAS.2023.3338210
Yudhajit Ray;Shreyas Sen
Recent advancements in low power and low noise front-end amplifiers have made it possible to support high-speed data transmission within the deep roll-off regions of conventional wireline channels. Despite being primarily limited by inter-symbol-interference (ISI), these legacy channels also require power-consuming front-end amplifiers due to increased insertion-loss at high frequencies. Wireline-like broadband channels, such as proximity communication and human-body-communication (HBC), as well as multi-lane, densely-packed channels, are further constrained by their high loss and unique channel responses which cause the received signal to be noise-limited. To address these challenges, this paper proposes the use of a discrete-time integrating amplifier as a low power <1 pJ/b using 65nm CMOS up to 5-6 Gb/s) alternative to traditional continuous-time front-end amplifiers. Integrating amplifiers also reduce the effects of noise due to its inherent current integrating process. The paper provides a detailed mathematical analysis of gain of two conventional and three novel and improved integrating amplifiers, accurate input referred noise estimations, signal-to-noise ratio, and a comparison of the integrating amplifier’s performance with that of a low-noise amplifier. The analysis identifies the most optimum integrator architecture and provides comparison with simulated results. This paper also develops theoretical expressions and provides in-depth understanding of input referred noise, while supporting them by simulations using 65nm CMOS technology node. Finally, a comparative analysis between low-noise amplifier and discrete-time integrating amplifier is presented to demonstrate power and noise benefits for both legacy and wireline-like channels, while providing an easier design space as integrator provides two-dimensional controllability for gain.
{"title":"Analysis of Discrete-Time Integrating Amplifiers as an Alternative to Continuous-Time Amplifiers in Broadband Receivers","authors":"Yudhajit Ray;Shreyas Sen","doi":"10.1109/OJCAS.2023.3338210","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3338210","url":null,"abstract":"Recent advancements in low power and low noise front-end amplifiers have made it possible to support high-speed data transmission within the deep roll-off regions of conventional wireline channels. Despite being primarily limited by inter-symbol-interference (ISI), these legacy channels also require power-consuming front-end amplifiers due to increased insertion-loss at high frequencies. Wireline-like broadband channels, such as proximity communication and human-body-communication (HBC), as well as multi-lane, densely-packed channels, are further constrained by their high loss and unique channel responses which cause the received signal to be noise-limited. To address these challenges, this paper proposes the use of a discrete-time integrating amplifier as a low power <1 pJ/b using 65nm CMOS up to 5-6 Gb/s) alternative to traditional continuous-time front-end amplifiers. Integrating amplifiers also reduce the effects of noise due to its inherent current integrating process. The paper provides a detailed mathematical analysis of gain of two conventional and three novel and improved integrating amplifiers, accurate input referred noise estimations, signal-to-noise ratio, and a comparison of the integrating amplifier’s performance with that of a low-noise amplifier. The analysis identifies the most optimum integrator architecture and provides comparison with simulated results. This paper also develops theoretical expressions and provides in-depth understanding of input referred noise, while supporting them by simulations using 65nm CMOS technology node. Finally, a comparative analysis between low-noise amplifier and discrete-time integrating amplifier is presented to demonstrate power and noise benefits for both legacy and wireline-like channels, while providing an easier design space as integrator provides two-dimensional controllability for gain.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"347-362"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10337627","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139034346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-27DOI: 10.1109/OJCAS.2023.3335400
Ahmed Abdelaziz;Mohamed Ahmed;Tawfiq Musah
This paper proposes a hybrid phase detector for use in multilevel timing recovery systems. The proposed approach suppresses errant zero-crossings associated with multilevel baud rate phase detectors and ensures maximum signal swing in lock, with minimal hardware and power overhead. Analysis and simulation results in a 28nm CMOS process are used to explore the functionality of proposed phase detector and demonstrate its effectiveness in achieving superior performance to the conventional approach.Clock and data recovery (CDR) loop simulations show that the proposed phase detector enables $1.36times $ increase in vertical eye margin while maintaining similar steady-state RMS jitter and compared to the conventional approach. The simulations also show effective suppression of unwanted phase detector zero-crossing, while achieving comparable acquisition bandwidth to the conventional approach.
{"title":"Hybrid Timing Error Detector for Baud Rate Multilevel Clock and Data Recovery","authors":"Ahmed Abdelaziz;Mohamed Ahmed;Tawfiq Musah","doi":"10.1109/OJCAS.2023.3335400","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3335400","url":null,"abstract":"This paper proposes a hybrid phase detector for use in multilevel timing recovery systems. The proposed approach suppresses errant zero-crossings associated with multilevel baud rate phase detectors and ensures maximum signal swing in lock, with minimal hardware and power overhead. Analysis and simulation results in a 28nm CMOS process are used to explore the functionality of proposed phase detector and demonstrate its effectiveness in achieving superior performance to the conventional approach.Clock and data recovery (CDR) loop simulations show that the proposed phase detector enables \u0000<inline-formula> <tex-math>$1.36times $ </tex-math></inline-formula>\u0000 increase in vertical eye margin while maintaining similar steady-state RMS jitter and compared to the conventional approach. The simulations also show effective suppression of unwanted phase detector zero-crossing, while achieving comparable acquisition bandwidth to the conventional approach.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"324-335"},"PeriodicalIF":0.0,"publicationDate":"2023-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10329284","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138558174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-15DOI: 10.1109/OJCAS.2023.3332853
Hamza Al Maharmeh;Nabil J. Sarhan;Mohammed Ismail;Mohammad Alhawari
The increasing demand for high performance and energy efficiency in Artificial Neural Networks (ANNs) accelerators has driven a wide range of application-specific integrated circuits (ASICs). Besides, the rapid deployment of low-power IoT devices requires highly efficient computing, which as a result urges the need to explore low-power hardware implementations in different domains. This paper proposes a spatially unrolled time-domain accelerator that uses an ultra-low-power digital-to-time converter (DTC) while occupying an active area of 0.201 mm2. The proposed DTC is implemented using a Laddered, Inverter (LI) circuit, which consumes 3 $times $ less power than the conventional inverter-based DTC and provides reliable performance across different process corners, supply voltages, and temperature variations. Post-synthesis results in 65nm CMOS show that the proposed core achieves a superior energy efficiency of 116 TOPS/W, a throughput of 4 GOPS, and an area efficiency of 20 GOPS/mm2. The proposed core improves energy efficiency by 2.4 - 47 $times $ compared to prior time-domain accelerators.
{"title":"A 116 TOPS/W Spatially Unrolled Time-Domain Accelerator Utilizing Laddered-Inverter DTC for Energy-Efficient Edge Computing in 65 nm","authors":"Hamza Al Maharmeh;Nabil J. Sarhan;Mohammed Ismail;Mohammad Alhawari","doi":"10.1109/OJCAS.2023.3332853","DOIUrl":"10.1109/OJCAS.2023.3332853","url":null,"abstract":"The increasing demand for high performance and energy efficiency in Artificial Neural Networks (ANNs) accelerators has driven a wide range of application-specific integrated circuits (ASICs). Besides, the rapid deployment of low-power IoT devices requires highly efficient computing, which as a result urges the need to explore low-power hardware implementations in different domains. This paper proposes a spatially unrolled time-domain accelerator that uses an ultra-low-power digital-to-time converter (DTC) while occupying an active area of 0.201 mm2. The proposed DTC is implemented using a Laddered, Inverter (LI) circuit, which consumes 3\u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 less power than the conventional inverter-based DTC and provides reliable performance across different process corners, supply voltages, and temperature variations. Post-synthesis results in 65nm CMOS show that the proposed core achieves a superior energy efficiency of 116 TOPS/W, a throughput of 4 GOPS, and an area efficiency of 20 GOPS/mm2. The proposed core improves energy efficiency by 2.4 - 47\u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 compared to prior time-domain accelerators.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"308-323"},"PeriodicalIF":0.0,"publicationDate":"2023-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10318175","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135710807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-02DOI: 10.1109/OJCAS.2023.3329723
Dimitrios Baxevanakis;Dimitris Nikitas;Paul P. Sotiriadis
This work presents a power stage architecture that combines high–linearity with high–efficiency. The power stage is configured as a push–pull Class–A topology with two buck–converters providing its supply rails. The buck–converters continuously track the stage’s output with a small constant margin, creating a minimum, constant voltage drop on the output devices; thus, the stage’s efficiency is increased and its linearity is improved. Theoretical analysis of the topology and its feedback control are presented, while a design example is implemented and simulated in Cadence Spectre as proof–of–concept.
{"title":"Class–CTA: Concept and Theoretical Analysis of a High Linearity and Efficiency Power Stage Architecture","authors":"Dimitrios Baxevanakis;Dimitris Nikitas;Paul P. Sotiriadis","doi":"10.1109/OJCAS.2023.3329723","DOIUrl":"10.1109/OJCAS.2023.3329723","url":null,"abstract":"This work presents a power stage architecture that combines high–linearity with high–efficiency. The power stage is configured as a push–pull Class–A topology with two buck–converters providing its supply rails. The buck–converters continuously track the stage’s output with a small constant margin, creating a minimum, constant voltage drop on the output devices; thus, the stage’s efficiency is increased and its linearity is improved. Theoretical analysis of the topology and its feedback control are presented, while a design example is implemented and simulated in Cadence Spectre as proof–of–concept.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"295-307"},"PeriodicalIF":0.0,"publicationDate":"2023-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10305243","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134888124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-02DOI: 10.1109/OJCAS.2023.3328871
Mohammad Oveisi;Seyedali Hosseinisangchi;Payam Heydari
A thorough investigation of major contributors to out-of-band emission (OOBE) in transmitters (TXs) utilizing digital modulation schemes is provided. Specifically, the paper delves into the detrimental effects of phase noise of the local oscillator (LO), typically realized using a phase-locked loop (PLL), on the OOBE phenomenon. Furthermore, the effects of the circuit nonlinearity in a TX, widely recognized as a primary contributor to spectral regrowth and elevated levels of OOBE, are investigated. Additionally, the impact of filtering and bandwidth (BW) limitation on OOBE is taken into account. Comprehensive simulations verify the accuracy of the analytical study. The results provided throughout this paper can be used to determine the linearity and phase noise requirements of different blocks, such as PLL and power amplifier (PA) within a TX chain to design a system complying with a specific mask emission dictated by a particular standard.
{"title":"A Study of Out-of-Band Emission in Digital Transmitters Due to PLL Phase Noise, Circuit Non-Linearity, and Bandwidth Limitation","authors":"Mohammad Oveisi;Seyedali Hosseinisangchi;Payam Heydari","doi":"10.1109/OJCAS.2023.3328871","DOIUrl":"10.1109/OJCAS.2023.3328871","url":null,"abstract":"A thorough investigation of major contributors to out-of-band emission (OOBE) in transmitters (TXs) utilizing digital modulation schemes is provided. Specifically, the paper delves into the detrimental effects of phase noise of the local oscillator (LO), typically realized using a phase-locked loop (PLL), on the OOBE phenomenon. Furthermore, the effects of the circuit nonlinearity in a TX, widely recognized as a primary contributor to spectral regrowth and elevated levels of OOBE, are investigated. Additionally, the impact of filtering and bandwidth (BW) limitation on OOBE is taken into account. Comprehensive simulations verify the accuracy of the analytical study. The results provided throughout this paper can be used to determine the linearity and phase noise requirements of different blocks, such as PLL and power amplifier (PA) within a TX chain to design a system complying with a specific mask emission dictated by a particular standard.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"283-294"},"PeriodicalIF":0.0,"publicationDate":"2023-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10305256","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134888134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-04DOI: 10.1109/OJCAS.2023.3302254
Archisman Ghosh;Debayan Das;Shreyas Sen
Mathematically secure cryptographic algorithms leak significant side-channel information through their power supplies when implemented on a physical platform. These side-channel leakages can be exploited by an attacker to extract the secret key of an embedded device. The existing state-of-the-art countermeasures mainly focus on power balancing, gate-level masking, or signal-to-noise (SNR) reduction using noise injection and signature attenuation, all of which suffer either from the limitations of high power/area overheads, throughput degradation or are not synthesizable. In this article, we propose a generic low-overhead digital-friendly power SCA countermeasure utilizing a physical Time-Varying Transfer Function (TVTF) by randomly shuffling distributed switched capacitors to significantly obfuscate the traces in the time domain. We evaluate our proposed technique utilizing a MATLAB-based system-level simulation. Finally, we implement a 65nm CMOS prototype IC and evaluate our technique against power side-channel attacks (SCA). System-level simulation results of the TVTF-AES show $sim 5000times $ minimum traces to disclosure (MTD) improvement over the unprotected implementation with $sim 1.25times $ power and $sim 1.2times $ area overheads, and without any performance degradation. SCA evaluation with the prototype IC shows $3.4M$ MTD which is $500times $ greater than the unprotected solution.
{"title":"Physical Time-Varying Transfer Function as Generic Low-Overhead Power-SCA Countermeasure","authors":"Archisman Ghosh;Debayan Das;Shreyas Sen","doi":"10.1109/OJCAS.2023.3302254","DOIUrl":"10.1109/OJCAS.2023.3302254","url":null,"abstract":"Mathematically secure cryptographic algorithms leak significant side-channel information through their power supplies when implemented on a physical platform. These side-channel leakages can be exploited by an attacker to extract the secret key of an embedded device. The existing state-of-the-art countermeasures mainly focus on power balancing, gate-level masking, or signal-to-noise (SNR) reduction using noise injection and signature attenuation, all of which suffer either from the limitations of high power/area overheads, throughput degradation or are not synthesizable. In this article, we propose a generic low-overhead digital-friendly power SCA countermeasure utilizing a physical Time-Varying Transfer Function (TVTF) by randomly shuffling distributed switched capacitors to significantly obfuscate the traces in the time domain. We evaluate our proposed technique utilizing a MATLAB-based system-level simulation. Finally, we implement a 65nm CMOS prototype IC and evaluate our technique against power side-channel attacks (SCA). System-level simulation results of the TVTF-AES show \u0000<inline-formula> <tex-math>$sim 5000times $ </tex-math></inline-formula>\u0000 minimum traces to disclosure (MTD) improvement over the unprotected implementation with \u0000<inline-formula> <tex-math>$sim 1.25times $ </tex-math></inline-formula>\u0000 power and \u0000<inline-formula> <tex-math>$sim 1.2times $ </tex-math></inline-formula>\u0000 area overheads, and without any performance degradation. SCA evaluation with the prototype IC shows \u0000<inline-formula> <tex-math>$3.4M$ </tex-math></inline-formula>\u0000 MTD which is \u0000<inline-formula> <tex-math>$500times $ </tex-math></inline-formula>\u0000 greater than the unprotected solution.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"228-240"},"PeriodicalIF":0.0,"publicationDate":"2023-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10208218.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43006579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A magnetoelectric antenna (ME) can exhibit the dual capabilities of wireless energy harvesting and sensing at different frequencies. In this article, a behavioral circuit model for hybrid ME antennas is described to emulate the radio frequency (RF) energy harvesting and sensing operations during circuit simulations. The ME antenna of this work is interfaced with a CMOS energy harvester chip towards the goal of developing a wireless communication link for fully integrated implantable devices. One role of the integrated system is to receive pulse-modulated power from a nearby transmitter, and another role is to sense and transmit low-magnitude neural signals. The measurements reported in this paper are the first results that demonstrate simultaneous low-frequency wireless magnetic sensing and high-frequency wireless energy harvesting at two different frequencies with one dual-mode ME antenna. The proposed behavioral ME antenna model can be utilized during design optimizations of energy harvesting circuits. Measurements were performed to validate the wireless power transfer link with an ME antenna having a 2.57 GHz resonance frequency connected to an energy harvester chip designed in 65nm CMOS technology. Furthermore, this dual-mode ME antenna enables concurrent sensing using a carrier signal with a frequency that matches the second 63.63 MHz resonance mode. A wireless test platform has been developed for evaluation of ME antennas as a tool for neural implant design, and this prototype system was utilized to provide first experimental results with the transmission of magnetically modulated action potential waveforms.
{"title":"Circuit-Level Modeling and Simulation of Wireless Sensing and Energy Harvesting With Hybrid Magnetoelectric Antennas for Implantable Neural Devices","authors":"Diptashree Das;Ziyue Xu;Mehdi Nasrollahpour;Isabel Martos-Repath;Mohsen Zaeimbashi;Adam Khalifa;Ankit Mittal;Sydney S. Cash;Nian X. Sun;Aatmesh Shrivastava;Marvin Onabajo","doi":"10.1109/OJCAS.2023.3259233","DOIUrl":"10.1109/OJCAS.2023.3259233","url":null,"abstract":"A magnetoelectric antenna (ME) can exhibit the dual capabilities of wireless energy harvesting and sensing at different frequencies. In this article, a behavioral circuit model for hybrid ME antennas is described to emulate the radio frequency (RF) energy harvesting and sensing operations during circuit simulations. The ME antenna of this work is interfaced with a CMOS energy harvester chip towards the goal of developing a wireless communication link for fully integrated implantable devices. One role of the integrated system is to receive pulse-modulated power from a nearby transmitter, and another role is to sense and transmit low-magnitude neural signals. The measurements reported in this paper are the first results that demonstrate simultaneous low-frequency wireless magnetic sensing and high-frequency wireless energy harvesting at two different frequencies with one dual-mode ME antenna. The proposed behavioral ME antenna model can be utilized during design optimizations of energy harvesting circuits. Measurements were performed to validate the wireless power transfer link with an ME antenna having a 2.57 GHz resonance frequency connected to an energy harvester chip designed in 65nm CMOS technology. Furthermore, this dual-mode ME antenna enables concurrent sensing using a carrier signal with a frequency that matches the second 63.63 MHz resonance mode. A wireless test platform has been developed for evaluation of ME antennas as a tool for neural implant design, and this prototype system was utilized to provide first experimental results with the transmission of magnetically modulated action potential waveforms.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"139-155"},"PeriodicalIF":0.0,"publicationDate":"2023-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10076793","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41223293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/OJCAS.2023.3245439
Gabriele Manganaro;Nicole Mcfarlane
DEAR readers, happy 2023! I have recently been elected as the Vice President for Publications for the CAS Society for the 2023–2024 term. Because of that I am unable to complete my term as EiC, which would have otherwise elapsed on 31 December 2023. We are lucky to have two outstanding leaders, Alison Burdett and Nicole Mcfarlane, presently serving as Associate Editors-in-Chief (AEiC). The IEEE Circuits and Systems Society (CASS) has formally appointed Nicole Mcfarlane to serve as the IEEE Open Journal of Circuits and Systems (OJCAS) Editor-in-Chief for the 2023 calendar year and I am glad that she accepted to work in this capacity. I have no doubts that Nicole will carry her new appointment flawlessly and I wish her all the best.
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