Pub Date : 2022-09-20DOI: 10.1109/OJCAS.2022.3202588
Alison Burdett
The International Symposium on Integrated Circuits and Systems (ISICAS) is a forum for dissemination of original work with experimental results from integrated circuits and systems in the areas of analog, digital, power, energy, biomedical, sensor interfaces and communications. Papers accepted to be presented at the symposium are automatically published in special issues of leading IEEE Circuits and Systems Society (CASS) journals, namely Transactions on Circuits and Systems (TCAS) Parts I and II, Transactions on Biomedical Circuits and Systems (TBioCAS), and Open Journal of Circuits and Systems (OJCAS).
{"title":"IEEE Open Journal of Circuits and Systems: Special Section on ISICAS 2022","authors":"Alison Burdett","doi":"10.1109/OJCAS.2022.3202588","DOIUrl":"10.1109/OJCAS.2022.3202588","url":null,"abstract":"The International Symposium on Integrated Circuits and Systems (ISICAS) is a forum for dissemination of original work with experimental results from integrated circuits and systems in the areas of analog, digital, power, energy, biomedical, sensor interfaces and communications. Papers accepted to be presented at the symposium are automatically published in special issues of leading IEEE Circuits and Systems Society (CASS) journals, namely Transactions on Circuits and Systems (TCAS) Parts I and II, Transactions on Biomedical Circuits and Systems (TBioCAS), and Open Journal of Circuits and Systems (OJCAS).","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9896231","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72854014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Real-time in-sensor spike sorting is a forefront requirement in the development of brainmachine interfaces (BMIs). This work presents the characterization, design, and efficient implementation on a field-programmable gate array (FPGA) of a novel approach to neural spike sorting intended for implantable devices based on convolutional neural networks (CNNs). While the temporal features, the shape of the spike signals, could be highly mitigated from the ambient noise, the proposed classifier effectively extracts spatial features from the multi-channel neural signal to maintain high accuracy on the noisy data. The proposed classifier mechanism was tested on real data that is recorded from multi-channel electrodes, containing 27 neural units, and the classifier achieves 93.1% accuracy despite high temporal noise in the signal. For hardware synthesis, the CNN weights are quantized to reduce the model storage requirement by 93% compared to its floating point-precision version, and the model achieves an accuracy of 86.1%.
{"title":"Multichannel Many-Class Real-Time Neural Spike Sorting With Convolutional Neural Networks","authors":"Jinho Yi;Jiachen Xu;Ethan Chen;Maysamreza Chamanzar;Vanessa Chen","doi":"10.1109/OJCAS.2022.3184302","DOIUrl":"10.1109/OJCAS.2022.3184302","url":null,"abstract":"Real-time in-sensor spike sorting is a forefront requirement in the development of brainmachine interfaces (BMIs). This work presents the characterization, design, and efficient implementation on a field-programmable gate array (FPGA) of a novel approach to neural spike sorting intended for implantable devices based on convolutional neural networks (CNNs). While the temporal features, the shape of the spike signals, could be highly mitigated from the ambient noise, the proposed classifier effectively extracts spatial features from the multi-channel neural signal to maintain high accuracy on the noisy data. The proposed classifier mechanism was tested on real data that is recorded from multi-channel electrodes, containing 27 neural units, and the classifier achieves 93.1% accuracy despite high temporal noise in the signal. For hardware synthesis, the CNN weights are quantized to reduce the model storage requirement by 93% compared to its floating point-precision version, and the model achieves an accuracy of 86.1%.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9896230","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62853241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-13DOI: 10.1109/OJCAS.2022.3206326
Ori Bass;Asaf Feldman;Joseph Shor
A nW-level BJT-based bandgap reference with fine grained voltage and temperature coefficient trimming is presented. The bandgap reference utilizes switched capacitors (SC) as impedance elements instead of resistors in a current mode configuration. This configuration enabled low power (38nW) with a minimal area (0.0174 mm2). The voltage could be trimmed independently without affecting the temperature coefficient. The SC’s are stacked in order to achieve accurate trimming without using unrealistically small capacitors. The temperature coefficient can be trimmed between 50-200 ppm/°C in either direction, while the voltage can be trimmed between 580-800mV.
{"title":"A Resistor-Less nW-Level Bandgap Reference With Fine-Grained Voltage and Temperature Coefficient Trims","authors":"Ori Bass;Asaf Feldman;Joseph Shor","doi":"10.1109/OJCAS.2022.3206326","DOIUrl":"10.1109/OJCAS.2022.3206326","url":null,"abstract":"A nW-level BJT-based bandgap reference with fine grained voltage and temperature coefficient trimming is presented. The bandgap reference utilizes switched capacitors (SC) as impedance elements instead of resistors in a current mode configuration. This configuration enabled low power (38nW) with a minimal area (0.0174 mm2). The voltage could be trimmed independently without affecting the temperature coefficient. The SC’s are stacked in order to achieve accurate trimming without using unrealistically small capacitors. The temperature coefficient can be trimmed between 50-200 ppm/°C in either direction, while the voltage can be trimmed between 580-800mV.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9888150","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62853774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The routing congestion over a QC-LDPC decoder with a large circular permutation matrix (CPM) size has long been an obstacle to high throughput designs. This paper presents a large-CPM congestion-free decoder for (18396, 16416) quasi-cyclic Euclidean geometry low-density parity-check (QC-EG-LDPC) code in NAND flash application. Considering area efficiency in scheduling schemes and the array dispersion structure, the Array-Disperse Based Dual Variable Node Unit (VNU) Cluster Architecture fully leverages the code structure to support at least two physical channels of the Open NAND Flash Interface 5.0 (ONFI 5.0). In addition, the proposed congestion-aware analysis and implementation method achieve a highly parallel decoder at a 70% utilization ratio. Implemented in TSMC 28nm process, the presented decoder provides 38.64 Gbps throughput at RBER=1.456% Bi-AWGN channel with an area of 2.97 mm2.
{"title":"A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories","authors":"Li-Wei Liu;Mu-Hua Yuan;Yen-Chin Liao;Hsie-Chia Chang","doi":"10.1109/OJCAS.2022.3203849","DOIUrl":"10.1109/OJCAS.2022.3203849","url":null,"abstract":"The routing congestion over a QC-LDPC decoder with a large circular permutation matrix (CPM) size has long been an obstacle to high throughput designs. This paper presents a large-CPM congestion-free decoder for (18396, 16416) quasi-cyclic Euclidean geometry low-density parity-check (QC-EG-LDPC) code in NAND flash application. Considering area efficiency in scheduling schemes and the array dispersion structure, the Array-Disperse Based Dual Variable Node Unit (VNU) Cluster Architecture fully leverages the code structure to support at least two physical channels of the Open NAND Flash Interface 5.0 (ONFI 5.0). In addition, the proposed congestion-aware analysis and implementation method achieve a highly parallel decoder at a 70% utilization ratio. Implemented in TSMC 28nm process, the presented decoder provides 38.64 Gbps throughput at RBER=1.456% Bi-AWGN channel with an area of 2.97 mm2.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9874844","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62853935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-09DOI: 10.1109/OJCAS.2022.3197333
Jeremy Cosson-Martin;Hossein Shakiba;Ali Sheikholeslami
This paper proposes an efficient multi-carrier system that combines filter-bank multi-carrier signalling, decision-directed channel estimation, and frequency-domain timing recovery to eliminate the overhead associated with cyclic prefix, large side-lobes, and pilot carriers. Furthermore, a technique is proposed to halve the required number of FFTs (IFFTs), reducing their complexity by 29% for a 32-point resolution; a method is proposed to correct tilt and stretch distortion; and a gain controller with adaptive loop coefficients is adopted to achieve the same stability but 65% higher tracking bandwidth regardless of the FFT size. The concept is validated at the system level, where impairments are applied, enabling an in-depth comparison to conventional discrete multi-tone signalling. Assuming a 32-point FFT, a $35dB$ channel, and an overlap factor of 3, results show 101% improvement in capacity, 100% improvement in power efficiency, and 101% improvement in area efficiency, and all while maintaining comparable latency. This work enables very low-resolution multi-carrier schemes, which were previously impractical due to the significant overhead.
{"title":"An Efficient Filter-Bank Multi-Carrier System for High-Speed Wireline Applications","authors":"Jeremy Cosson-Martin;Hossein Shakiba;Ali Sheikholeslami","doi":"10.1109/OJCAS.2022.3197333","DOIUrl":"10.1109/OJCAS.2022.3197333","url":null,"abstract":"This paper proposes an efficient multi-carrier system that combines filter-bank multi-carrier signalling, decision-directed channel estimation, and frequency-domain timing recovery to eliminate the overhead associated with cyclic prefix, large side-lobes, and pilot carriers. Furthermore, a technique is proposed to halve the required number of FFTs (IFFTs), reducing their complexity by 29% for a 32-point resolution; a method is proposed to correct tilt and stretch distortion; and a gain controller with adaptive loop coefficients is adopted to achieve the same stability but 65% higher tracking bandwidth regardless of the FFT size. The concept is validated at the system level, where impairments are applied, enabling an in-depth comparison to conventional discrete multi-tone signalling. Assuming a 32-point FFT, a \u0000<inline-formula> <tex-math>$35dB$ </tex-math></inline-formula>\u0000 channel, and an overlap factor of 3, results show 101% improvement in capacity, 100% improvement in power efficiency, and 101% improvement in area efficiency, and all while maintaining comparable latency. This work enables very low-resolution multi-carrier schemes, which were previously impractical due to the significant overhead.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9852766","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62853821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-12DOI: 10.1109/OJCAS.2022.3189550
Gain Kim
The 4-level pulse-amplitude modulation (PAM-4) with an analog-digital converter (ADC)-based receiver (RX) has become the most commonly employed modulation for ultra-high-speed serial links with the data rate above 100 Gb/s. To support the data rate of 200 Gb/s, orthogonal frequency division multiplexing (OFDM) has been studied recently as one of the possible modulation schemes in the next-generation serial links. The OFDM can feature high bandwidth efficiency without increasing the equalization complexity, leading to a reduced maximum signal amplitude attenuation and lower required DAC/ADC conversion rates given sufficient DAC/ADC resolutions such that the BER is not primarily limited by the data converters’ resolution. This paper presents system-level modeling results of OFDM-based wireline serial links, with a particular emphasis on the impacts of the fast Fourier transform (FFT) processor’s tap count on the serial link performance. The relationship among the cyclic prefix (CP), FFT tap count, and the link bit-error-rate (BER) are thoroughly explained. The analysis explains that the power consumption of a partially-serial FFT processor improves with a larger kernel FFT size, and simulation results show that the BER performance improves with the FFT size where an optimal CP length exists given the FFT size.
{"title":"Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications","authors":"Gain Kim","doi":"10.1109/OJCAS.2022.3189550","DOIUrl":"10.1109/OJCAS.2022.3189550","url":null,"abstract":"The 4-level pulse-amplitude modulation (PAM-4) with an analog-digital converter (ADC)-based receiver (RX) has become the most commonly employed modulation for ultra-high-speed serial links with the data rate above 100 Gb/s. To support the data rate of 200 Gb/s, orthogonal frequency division multiplexing (OFDM) has been studied recently as one of the possible modulation schemes in the next-generation serial links. The OFDM can feature high bandwidth efficiency without increasing the equalization complexity, leading to a reduced maximum signal amplitude attenuation and lower required DAC/ADC conversion rates given sufficient DAC/ADC resolutions such that the BER is not primarily limited by the data converters’ resolution. This paper presents system-level modeling results of OFDM-based wireline serial links, with a particular emphasis on the impacts of the fast Fourier transform (FFT) processor’s tap count on the serial link performance. The relationship among the cyclic prefix (CP), FFT tap count, and the link bit-error-rate (BER) are thoroughly explained. The analysis explains that the power consumption of a partially-serial FFT processor improves with a larger kernel FFT size, and simulation results show that the BER performance improves with the FFT size where an optimal CP length exists given the FFT size.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9827577","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62853299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper reviews and analyses the design of popular radio frequency energy harvesting systems and proposes a method to qualitatively and quantitatively analyze their circuit architectures using new square-wave approximation method. This approach helps in simplifying design analysis. Using this analysis, we can establish no load output voltage characteristics, upper limit on rectifier efficiency, and maximum power characteristics of a rectifier. This paper will help guide the design of RF energy harvesting rectifier circuits for radio frequency identification (RFIDs), the Internet of Things (IoTs), wearable, and implantable medical device applications. Different application scenarios are explained in the context of design challenges, and corresponding design considerations are discussed in order to evaluate their performance. The pros and cons of different rectifier topologies are also investigated. In addition to presenting the popular rectifier topologies, new measurement results of these energy harvester topologies, fabricated in 65nm, 130nm and 180nm CMOS technologies are also presented.
{"title":"Analysis and Design Methodology of RF Energy Harvesting Rectifier Circuit for Ultra-Low Power Applications","authors":"Ziyue Xu;Adam Khalifa;Ankit Mittal;Mehdi Nasrollahpourmotlaghzanjani;Ralph Etienne-Cummings;Nian Xiang Sun;Sydney S. Cash;Aatmesh Shrivastava","doi":"10.1109/OJCAS.2022.3169437","DOIUrl":"10.1109/OJCAS.2022.3169437","url":null,"abstract":"This paper reviews and analyses the design of popular radio frequency energy harvesting systems and proposes a method to qualitatively and quantitatively analyze their circuit architectures using new square-wave approximation method. This approach helps in simplifying design analysis. Using this analysis, we can establish no load output voltage characteristics, upper limit on rectifier efficiency, and maximum power characteristics of a rectifier. This paper will help guide the design of RF energy harvesting rectifier circuits for radio frequency identification (RFIDs), the Internet of Things (IoTs), wearable, and implantable medical device applications. Different application scenarios are explained in the context of design challenges, and corresponding design considerations are discussed in order to evaluate their performance. The pros and cons of different rectifier topologies are also investigated. In addition to presenting the popular rectifier topologies, new measurement results of these energy harvester topologies, fabricated in 65nm, 130nm and 180nm CMOS technologies are also presented.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9761164","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46333264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a transformer-based bandwidth (BW) extension technique is employed to improve the BW, noise, and silicon area of inverter-based transimpedance amplifiers (TIAs) even when they use inductive peaking. A TIA based on the proposed technique, designed and laid out in a 16-nm FinFET process, demonstrates a 36% increased in BW, a 19% reduction in input-referred noise, and a 57% reduction in silicon area compared to the conventional TIA with inductive peaking. In the proposed TIA architecture, inclusion of a transformer in the forward path compensates partially for the parasitic capacitances of the inverter and relaxes the transimpedance limit of the conventional TIA. The proposed technique also lowers the input-referred current noise spectrum of the TIA. Post-layout in companion with electromagnetic (EM) simulations and statistical analysis are employed to verify the effectiveness of the proposed architecture. Simulation results show that the TIA achieves a transimpedance gain of 58 dB $Omega $ , a BW of 17.4 GHz, an input-referred noise of 17.4 pA/sqrt (Hz), and an eye-opening of 20 mV at a data-rate of 64 Gbps PAM4 and at a bit-error-rate (BER) of 1E-6. The whole TIA chain is expected to consume 19 mW and occupies an active area of 0.023 mm 2 .
{"title":"A Low-Noise High-Gain Broadband Transformer-Based Inverter-Based Transimpedance Amplifier","authors":"Milad Haghi Kashani;Hossein Shakiba;Ali Sheikholeslami","doi":"10.1109/OJCAS.2022.3164396","DOIUrl":"10.1109/OJCAS.2022.3164396","url":null,"abstract":"In this paper, a transformer-based bandwidth (BW) extension technique is employed to improve the BW, noise, and silicon area of inverter-based transimpedance amplifiers (TIAs) even when they use inductive peaking. A TIA based on the proposed technique, designed and laid out in a 16-nm FinFET process, demonstrates a 36% increased in BW, a 19% reduction in input-referred noise, and a 57% reduction in silicon area compared to the conventional TIA with inductive peaking. In the proposed TIA architecture, inclusion of a transformer in the forward path compensates partially for the parasitic capacitances of the inverter and relaxes the transimpedance limit of the conventional TIA. The proposed technique also lowers the input-referred current noise spectrum of the TIA. Post-layout in companion with electromagnetic (EM) simulations and statistical analysis are employed to verify the effectiveness of the proposed architecture. Simulation results show that the TIA achieves a transimpedance gain of 58 dB\u0000<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>\u0000, a BW of 17.4 GHz, an input-referred noise of 17.4 pA/sqrt (Hz), and an eye-opening of 20 mV at a data-rate of 64 Gbps PAM4 and at a bit-error-rate (BER) of 1E-6. The whole TIA chain is expected to consume 19 mW and occupies an active area of 0.023 mm\u0000<sup>2</sup>\u0000.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9748875","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62852916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-03-29DOI: 10.1109/OJCAS.2022.3163075
Lulu Ge;Keshab K. Parhi
Hyperdimensional (HD) computing is a form of brain-inspired computing which can be applied to numerous classification problems. In past research, it has been shown that seizures can be detected from electroencephalograms (EEG) with high accuracy using local binary pattern (LBP) encoding. This paper explores applicability of binary HD computing to seizure detection from intra-cranial EEG (iEEG) data from the Kaggle seizure detection contest based on using both LBP and power spectral density (PSD) features. In the PSD method, three novel approaches to HD classification are presented for both selected features and all features. These are referred as single classifier long hypervector , multiple classifiers , and single classifier short hypervector . To visualize the quality of classification of test data, a hypervector distance plot is introduced that plots the Hamming distance of the query hpervectors from one class hypervector vs. that from the other. Simulation results show that: 1) . LBP method offers an average 80.9% test accuracy, 71.9% sensitivity, 81.4% specificity and 76.6% test AUC whereas the PSD method can achieve an average of 91.0% test accuracy, 81.8% sensitivity, 92.0% specificity and 86.9% test AUC. 2) . The average seizure detection latency is 2.5s for LBP method and is 4.5s for the PSD methods. This average latency, less than 5s, is a relevant parameter for fast drug delivery, indicating that both LBP and PSD methods are able to detect the seizures in a timely manner. The performance using selected PSD features is better than that using all features. 3) . It is shown that the dimensionality of the hypervector can be reduced to 1, 000 bits for LBP and PSD methods from 10, 000. Futhermore, for some approaches of selected features, the dimensionality of the hypervector can be reduced to 100 bits.
{"title":"Applicability of Hyperdimensional Computing to Seizure Detection","authors":"Lulu Ge;Keshab K. Parhi","doi":"10.1109/OJCAS.2022.3163075","DOIUrl":"10.1109/OJCAS.2022.3163075","url":null,"abstract":"Hyperdimensional (HD) computing is a form of brain-inspired computing which can be applied to numerous classification problems. In past research, it has been shown that seizures can be detected from electroencephalograms (EEG) with high accuracy using local binary pattern (LBP) encoding. This paper explores applicability of binary HD computing to seizure detection from intra-cranial EEG (iEEG) data from the Kaggle seizure detection contest based on using both LBP and power spectral density (PSD) features. In the PSD method, three novel approaches to HD classification are presented for both selected features and all features. These are referred as \u0000<italic>single classifier long hypervector</i>\u0000, \u0000<italic>multiple classifiers</i>\u0000, and \u0000<italic>single classifier short hypervector</i>\u0000. To visualize the quality of classification of test data, a \u0000<italic>hypervector distance</i>\u0000 plot is introduced that plots the Hamming distance of the query hpervectors from one class hypervector \u0000<italic>vs.</i>\u0000 that from the other. Simulation results show that: \u0000<italic>1)</i>\u0000. LBP method offers an average 80.9% test accuracy, 71.9% sensitivity, 81.4% specificity and 76.6% test AUC whereas the PSD method can achieve an average of 91.0% test accuracy, 81.8% sensitivity, 92.0% specificity and 86.9% test AUC. \u0000<italic>2)</i>\u0000. The average seizure detection latency is 2.5s for LBP method and is 4.5s for the PSD methods. This average latency, less than 5s, is a relevant parameter for fast drug delivery, indicating that both LBP and PSD methods are able to detect the seizures in a timely manner. The performance using selected PSD features is better than that using all features. \u0000<italic>3)</i>\u0000. It is shown that the dimensionality of the hypervector can be reduced to 1, 000 bits for LBP and PSD methods from 10, 000. Futhermore, for some approaches of selected features, the dimensionality of the hypervector can be reduced to 100 bits.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9744111","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62852816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-03-23DOI: 10.1109/OJCAS.2022.3161873
Muhammad Ali Akbar;Bo Wang;Amine Bermak
In this paper, a self-checking and -repairing carry-lookahead adder (CLA) is proposed with distributed fault detection ability. The presented design with self-checking and fault localization ability requires an area overhead of 69.6% as compared to the conventional CLA. It can handle multiple faults simultaneously without affecting the delay of conventional CLA, with the condition that each module has a single fault at a time. The repairing operation utilizes the hot-standby approach with partial reconfiguration in which the faulty module would be replaced by an accurately functioning module at run-time. The proposed self-repairing adder with high fault coverage requires 161.5% area overhead as compared to conventional CLA design which is 35.3% less as compared to the state-of-the-art partial self-repairing CLA. Moreover, the delay of the proposed 64-bit self-repairing CLA is 40.7% more efficient as compared to conventional ripple carry adder.
{"title":"Self-Repairing Carry-Lookahead Adder With Hot-Standby Topology Using Fault-Localization and Partial Reconfiguration","authors":"Muhammad Ali Akbar;Bo Wang;Amine Bermak","doi":"10.1109/OJCAS.2022.3161873","DOIUrl":"10.1109/OJCAS.2022.3161873","url":null,"abstract":"In this paper, a self-checking and -repairing carry-lookahead adder (CLA) is proposed with distributed fault detection ability. The presented design with self-checking and fault localization ability requires an area overhead of 69.6% as compared to the conventional CLA. It can handle multiple faults simultaneously without affecting the delay of conventional CLA, with the condition that each module has a single fault at a time. The repairing operation utilizes the hot-standby approach with partial reconfiguration in which the faulty module would be replaced by an accurately functioning module at run-time. The proposed self-repairing adder with high fault coverage requires 161.5% area overhead as compared to conventional CLA design which is 35.3% less as compared to the state-of-the-art partial self-repairing CLA. Moreover, the delay of the proposed 64-bit self-repairing CLA is 40.7% more efficient as compared to conventional ripple carry adder.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9740253","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62853050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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