Pub Date : 2023-01-01DOI: 10.1109/OJCAS.2023.3256368
Liwen Lin;Ka-Meng Lei;Pui-In Mak;Rui P. Martins
This paper reports an ultra-low-voltage (ULV) single-crystal oscillator-timer (XO-Timer) for sub-0.5 V Bluetooth low-energy (BLE) radios that aims for self-powering by harvesting the ambient energies. Specifically, we tailor an on-chip micropower manager $(mu $ PM) to customize the voltage and current budgets for each sub-function of the XO-Timer. Such $mu $ PM shows a high power efficiency by introducing a 3-stage cascaded structure and a single voltage-regulation loop; they together uphold the performance of the XO-Timer amid supply-voltage and temperature variations. The core amplifier of the XO-Timer is ULV-enabled, and is reconfigurable (i.e., 1-stage and 3-stage gm) to balance between the power budget and performance under the high-performance mode (HPM) and low-power mode (LPM). Fabricated in 28-nm CMOS, the XO-Timer in HPM generates a 16-MHz clock with a power of $24.3 ~mu text{W}$ , and a phase noise of −133.8 dBc/Hz at 1-kHz offset, resulting in a Figure-of-Merit (FoM1) of −236 dBc/Hz. In the LPM, the XO-Timer delivers a 32.258-kHz clock while consuming $11.4 ~mu text{W}$ . The sleep-timer FoM2 is $14.8 ~mu text{W}$ and the Allan deviation is 35.1 ppb, achieving the lowest supply voltage (0.25 V) not only for a dual-mode XO-Timer but also for a MHz-range XO.
{"title":"An Ultra-Low-Voltage Single-Crystal Oscillator-Timer (XO-Timer) Delivering 16-MHz and 32.258-kHz Clocks for Sub-0.5-V Energy-Harvesting BLE Radios in 28-nm CMOS","authors":"Liwen Lin;Ka-Meng Lei;Pui-In Mak;Rui P. Martins","doi":"10.1109/OJCAS.2023.3256368","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3256368","url":null,"abstract":"This paper reports an ultra-low-voltage (ULV) single-crystal oscillator-timer (XO-Timer) for sub-0.5 V Bluetooth low-energy (BLE) radios that aims for self-powering by harvesting the ambient energies. Specifically, we tailor an on-chip micropower manager <inline-formula> <tex-math notation=\"LaTeX\">$(mu $ </tex-math></inline-formula>PM) to customize the voltage and current budgets for each sub-function of the XO-Timer. Such <inline-formula> <tex-math notation=\"LaTeX\">$mu $ </tex-math></inline-formula>PM shows a high power efficiency by introducing a 3-stage cascaded structure and a single voltage-regulation loop; they together uphold the performance of the XO-Timer amid supply-voltage and temperature variations. The core amplifier of the XO-Timer is ULV-enabled, and is reconfigurable (i.e., 1-stage and 3-stage gm) to balance between the power budget and performance under the high-performance mode (HPM) and low-power mode (LPM). Fabricated in 28-nm CMOS, the XO-Timer in HPM generates a 16-MHz clock with a power of <inline-formula> <tex-math notation=\"LaTeX\">$24.3 ~mu text{W}$ </tex-math></inline-formula>, and a phase noise of −133.8 dBc/Hz at 1-kHz offset, resulting in a Figure-of-Merit (FoM1) of −236 dBc/Hz. In the LPM, the XO-Timer delivers a 32.258-kHz clock while consuming <inline-formula> <tex-math notation=\"LaTeX\">$11.4 ~mu text{W}$ </tex-math></inline-formula>. The sleep-timer FoM2 is <inline-formula> <tex-math notation=\"LaTeX\">$14.8 ~mu text{W}$ </tex-math></inline-formula> and the Allan deviation is 35.1 ppb, achieving the lowest supply voltage (0.25 V) not only for a dual-mode XO-Timer but also for a MHz-range XO.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"126-138"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10068768.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wireless sensing and communication for space exploration in areas inaccessible to human often suffer from severe performance degradation due to the cryogenic effects on the transmitters’ circuits. To survive extreme temperatures, programmable radio frequency (RF) power amplifiers (PA) can be built into the transmitter, and intelligent PA controllers need to be integrated into the system to interact with the environment and restore the PA’s functionalities. This problem can be modeled as the controller acts (control the PA) in an environment to maximize the reward (signal quality), and it is most suitable to use reinforcement learning as a solution. This paper presents a cryogenic and energy-efficient reinforcement learning (RL) module on Field Programmable Gate Arrays (FPGA) that can directly program the PA. By characterizing a self-healing PA in a liquid nitrogen environment, we generated an RF signal data set and built an interactive RL environment to model the PA’s behaviors across its configurations and cryogenic temperatures down to −197°C. We developed a deep RL model with a high generalization capability introduced by the neural networks to control the PA and restore its performance. The RL model with fixed-point training and inference is implemented on FPGA to survive the cryogenic conditions and carry out fast and low-power training and inference for PA control. All functionalities of the programmed FPGA operate correctly in the cryogenic testing environment.
{"title":"Deep Reinforcement Learning on FPGA for Self-Healing Cryogenic Power Amplifier Control","authors":"Jiachen Xu;Yuyi Shen;Jinho Yi;Ethan Chen;Vanessa Chen","doi":"10.1109/OJCAS.2023.3282929","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3282929","url":null,"abstract":"Wireless sensing and communication for space exploration in areas inaccessible to human often suffer from severe performance degradation due to the cryogenic effects on the transmitters’ circuits. To survive extreme temperatures, programmable radio frequency (RF) power amplifiers (PA) can be built into the transmitter, and intelligent PA controllers need to be integrated into the system to interact with the environment and restore the PA’s functionalities. This problem can be modeled as the controller acts (control the PA) in an environment to maximize the reward (signal quality), and it is most suitable to use reinforcement learning as a solution. This paper presents a cryogenic and energy-efficient reinforcement learning (RL) module on Field Programmable Gate Arrays (FPGA) that can directly program the PA. By characterizing a self-healing PA in a liquid nitrogen environment, we generated an RF signal data set and built an interactive RL environment to model the PA’s behaviors across its configurations and cryogenic temperatures down to −197°C. We developed a deep RL model with a high generalization capability introduced by the neural networks to control the PA and restore its performance. The RL model with fixed-point training and inference is implemented on FPGA to survive the cryogenic conditions and carry out fast and low-power training and inference for PA control. All functionalities of the programmed FPGA operate correctly in the cryogenic testing environment.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"176-187"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10143969.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1109/OJCAS.2023.3305557
Syed Farah Naz;Ambika Prasad Shah
The reversible gate has been one of the emerging research areas that ensure a continual process of innovation trends that explore and utilizes the resources. This review paper provides a comprehensive overview of reversible gates, including their fundamental principles, design methodologies, and various applications. It also analyzes the reversible gates, comparing them based on metrics such as Quantum Cost, Complexity, and other performance evaluation measures. The analysis of several reversible gates is presented in this paper and provides a comprehensive overview of reversible gates, encompassing their fundamental principles, design methodologies, and diverse applications. Reversible logic circuits allow for the production of both unique outputs and distinct input combinations. The majority of the findings about the reversible gates from previous research papers are discussed and contrasted. All the reversible gates that have been proposed till now are presented in tabular form and the parameters are discussed to help the researchers to find every detail related to the reversible gates. To highlight our understanding, we have ended most of the sections with questions. The inclusion of questions is likely intended to stimulate further discussion and promote a deeper understanding of the material presented in this paper. These questions can serve as prompts for readers to reflect on the content and potentially explore related research directions or areas of improvement.
{"title":"Reversible Gates: A Paradigm Shift in Computing","authors":"Syed Farah Naz;Ambika Prasad Shah","doi":"10.1109/OJCAS.2023.3305557","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3305557","url":null,"abstract":"The reversible gate has been one of the emerging research areas that ensure a continual process of innovation trends that explore and utilizes the resources. This review paper provides a comprehensive overview of reversible gates, including their fundamental principles, design methodologies, and various applications. It also analyzes the reversible gates, comparing them based on metrics such as Quantum Cost, Complexity, and other performance evaluation measures. The analysis of several reversible gates is presented in this paper and provides a comprehensive overview of reversible gates, encompassing their fundamental principles, design methodologies, and diverse applications. Reversible logic circuits allow for the production of both unique outputs and distinct input combinations. The majority of the findings about the reversible gates from previous research papers are discussed and contrasted. All the reversible gates that have been proposed till now are presented in tabular form and the parameters are discussed to help the researchers to find every detail related to the reversible gates. To highlight our understanding, we have ended most of the sections with questions. The inclusion of questions is likely intended to stimulate further discussion and promote a deeper understanding of the material presented in this paper. These questions can serve as prompts for readers to reflect on the content and potentially explore related research directions or areas of improvement.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"241-257"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10218349.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49910075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As integrated circuit (IC) designs become more and more complex, the globalization of the IC supply chain has become inevitable. Because multiple entities are required to design, fabricate, test, and distribute an IC, the need for reliable security and assurance methods to maintain trust throughout the entire supply chain has never been more critical. This tutorial introduces a variety of mixed-signal approaches to combat electronic counterfeiting. An LDO-based odometer capable of accurately classifying ICs as new or aged is presented as a promising method for detecting counterfeit and recycled ICs. Additionally, this tutorial discusses the use of physical unclonable functions (PUFs) as primitives for generating cryptographic keys for digital signatures, encryption, or authentication. The design process of all PUFs is introduced and the key characteristics and evaluation metrics of state-of-the-art PUFs are defined. Finally, to promote digital IP protection, several methods for camouflaged digital gates are presented and analyzed. The threshold voltage defined (TVD) logic families discussed are capable of implementing any N-to-1 logic function and are highly resilient to reverse engineering attacks.
{"title":"A Brief Tutorial on Mixed Signal Approaches to Combat Electronic Counterfeiting","authors":"Troy Bryant;Yingjie Chen;David Selasi Koblah;Domenic Forte;Nima Maghari","doi":"10.1109/OJCAS.2023.3253144","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3253144","url":null,"abstract":"As integrated circuit (IC) designs become more and more complex, the globalization of the IC supply chain has become inevitable. Because multiple entities are required to design, fabricate, test, and distribute an IC, the need for reliable security and assurance methods to maintain trust throughout the entire supply chain has never been more critical. This tutorial introduces a variety of mixed-signal approaches to combat electronic counterfeiting. An LDO-based odometer capable of accurately classifying ICs as new or aged is presented as a promising method for detecting counterfeit and recycled ICs. Additionally, this tutorial discusses the use of physical unclonable functions (PUFs) as primitives for generating cryptographic keys for digital signatures, encryption, or authentication. The design process of all PUFs is introduced and the key characteristics and evaluation metrics of state-of-the-art PUFs are defined. Finally, to promote digital IP protection, several methods for camouflaged digital gates are presented and analyzed. The threshold voltage defined (TVD) logic families discussed are capable of implementing any N-to-1 logic function and are highly resilient to reverse engineering attacks.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"99-114"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10064465.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1109/OJCAS.2023.3292109
Dara Nagaraju;Nitin Chandrachoodan
Convolutional Neural Networks (CNNs) have been shown to achieve state of the art results on several image processing tasks such as classification, localization, and segmentation. Convolutional and fully connected layers form the building blocks of these networks. The convolution layers are responsible for the majority of the computations even though they have fewer parameters. As inference is used much more than training (which happens only once), it is important to reduce the computations of the network for this phase. This work presents a systematic procedure to trim CNNs by identifying the least important features in the convolution layers and replacing them either with approximations or kernels of reduced size. We also propose an algorithm to integrate the lower kernel approximation technique for a given accuracy budget. We show that using the linear approximation method can achieve a 15% – 80% savings with a median of 52% reduction while the lower kernel method can achieve 33% – 95% reduction with a median of 65% in the required number of computations with only a marginal 1% loss in accuracy across several benchmark datasets. We have also demonstrated the proposed methods on VGG-16 architecture for various datasets. On VGG-16 we have achieved 4.2% - 45% savings in MAC computations (with a median of 18.5%) with only a marginal 0.5% loss in accuracy. We also show how an existing hardware accelerator for DNNs (DianNao) can be modified with low added complexity to take advantage of the kernel approximations, and estimate the speedups that can be obtained in such a way on custom embedded hardware.
{"title":"Slimmer CNNs Through Feature Approximation and Kernel Size Reduction","authors":"Dara Nagaraju;Nitin Chandrachoodan","doi":"10.1109/OJCAS.2023.3292109","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3292109","url":null,"abstract":"Convolutional Neural Networks (CNNs) have been shown to achieve state of the art results on several image processing tasks such as classification, localization, and segmentation. Convolutional and fully connected layers form the building blocks of these networks. The convolution layers are responsible for the majority of the computations even though they have fewer parameters. As inference is used much more than training (which happens only once), it is important to reduce the computations of the network for this phase. This work presents a systematic procedure to trim CNNs by identifying the least important features in the convolution layers and replacing them either with approximations or kernels of reduced size. We also propose an algorithm to integrate the lower kernel approximation technique for a given accuracy budget. We show that using the linear approximation method can achieve a 15% – 80% savings with a median of 52% reduction while the lower kernel method can achieve 33% – 95% reduction with a median of 65% in the required number of computations with only a marginal 1% loss in accuracy across several benchmark datasets. We have also demonstrated the proposed methods on VGG-16 architecture for various datasets. On VGG-16 we have achieved 4.2% - 45% savings in MAC computations (with a median of 18.5%) with only a marginal 0.5% loss in accuracy. We also show how an existing hardware accelerator for DNNs (DianNao) can be modified with low added complexity to take advantage of the kernel approximations, and estimate the speedups that can be obtained in such a way on custom embedded hardware.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"188-202"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10173478.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49919366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1109/OJCAS.2023.3295649
George Souliotis;Andreas Tsimpos;Spyridon Vlassis
In this paper, it is proposed a jitter analysis methodology, targeting on the optimization of a phase interpolator (PI) based clock and data recovery circuit (CDR). The methodology is applied for the optimized design of an 8-bit dual-loop CDR, designed with the CMOS TSMC 65 nm process node. The CDR is based on an extended, in terms of phase resolution, version, with a novel PI topology proposed in this work. The proposed CDR loop has a minimum frequency offset tracking ability equal to 500ppm at 5.83 Gbps, and so is suitable for adoption either in mesochronous or plesiochronous High Speed Serial Interface (HSSI) receivers. It consumes 14.2 mW with 1 V supply voltage and is able to achieve better than 10−10 Bit Error Rate (BER) performance. The CDR loop performance verification has been realized through the AMS simulator of Analog Design Environment of Cadence, by co-simulations of the transistor level CDR circuit with the Verilog-AMS based jitter generator.
{"title":"Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization","authors":"George Souliotis;Andreas Tsimpos;Spyridon Vlassis","doi":"10.1109/OJCAS.2023.3295649","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3295649","url":null,"abstract":"In this paper, it is proposed a jitter analysis methodology, targeting on the optimization of a phase interpolator (PI) based clock and data recovery circuit (CDR). The methodology is applied for the optimized design of an 8-bit dual-loop CDR, designed with the CMOS TSMC 65 nm process node. The CDR is based on an extended, in terms of phase resolution, version, with a novel PI topology proposed in this work. The proposed CDR loop has a minimum frequency offset tracking ability equal to 500ppm at 5.83 Gbps, and so is suitable for adoption either in mesochronous or plesiochronous High Speed Serial Interface (HSSI) receivers. It consumes 14.2 mW with 1 V supply voltage and is able to achieve better than 10−10 Bit Error Rate (BER) performance. The CDR loop performance verification has been realized through the AMS simulator of Analog Design Environment of Cadence, by co-simulations of the transistor level CDR circuit with the Verilog-AMS based jitter generator.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"203-217"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10184121.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49919367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1109/OJCAS.2023.3270752
Mathieu Xhonneux;Jérôme Louveaux;David Bol
We present an Internet-of-Things (IoT) software-defined radio platform based on an ultra low-power microcontroller. Whereas conventional wireless IoT radios often implement a single protocol, we demonstrate that general-purpose microcontrollers running software implementations of wireless physical layers are a promising solution to increase interoperability of IoT devices. Yet, since IoT devices are often energy-constrained, the underlying challenge is to implement the digital signal processing of the radio in software while maintaining an overall very low power consumption. To overcome this problem, we propose an ultra low-power microcontroller architecture with an ARM Cortex-M4 processor for the protocol-specific computations and a hardware digital front-end for the generic signal processing. The proposed architecture has been prototyped in 28nm FDSOI and the physical layers of the well-known LoRa and Sigfox protocols have been implemented in software. Thanks to the efficient hardware/software partitioning and an ultra-low power digital implementation, experimental evaluations of the microcontroller prototype show sub-mW power consumptions (32 – $332~mu text{W}$ ) for the digital signal processing of the software-defined radios.
{"title":"A Sub-mW Cortex-M4 Microcontroller Design for IoT Software-Defined Radios","authors":"Mathieu Xhonneux;Jérôme Louveaux;David Bol","doi":"10.1109/OJCAS.2023.3270752","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3270752","url":null,"abstract":"We present an Internet-of-Things (IoT) software-defined radio platform based on an ultra low-power microcontroller. Whereas conventional wireless IoT radios often implement a single protocol, we demonstrate that general-purpose microcontrollers running software implementations of wireless physical layers are a promising solution to increase interoperability of IoT devices. Yet, since IoT devices are often energy-constrained, the underlying challenge is to implement the digital signal processing of the radio in software while maintaining an overall very low power consumption. To overcome this problem, we propose an ultra low-power microcontroller architecture with an ARM Cortex-M4 processor for the protocol-specific computations and a hardware digital front-end for the generic signal processing. The proposed architecture has been prototyped in 28nm FDSOI and the physical layers of the well-known LoRa and Sigfox protocols have been implemented in software. Thanks to the efficient hardware/software partitioning and an ultra-low power digital implementation, experimental evaluations of the microcontroller prototype show sub-mW power consumptions (32 – $332~mu text{W}$ ) for the digital signal processing of the software-defined radios.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"165-175"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10109258.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1109/OJCAS.2023.3240644
Noora Almarri;Dai Jiang;Peter J. Langlois;Mohamad Rahal;Andreas Demosthenous
Battery-less active implantable devices are of interest because they offer longer life span and eliminate costly battery replacement surgical interventions. This is possible as a result of advances in inductive power transfer and development of power management circuits to maximize the overall power transfer and provide various voltage levels for multi-functional implantable devices. Rehabilitation therapy using optical stimulation of genetically modified peripheral neurons requires high current loads. Standard rectification topologies are inefficient and have associated voltage drops unsuited for miniaturized implants. This paper presents an integrated power management unit (PMU) for an optical-electrical stimulator to be used in the treatment of motor neurone disease. It includes a power-efficient regulating rectifier with a novel body biased high-speed comparator providing 3.3 V for the operation of the stimulator, a 3-stage latch-up charge pump with 12 V output for the input stage of the optical-electrical stimulator, and 1.8 V for digital control logic. The chip was fabricated in a $0.18 ~mu text{m}$ CMOS process. Measured results show that for a regulated output of 3.3 V delivering 30.3 mW power, the peak power conversion efficiency is 84.2% at 6.78 MHz inductive link tunable frequency reducing to 70.3% at 13.56 MHz. The charge pump with on chip capacitors has 90.9% measured voltage conversion efficiency.
{"title":"High Efficiency Power Management Unit for Implantable Optical-Electrical Stimulators","authors":"Noora Almarri;Dai Jiang;Peter J. Langlois;Mohamad Rahal;Andreas Demosthenous","doi":"10.1109/OJCAS.2023.3240644","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3240644","url":null,"abstract":"Battery-less active implantable devices are of interest because they offer longer life span and eliminate costly battery replacement surgical interventions. This is possible as a result of advances in inductive power transfer and development of power management circuits to maximize the overall power transfer and provide various voltage levels for multi-functional implantable devices. Rehabilitation therapy using optical stimulation of genetically modified peripheral neurons requires high current loads. Standard rectification topologies are inefficient and have associated voltage drops unsuited for miniaturized implants. This paper presents an integrated power management unit (PMU) for an optical-electrical stimulator to be used in the treatment of motor neurone disease. It includes a power-efficient regulating rectifier with a novel body biased high-speed comparator providing 3.3 V for the operation of the stimulator, a 3-stage latch-up charge pump with 12 V output for the input stage of the optical-electrical stimulator, and 1.8 V for digital control logic. The chip was fabricated in a $0.18 ~mu text{m}$ CMOS process. Measured results show that for a regulated output of 3.3 V delivering 30.3 mW power, the peak power conversion efficiency is 84.2% at 6.78 MHz inductive link tunable frequency reducing to 70.3% at 13.56 MHz. The charge pump with on chip capacitors has 90.9% measured voltage conversion efficiency.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"3-14"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10029935.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49910009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1109/OJCAS.2023.3299052
Ti-Yu Chen;Zhi-Jing Lin;Tzi-Dar Chiueh
Massive Machine-type Communications (mMTCs) is a major use case for the 5G standard. The grant-free (GF) sparse-coded multiple access (SCMA) transmission is particularly spectrum efficient in the sporadic uplink traffic, which is characteristic of the mMTC networks. In this paper, an uplink GF-SCMA receiver with a user activity detection (UAD) function was designed and implemented. In particular, several new techniques were proposed to enhance the SCMA decoder performance; they include delayed serial update, early stopping, message passing algorithm equation reformulation, distance approximation, and sum circuit sharing. To meet the real-time operation requirements, we implemented key inner receiver function circuits, such as carrier frequency synchronization, user signature detection, channel estimation and compensation, soft SCMA detection, etc. on a Xilinx KCU1500 FPGA chip. Finally, an over-the-air (OTA) prototype has been constructed, demonstrating the efficient and reliable multi-user GF-SCMA uplink transmission of the proposed system.
{"title":"Grant-Free Sparse Code Multiple Access for Uplink Massive Machine-Type Communications and Its Real-Time Receiver Design","authors":"Ti-Yu Chen;Zhi-Jing Lin;Tzi-Dar Chiueh","doi":"10.1109/OJCAS.2023.3299052","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3299052","url":null,"abstract":"Massive Machine-type Communications (mMTCs) is a major use case for the 5G standard. The grant-free (GF) sparse-coded multiple access (SCMA) transmission is particularly spectrum efficient in the sporadic uplink traffic, which is characteristic of the mMTC networks. In this paper, an uplink GF-SCMA receiver with a user activity detection (UAD) function was designed and implemented. In particular, several new techniques were proposed to enhance the SCMA decoder performance; they include delayed serial update, early stopping, message passing algorithm equation reformulation, distance approximation, and sum circuit sharing. To meet the real-time operation requirements, we implemented key inner receiver function circuits, such as carrier frequency synchronization, user signature detection, channel estimation and compensation, soft SCMA detection, etc. on a Xilinx KCU1500 FPGA chip. Finally, an over-the-air (OTA) prototype has been constructed, demonstrating the efficient and reliable multi-user GF-SCMA uplink transmission of the proposed system.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"218-227"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10195181.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49919368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-24DOI: 10.1109/OJCAS.2022.3219531
Ping-Hsuan Hsieh;Vanessa Chen
This Special Section of the IEEE Open Journal of Circuits and Systems is dedicated to a collection of articles on Smart Imaging, to promote techniques in both system and circuit levels to tackle various challenges as the requirements for image quality, efficiency, and levels of integration keep increasing and to provide insightful guidelines for intelligent vision in the years to come. This Special Section covers articles for applications including vision system, time-of-flight system, and terahertz imaging system.
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