Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015423
H. Park, D. Schepis, A. Mocuta, M. Khare, Y. Li, B. Doris, S. Shukla, T. Hughes, O. Dokumaci, S. Narasimha, S. Fung, J. Snare, B. Lee, J. Li, P. Ronsheim, A. Domenicucci, P. Varekamp, A. Ajmera, J. Sleight, P. O'Neil, E. Maciejewski, C. Lavoie
We present a systematic study on maximizing polysilicon gate activation for aggressively scaled 0.1 /spl mu/m CMOS technologies. The fundamental limit of gate activation due to poly depletion effect was investigated in terms of gate implant/anneal condition and sequence, poly grain size, dopant penetration and activation. For the first time, we achieved significant improvement in CMOS performance by developing a novel process of "gate postdoping" to decouple implant and anneals for gate, source/drain, and extension. The method successfully reduces the poly depletion effect and thus the equivalent gate oxide thickness in inversion by up to /spl sim/2 /spl Aring/, improving CMOS on-currents by 9/spl sim/33% over a conventional process.
{"title":"Gate postdoping to decouple implant/anneal for gate, source/drain, and extension: maximizing polysilicon gate activation for 0.1 /spl mu/m CMOS technologies","authors":"H. Park, D. Schepis, A. Mocuta, M. Khare, Y. Li, B. Doris, S. Shukla, T. Hughes, O. Dokumaci, S. Narasimha, S. Fung, J. Snare, B. Lee, J. Li, P. Ronsheim, A. Domenicucci, P. Varekamp, A. Ajmera, J. Sleight, P. O'Neil, E. Maciejewski, C. Lavoie","doi":"10.1109/VLSIT.2002.1015423","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015423","url":null,"abstract":"We present a systematic study on maximizing polysilicon gate activation for aggressively scaled 0.1 /spl mu/m CMOS technologies. The fundamental limit of gate activation due to poly depletion effect was investigated in terms of gate implant/anneal condition and sequence, poly grain size, dopant penetration and activation. For the first time, we achieved significant improvement in CMOS performance by developing a novel process of \"gate postdoping\" to decouple implant and anneals for gate, source/drain, and extension. The method successfully reduces the poly depletion effect and thus the equivalent gate oxide thickness in inversion by up to /spl sim/2 /spl Aring/, improving CMOS on-currents by 9/spl sim/33% over a conventional process.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132877222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015402
T. Ernst, J. Hartmann, V. Loup, F. Ducroquet, P. Dollfus, G. Guégan, D. Lafond, P. Hilliger, B. Previtali, A. Toffoli, S. Deleonibus
We present for the first time tensile-strained epitaxially grown Si:C and SiGe:C channel NMOS devices compatible with a standard 50 nm CMOS process flow. Some of the advantages of this new architecture for CMOS integration are a highly retrograde channel doping profile and a suppression of boron diffusion and Oxidation Enhanced Diffusion (OED). Those properties lead to a dramatic decrease of short channel effects. Transport in the Si:C and SiGe:C inversion layers is characterized for the first time (77 K to 300 K) and the associated scattering mechanisms are identified. Finely tuned carbon concentration have a strong impact on transport properties.
{"title":"Fabrication of a novel strained SiGe:C-channel planar 55 nm nMOSFET for high-performance CMOS","authors":"T. Ernst, J. Hartmann, V. Loup, F. Ducroquet, P. Dollfus, G. Guégan, D. Lafond, P. Hilliger, B. Previtali, A. Toffoli, S. Deleonibus","doi":"10.1109/VLSIT.2002.1015402","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015402","url":null,"abstract":"We present for the first time tensile-strained epitaxially grown Si:C and SiGe:C channel NMOS devices compatible with a standard 50 nm CMOS process flow. Some of the advantages of this new architecture for CMOS integration are a highly retrograde channel doping profile and a suppression of boron diffusion and Oxidation Enhanced Diffusion (OED). Those properties lead to a dramatic decrease of short channel effects. Transport in the Si:C and SiGe:C inversion layers is characterized for the first time (77 K to 300 K) and the associated scattering mechanisms are identified. Finely tuned carbon concentration have a strong impact on transport properties.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123319649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015439
J. Cai, A. Ajmera, C. Ouyang, P. Oldiges, M. Steigerwalt, K. Stein, K. Jenkins, G. Shahidi, T. Ning
A novel vertical bipolar transistor on SOI is proposed and demonstrated. The transistor operates on the principle that the collector region is fully depleted so that the charge carriers travel laterally towards the collector reachthrough and contact after traversing the intrinsic base layer. The SOI silicon layer thickness is comparable to that used in SOI CMOS, and no subcollector layer or deep trench isolation are required. Simulated device characteristics are shown. The transistor is demonstrated in a polysilicon-emitter SiGe-base npn implementation on SOI with a 140-nm silicon layer. The fabricated npn bipolar transistors exhibit a BVceo of 4.2 V and a peak f/sub T/ of over 60 GHz.
{"title":"Fully-depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI","authors":"J. Cai, A. Ajmera, C. Ouyang, P. Oldiges, M. Steigerwalt, K. Stein, K. Jenkins, G. Shahidi, T. Ning","doi":"10.1109/VLSIT.2002.1015439","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015439","url":null,"abstract":"A novel vertical bipolar transistor on SOI is proposed and demonstrated. The transistor operates on the principle that the collector region is fully depleted so that the charge carriers travel laterally towards the collector reachthrough and contact after traversing the intrinsic base layer. The SOI silicon layer thickness is comparable to that used in SOI CMOS, and no subcollector layer or deep trench isolation are required. Simulated device characteristics are shown. The transistor is demonstrated in a polysilicon-emitter SiGe-base npn implementation on SOI with a 140-nm silicon layer. The fabricated npn bipolar transistors exhibit a BVceo of 4.2 V and a peak f/sub T/ of over 60 GHz.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122206089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015413
T. Yamada, K. Takahashi, H. Oyamatsu, H. Nagano, T. Sato, I. Mizushima, S. Nitta, T. Hojo, K. Kokubun, K. Yasumoto, Y. Matsubara, T. Yoshida, S. Yamada, Y. Tsunashima, Y. Saito, S. Nadahara, Y. Katsumata, M. Yoshimi, H. Ishiuchi
A highly manufacturable embedded DRAM technology in SOI (Silicon On Insulator) has been developed for high-end SOC (System On a Chip). Partial etching of SOI/BOX (Buried OXide) layers and SEG (Selective Epitaxial Growth) processes simply transform an SOI wafer into a high quality SOI/bulk hybrid substrate wafer, which has both SOI substrate regions and bulk epitaxial Si regions. DRAM macros developed for the bulk can be introduced in SOI without any modification of the design and process, resulting in stable DRAM operation freed from floating-body effects. Fabrication of 1 Mb ADMs (Array Diagnostic Monitors) on the hybrid substrate wafer with the 0.18 /spl mu/m embedded DRAM process has attained all-bits-functional yield of 90%. Moreover, excellent data retention characteristics, by no means inferior to those for a bulk wafer, were obtained in SOI for the first time. The proposed methodology is attractive for SOI SOC, where high band width with low power consumption due to DRAM-embedding as well as high-speed/low-power circuit performance of SOI logic can be enjoyed.
{"title":"An embedded DRAM technology on SOI/bulk hybrid substrate formed with SEG process for high-end SOC application","authors":"T. Yamada, K. Takahashi, H. Oyamatsu, H. Nagano, T. Sato, I. Mizushima, S. Nitta, T. Hojo, K. Kokubun, K. Yasumoto, Y. Matsubara, T. Yoshida, S. Yamada, Y. Tsunashima, Y. Saito, S. Nadahara, Y. Katsumata, M. Yoshimi, H. Ishiuchi","doi":"10.1109/VLSIT.2002.1015413","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015413","url":null,"abstract":"A highly manufacturable embedded DRAM technology in SOI (Silicon On Insulator) has been developed for high-end SOC (System On a Chip). Partial etching of SOI/BOX (Buried OXide) layers and SEG (Selective Epitaxial Growth) processes simply transform an SOI wafer into a high quality SOI/bulk hybrid substrate wafer, which has both SOI substrate regions and bulk epitaxial Si regions. DRAM macros developed for the bulk can be introduced in SOI without any modification of the design and process, resulting in stable DRAM operation freed from floating-body effects. Fabrication of 1 Mb ADMs (Array Diagnostic Monitors) on the hybrid substrate wafer with the 0.18 /spl mu/m embedded DRAM process has attained all-bits-functional yield of 90%. Moreover, excellent data retention characteristics, by no means inferior to those for a bulk wafer, were obtained in SOI for the first time. The proposed methodology is attractive for SOI SOC, where high band width with low power consumption due to DRAM-embedding as well as high-speed/low-power circuit performance of SOI logic can be enjoyed.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133407847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015424
K. Itonaga, K. Eriguchi, I. Miyanaga, A. Kajiya, M. Ogura, T. Tsutsumi, H. Sayama, H. Oda, T. Eimori, H. Morimoto
We propose the "bi-layer" CoSi/sub 2/ structure with smaller grain size, which realizes low sheet resistance for 35 nm gate length as well as low junction leakage current for 100 nm junction depth for the first time. The formation of the bi-layer CoSi/sub 2/ structure is successfully controlled by the N/sub 2/ ion implantation with low energy and high dosage, and enables us to manufacture sub-50 nm CMOS devices.
{"title":"A novel bi-layer cobalt silicide process with nitrogen implantation for sub-50 nm CMOS and beyond","authors":"K. Itonaga, K. Eriguchi, I. Miyanaga, A. Kajiya, M. Ogura, T. Tsutsumi, H. Sayama, H. Oda, T. Eimori, H. Morimoto","doi":"10.1109/VLSIT.2002.1015424","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015424","url":null,"abstract":"We propose the \"bi-layer\" CoSi/sub 2/ structure with smaller grain size, which realizes low sheet resistance for 35 nm gate length as well as low junction leakage current for 100 nm junction depth for the first time. The formation of the bi-layer CoSi/sub 2/ structure is successfully controlled by the N/sub 2/ ion implantation with low energy and high dosage, and enables us to manufacture sub-50 nm CMOS devices.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134315333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015411
S. Monfray, T. Skotnicki, Y. Morand, S. Descombes, P. Coronel, P. Mazoyer, S. Harrison, P. Ribot, A. Talbot, D. Dutartre, M. Haond, R. Palla, Y. L. Friec, F. Leverd, M. Nier, C. Vizioz, D. Louis
For the first time, both GAA and bulk devices were shown to be operational on the same chip. Not all issues have been solved yet (gate materials, access resistance) but already the first-try results are very encouraging: I/sub on/=170 /spl mu/A//spl mu/m@1.2 V and gate oxide of 20 /spl Aring/. Thanks to the GAA intrinsic immunity to SCE, its DIBL was as small as 10 mV compared with 600 mV on bulk control devices. Calibrating a 2D simulator on this electrical data, the performance of the GAA was estimated to be at least 1500 /spl mu/A//spl mu/m@ 1 V with comfortable gate oxide of 20 /spl Aring/, once having corrected for the large R/sub access/ (/spl sim/3000 /spl Omega/), that was simply due to non-optimal mask layout used in this first device realization.
{"title":"50 nm-Gate All Around (GAA)-Silicon On Nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process","authors":"S. Monfray, T. Skotnicki, Y. Morand, S. Descombes, P. Coronel, P. Mazoyer, S. Harrison, P. Ribot, A. Talbot, D. Dutartre, M. Haond, R. Palla, Y. L. Friec, F. Leverd, M. Nier, C. Vizioz, D. Louis","doi":"10.1109/VLSIT.2002.1015411","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015411","url":null,"abstract":"For the first time, both GAA and bulk devices were shown to be operational on the same chip. Not all issues have been solved yet (gate materials, access resistance) but already the first-try results are very encouraging: I/sub on/=170 /spl mu/A//spl mu/m@1.2 V and gate oxide of 20 /spl Aring/. Thanks to the GAA intrinsic immunity to SCE, its DIBL was as small as 10 mV compared with 600 mV on bulk control devices. Calibrating a 2D simulator on this electrical data, the performance of the GAA was estimated to be at least 1500 /spl mu/A//spl mu/m@ 1 V with comfortable gate oxide of 20 /spl Aring/, once having corrected for the large R/sub access/ (/spl sim/3000 /spl Omega/), that was simply due to non-optimal mask layout used in this first device realization.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115909056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015461
Y. Huh, V. Axerad, J.W. Chen, P. Bendix
We present a multi-finger turn-on model incorporating substrate coupling effects in multi-finger NMOS transistors during ESD events. It is demonstrated that the substrate coupling enables uniform triggering in a multi-finger structure. In addition, we show that fully silicided transistors can be used successfully as an ESD protection device without any design/process options if the effective epi thickness is larger than 1.5 /spl mu/m or bulk wafer is used.
{"title":"The effects of substrate coupling on triggering uniformity and ESD failure threshold of fully silicided NMOS transistors","authors":"Y. Huh, V. Axerad, J.W. Chen, P. Bendix","doi":"10.1109/VLSIT.2002.1015461","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015461","url":null,"abstract":"We present a multi-finger turn-on model incorporating substrate coupling effects in multi-finger NMOS transistors during ESD events. It is demonstrated that the substrate coupling enables uniform triggering in a multi-finger structure. In addition, we show that fully silicided transistors can be used successfully as an ESD protection device without any design/process options if the effective epi thickness is larger than 1.5 /spl mu/m or bulk wafer is used.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132980340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015419
M. Mehrotra, J. Wu, A. Jain, T. Laaksonen, K. Kim, W. Bather, R. Koshy, J. Chen, J. Jacobs, V. Ukraintsev, L. Olsen, J. Deloach, J. Mehigan, R. Agarwal, S. Walsh, D. Sekel, L. Tsung, M. Vaidyanathan, B. Trentman, K. Liu, S. Aur, R. Khamankar, P. Nicollian, Q. Jiang, Y. Xu, B. Campbell, P. Tiner, R. Wise, D. Scott, M. Rodder
In this work, we present a 60 nm gate length CMOS for high performance applications at the 0.13 /spl mu/m CMOS node. The technology utilizes 193 nm gate lithography, dual spacers with thin spacer before drain extension implant and L-shaped nitride spacer after drain extensions, and remote-plasma nitrided dielectric with 1.75 nm EOT. 10-15% improvement in drive current is achieved with lower series resistance by reduction of dopant loss and higher dopant activation, resulting in n- and pMOS I/sub drive/ of 1160 /spl mu/A//spl mu/m and 550 /spl mu/A//spl mu/m at 1.3 V at I/sub off/=100 nA//spl mu/m.
在这项工作中，我们提出了一种60 nm栅长CMOS，用于0.13 /spl mu/m CMOS节点的高性能应用。该技术采用193nm栅极光刻技术，在漏极延伸植入前采用薄间隔层，漏极延伸植入后采用l形氮化间隔层的双间隔层，以及1.75 nm EOT的远程等离子体氮化电介质。通过减少掺杂损耗和提高掺杂激活度，在降低串联电阻的情况下实现了10-15%的驱动电流提高，从而使n-和pMOS的I/sub驱动在1.3 V下为1160 /spl μ l /A//spl μ l μ m和550 /spl μ l μ l /A//spl μ m, I/sub off =100 nA//spl μ m。
{"title":"60 nm gate length dual-Vt CMOS for high performance applications","authors":"M. Mehrotra, J. Wu, A. Jain, T. Laaksonen, K. Kim, W. Bather, R. Koshy, J. Chen, J. Jacobs, V. Ukraintsev, L. Olsen, J. Deloach, J. Mehigan, R. Agarwal, S. Walsh, D. Sekel, L. Tsung, M. Vaidyanathan, B. Trentman, K. Liu, S. Aur, R. Khamankar, P. Nicollian, Q. Jiang, Y. Xu, B. Campbell, P. Tiner, R. Wise, D. Scott, M. Rodder","doi":"10.1109/VLSIT.2002.1015419","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015419","url":null,"abstract":"In this work, we present a 60 nm gate length CMOS for high performance applications at the 0.13 /spl mu/m CMOS node. The technology utilizes 193 nm gate lithography, dual spacers with thin spacer before drain extension implant and L-shaped nitride spacer after drain extensions, and remote-plasma nitrided dielectric with 1.75 nm EOT. 10-15% improvement in drive current is achieved with lower series resistance by reduction of dopant loss and higher dopant activation, resulting in n- and pMOS I/sub drive/ of 1160 /spl mu/A//spl mu/m and 550 /spl mu/A//spl mu/m at 1.3 V at I/sub off/=100 nA//spl mu/m.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120934341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015420
H. Rhee, J. Lee, Sang S. Kim, G. Bae, N. Lee, Do Hyung Kim, J. Hong, Ho-Kyu Kang, K. Suh
A new double-layered structure of poly-Si/SiGe gate has been proposed to improve the current performance of CMOSFETs and the reproducibility of devices. The double-layered poly-Si/SiGe stack has small-sized (columnar) grains in the lower poly-SiGe layer and large-sized grains in the upper poly-Si layer. The new structure can suppress Ge diffusion into the upper poly-Si layer during CMOS process, resulting in enhanced current performance and better sheet resistance distribution to meet gate height scaling requirements of sub-0.1 /spl mu/m CMOSFETs. A mass productive 8 Mbit SRAM with both the smallest cell size and enhanced operation speed by 20% was successfully fabricated using the proposed poly-SiGe gate structure.
{"title":"A new double-layered structure for mass-production-worthy CMOSFETs with poly-SiGe gate","authors":"H. Rhee, J. Lee, Sang S. Kim, G. Bae, N. Lee, Do Hyung Kim, J. Hong, Ho-Kyu Kang, K. Suh","doi":"10.1109/VLSIT.2002.1015420","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015420","url":null,"abstract":"A new double-layered structure of poly-Si/SiGe gate has been proposed to improve the current performance of CMOSFETs and the reproducibility of devices. The double-layered poly-Si/SiGe stack has small-sized (columnar) grains in the lower poly-SiGe layer and large-sized grains in the upper poly-Si layer. The new structure can suppress Ge diffusion into the upper poly-Si layer during CMOS process, resulting in enhanced current performance and better sheet resistance distribution to meet gate height scaling requirements of sub-0.1 /spl mu/m CMOSFETs. A mass productive 8 Mbit SRAM with both the smallest cell size and enhanced operation speed by 20% was successfully fabricated using the proposed poly-SiGe gate structure.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115000680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-06-11DOI: 10.1109/VLSIT.2002.1015369
K. Tomita, K. Hashimoto, T. Inbe, T. Oashi, K. Tsukamoto, Y. Nishioka, M. Matsuura, T. Eimori, M. Inuishi, I. Miyanaga, M. Nakamura, T. Kishimoto, T. Yamada, K. Eriguchi, H. Yuasa, T. Satake, A. Kajiya, M. Ogura
We have integrated a high speed and high density 6T-SRAM cell (0.998 /spl mu/m/sup 2/) for system-on-a-chip (SOC) using enhanced 100 nm CMOS logic technology. This is achieved by a systematic integration methodology, which includes high-NA ArF lithography, optimized optical proximity correction (OPC) CAD, narrow well isolation, poly-buffered shallow trench isolation (STI), offset spacer transistor, and 9-level Cu interconnect and low-k dielectric technologies with the lithographically scalable SRAM cell design.
{"title":"Sub-1 /spl mu/m/sup 2/ high density embedded SRAM technologies for 100 nm generation SOC and beyond","authors":"K. Tomita, K. Hashimoto, T. Inbe, T. Oashi, K. Tsukamoto, Y. Nishioka, M. Matsuura, T. Eimori, M. Inuishi, I. Miyanaga, M. Nakamura, T. Kishimoto, T. Yamada, K. Eriguchi, H. Yuasa, T. Satake, A. Kajiya, M. Ogura","doi":"10.1109/VLSIT.2002.1015369","DOIUrl":"https://doi.org/10.1109/VLSIT.2002.1015369","url":null,"abstract":"We have integrated a high speed and high density 6T-SRAM cell (0.998 /spl mu/m/sup 2/) for system-on-a-chip (SOC) using enhanced 100 nm CMOS logic technology. This is achieved by a systematic integration methodology, which includes high-NA ArF lithography, optimized optical proximity correction (OPC) CAD, narrow well isolation, poly-buffered shallow trench isolation (STI), offset spacer transistor, and 9-level Cu interconnect and low-k dielectric technologies with the lithographically scalable SRAM cell design.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"1216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120878576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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