Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430956
Jae Chang Yang, J. Choi, Ho Jung, S. Kong
The bolometric infrared spectrometer instantaneously detects the incoming IR spectra by detecting the decrease or increase of bolometer resistance due to its temperature change caused by the incident infrared light. In this paper, the design and fabrication methods of bolometric IR spectrometer are presented. The IR spectrometer reported in this paper consists of a bolometric IR detector array made of V2O5 and a grating structure used for separating incident infrared light depending on its wavelength.
{"title":"Fabrication of a bolometric infrared micro-spectrometer","authors":"Jae Chang Yang, J. Choi, Ho Jung, S. Kong","doi":"10.1109/ESSDERC.2007.4430956","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430956","url":null,"abstract":"The bolometric infrared spectrometer instantaneously detects the incoming IR spectra by detecting the decrease or increase of bolometer resistance due to its temperature change caused by the incident infrared light. In this paper, the design and fabrication methods of bolometric IR spectrometer are presented. The IR spectrometer reported in this paper consists of a bolometric IR detector array made of V2O5 and a grating structure used for separating incident infrared light depending on its wavelength.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117120390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430951
L. La Spina, L. Nanver, H. Schellevis, E. Iborra, M. Clement, J. Olivares
Physical-vapor-deposited aluminum nitride, developed for heat spreading in RF ICs, is characterized by fabricating and measuring several different types of test structures. Among other things, it is shown that the material is a good dielectric insulator and has suitably low mechanical stress and piezoelectric response. With layers as thick as 6 mum, the electrothermal instabilities in a silicon-on-glass bipolar process are drastically reduced.
{"title":"Characterization of PVD aluminum nitride for heat spreading in RF IC's","authors":"L. La Spina, L. Nanver, H. Schellevis, E. Iborra, M. Clement, J. Olivares","doi":"10.1109/ESSDERC.2007.4430951","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430951","url":null,"abstract":"Physical-vapor-deposited aluminum nitride, developed for heat spreading in RF ICs, is characterized by fabricating and measuring several different types of test structures. Among other things, it is shown that the material is a good dielectric insulator and has suitably low mechanical stress and piezoelectric response. With layers as thick as 6 mum, the electrothermal instabilities in a silicon-on-glass bipolar process are drastically reduced.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116192567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430897
K. Okada, T. Horikawa, H. Ota, T. Nabatame, A. Toriumi
Threshold voltage (V,h) shift under the NBT-stress of TaN gated HfO2/SiO2 stacked gate dielectrics has been studied by conventional DC and the pulsed measurements. A large Vth shift in the early stage of stress occurs typically within 1 s by the fast transient charging under the stress as well as during the Vth measurement. Contributions of both charging components strongly depend on the film quality and also on the stress conditions. Therefore, an accurate deconvolution of measured DeltaVth into each component is indispensable for accurate lifetime prediction and the understandings of the NBTI reliability.
{"title":"Analysis of transient charging components in NBTI degradation studied for TaN gated HfO2/SiO2 dielectrics","authors":"K. Okada, T. Horikawa, H. Ota, T. Nabatame, A. Toriumi","doi":"10.1109/ESSDERC.2007.4430897","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430897","url":null,"abstract":"Threshold voltage (V,h) shift under the NBT-stress of TaN gated HfO2/SiO2 stacked gate dielectrics has been studied by conventional DC and the pulsed measurements. A large Vth shift in the early stage of stress occurs typically within 1 s by the fast transient charging under the stress as well as during the Vth measurement. Contributions of both charging components strongly depend on the film quality and also on the stress conditions. Therefore, an accurate deconvolution of measured DeltaVth into each component is indispensable for accurate lifetime prediction and the understandings of the NBTI reliability.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131757930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430976
G. Eneman, O. Sicart i Casain, E. Simoen, D. Brunco, B. de Jaeger, A. Satta, G. Nicholas, C. Claeys, M. Meuris, M. Heyns
We analysed heavily doped p+/n junctions in germanium, and found that the halos in this work provide a tradeoff between transistor channel control and junction leakage. Temperature-dependent leakage measurements show that either trap-assisted tunneling (TAT) or band-to-band-tunneling (BTBT) are the dominant leakage mechanisms for junctions with halos, (junction doping above ~ 1018 cm-3). Further, perimeter leakage data at/near room temperature for these junctions are consistent with the Hurckx model for TAT. At lower doping levels (no Halo), leakages are significantly lower and correspond to a shockley-read-hall (SRH) mechanism at/near room temperature and a standard diffusion current mechanism for temperatures above ~ 75degC.
{"title":"Analysis of junction leakage in advanced germanium P+/n junctions","authors":"G. Eneman, O. Sicart i Casain, E. Simoen, D. Brunco, B. de Jaeger, A. Satta, G. Nicholas, C. Claeys, M. Meuris, M. Heyns","doi":"10.1109/ESSDERC.2007.4430976","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430976","url":null,"abstract":"We analysed heavily doped p+/n junctions in germanium, and found that the halos in this work provide a tradeoff between transistor channel control and junction leakage. Temperature-dependent leakage measurements show that either trap-assisted tunneling (TAT) or band-to-band-tunneling (BTBT) are the dominant leakage mechanisms for junctions with halos, (junction doping above ~ 1018 cm-3). Further, perimeter leakage data at/near room temperature for these junctions are consistent with the Hurckx model for TAT. At lower doping levels (no Halo), leakages are significantly lower and correspond to a shockley-read-hall (SRH) mechanism at/near room temperature and a standard diffusion current mechanism for temperatures above ~ 75degC.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127982915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430898
T. Smorodin, M. Stecher, J. Wilde, M. Glavanovics
In this article the failure behavior of DMOS-switches under power-cycle stress is shown to be dominated by thermo-mechanical deformation of the metallization. The failure evolves without a significant influence from electromigration stress.
{"title":"Power-cycling of DMOS-switches triggers thermo-mechanical failure mechanisms","authors":"T. Smorodin, M. Stecher, J. Wilde, M. Glavanovics","doi":"10.1109/ESSDERC.2007.4430898","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430898","url":null,"abstract":"In this article the failure behavior of DMOS-switches under power-cycle stress is shown to be dominated by thermo-mechanical deformation of the metallization. The failure evolves without a significant influence from electromigration stress.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132216634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430963
A. Roest, K. Reimann, M. Klee
This paper discusses the investigation of thin film ferroelectric capacitors (high-K) with respect to resistance degradation. Accelerated lifetime tests under elevated temperatures of 210-290degC and dc fields of 25-250 kV/cm were performed on these high-K capacitors. The capacitors were studied, making use of the lifetime specifications for ceramic multi-layer capacitors. The increase of the current density by one order of magnitude is here defined as the lifetime of the capacitors. The capacitor under these conditions is still functioning and therefore this is not the lifetime as determined by a breakdown. The accelerated lifetime measurements are used to investigate activation energies and voltage dependences, to enable the extrapolation of the lifetime to operation conditions. It was found that the resistance degradation of these thin film capacitors is a thermally activated process. Activation energies of 1.1-1.6 eV have been determined. An activation energy dependence on the voltage (Eact* = Eact-f2*V) has been fitted. For the voltage dependence of the lifetime an exponential dependence has been found.
{"title":"Accelerated lifetime measurements on thin film ferroelectric materials with a high dielectric constant","authors":"A. Roest, K. Reimann, M. Klee","doi":"10.1109/ESSDERC.2007.4430963","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430963","url":null,"abstract":"This paper discusses the investigation of thin film ferroelectric capacitors (high-K) with respect to resistance degradation. Accelerated lifetime tests under elevated temperatures of 210-290degC and dc fields of 25-250 kV/cm were performed on these high-K capacitors. The capacitors were studied, making use of the lifetime specifications for ceramic multi-layer capacitors. The increase of the current density by one order of magnitude is here defined as the lifetime of the capacitors. The capacitor under these conditions is still functioning and therefore this is not the lifetime as determined by a breakdown. The accelerated lifetime measurements are used to investigate activation energies and voltage dependences, to enable the extrapolation of the lifetime to operation conditions. It was found that the resistance degradation of these thin film capacitors is a thermally activated process. Activation energies of 1.1-1.6 eV have been determined. An activation energy dependence on the voltage (Eact* = Eact-f2*V) has been fitted. For the voltage dependence of the lifetime an exponential dependence has been found.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128726113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430966
J. Razafmdramora, L. Perniola, C. Jahan, P. Scheiblin, M. Gely, C. Vizioz, C. Carabasse, F. Boulanger, B. De Salvo, S. Deleonibus, S. Lombardo, C. Bongiorno
In this paper, we present a deep investigation of ultra-scaled Finflash memories, fabricated on Silicon on Insulator (SOI) substrate, with Silicon NanoCrystal (Si-NC) or nitride layers acting as storage nodes. Electrical characteristics of devices with channel length (LG) as short as 30 nm, and fin width (WFIN) as narrow as 10 nm are shown. Effective Channel Hot Electron (CHE) writing with sub-3.2 V drain biases (i.e. DeltaVTH=3V at VG/VD/tstress=9V/2.5V/100 mus), as well as Hot Hole Injection (HHI) erasing with sub-4.5V drain biases are demonstrated. Finally, fully three dimensional Monte Carlo simulations, coupled with an original semi-analytical approach, allow us to give a qualitative explanation of the obtained experimental data.
{"title":"Low voltage hot-carrier programming of ultra-scaled SOI finflash memories","authors":"J. Razafmdramora, L. Perniola, C. Jahan, P. Scheiblin, M. Gely, C. Vizioz, C. Carabasse, F. Boulanger, B. De Salvo, S. Deleonibus, S. Lombardo, C. Bongiorno","doi":"10.1109/ESSDERC.2007.4430966","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430966","url":null,"abstract":"In this paper, we present a deep investigation of ultra-scaled Finflash memories, fabricated on Silicon on Insulator (SOI) substrate, with Silicon NanoCrystal (Si-NC) or nitride layers acting as storage nodes. Electrical characteristics of devices with channel length (LG) as short as 30 nm, and fin width (WFIN) as narrow as 10 nm are shown. Effective Channel Hot Electron (CHE) writing with sub-3.2 V drain biases (i.e. DeltaVTH=3V at VG/VD/tstress=9V/2.5V/100 mus), as well as Hot Hole Injection (HHI) erasing with sub-4.5V drain biases are demonstrated. Finally, fully three dimensional Monte Carlo simulations, coupled with an original semi-analytical approach, allow us to give a qualitative explanation of the obtained experimental data.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121077017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430905
D. Tsamados, Y. Chauhan, C. Eggimann, K. Akarvardar, H. Wong, A. Ionescu
This paper proposes, for the first time, the investigation of the SG-FET small slope switch based on a hybrid numerical simulation approach combining ANSYSTM Multiphysics and ISE-DESSISTM in a self-consistent system. The proposed hybrid numerical simulations uniquely enables the investigation of the physics of complex Micro-Electro-Mechanical/solid-state devices, such as SG-FET. Abrupt switching and effect of gate charges are demonstrated. The numerical data serves to calibrate an analytical EKV-based SG-FET model, which is the used to design and originally simulate a sub-micron (90 nm) scaled SG-FET complementary inverter. It is demonstrated that, due to abrupt switch in the subthreshold region and electro-mechanical hysteresis, the SG-FET inverter provides significant power saving (1-2 decades reduction of inverter peak current and practically, no leakage power) compared with traditional CMOS inverter.
{"title":"Numerical and analytical simulations of suspended gate - FET for ultra-low power inverters","authors":"D. Tsamados, Y. Chauhan, C. Eggimann, K. Akarvardar, H. Wong, A. Ionescu","doi":"10.1109/ESSDERC.2007.4430905","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430905","url":null,"abstract":"This paper proposes, for the first time, the investigation of the SG-FET small slope switch based on a hybrid numerical simulation approach combining ANSYSTM Multiphysics and ISE-DESSISTM in a self-consistent system. The proposed hybrid numerical simulations uniquely enables the investigation of the physics of complex Micro-Electro-Mechanical/solid-state devices, such as SG-FET. Abrupt switching and effect of gate charges are demonstrated. The numerical data serves to calibrate an analytical EKV-based SG-FET model, which is the used to design and originally simulate a sub-micron (90 nm) scaled SG-FET complementary inverter. It is demonstrated that, due to abrupt switch in the subthreshold region and electro-mechanical hysteresis, the SG-FET inverter provides significant power saving (1-2 decades reduction of inverter peak current and practically, no leakage power) compared with traditional CMOS inverter.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126269386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430936
E. Toh, G. Wang, L. Chan, G. Lo, D. Sylvester, C. Heng, G. Samudra, Y. Yeo
We report the first demonstration of silicon-germanium (SiGe) impact-ionization MOS (I-MOS) transistors that feature a SiGe channel and a SiGe impact-ionization region. The lower bandgap of SiGe as compared to Si contributes to higher electron and hole impact-ionization rates, leading to avalanche breakdown at a much reduced source voltage and enhanced device performance. Both n-and p-channel I-MOS devices were fabricated on Si0.7sGe0.25-on-insulator substrates using a CMOS-compatible process flow. Compared to Si I-MOS, the breakdown voltage of SiGe I-MOS is reduced by ~1 V along with the doubling of the drive current and transconductance. The subthreshold swing is also improved. Excellent subthreshold swings of 2.88 mV/decade and 3.24 mV/decade are achieved for the n-and p-channel SiGe I-MOS devices, respectively.
{"title":"A complementary-I-MOS technology featuring SiGe channel and i-region for enhancement of impact-ionization, breakdown voltage, and performance","authors":"E. Toh, G. Wang, L. Chan, G. Lo, D. Sylvester, C. Heng, G. Samudra, Y. Yeo","doi":"10.1109/ESSDERC.2007.4430936","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430936","url":null,"abstract":"We report the first demonstration of silicon-germanium (SiGe) impact-ionization MOS (I-MOS) transistors that feature a SiGe channel and a SiGe impact-ionization region. The lower bandgap of SiGe as compared to Si contributes to higher electron and hole impact-ionization rates, leading to avalanche breakdown at a much reduced source voltage and enhanced device performance. Both n-and p-channel I-MOS devices were fabricated on Si0.7sGe0.25-on-insulator substrates using a CMOS-compatible process flow. Compared to Si I-MOS, the breakdown voltage of SiGe I-MOS is reduced by ~1 V along with the doubling of the drive current and transconductance. The subthreshold swing is also improved. Excellent subthreshold swings of 2.88 mV/decade and 3.24 mV/decade are achieved for the n-and p-channel SiGe I-MOS devices, respectively.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128020512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430964
A. Arreghini, N. Akil, F. Driussi, D. Esseni, L. Selmi, M. van Duuren
An improved model to predict the charge retention dynamics of SONOS non volatile memory cells has been developed which accounts for the space and energy dependence of the trapped charge in the silicon nitride self consistently with the potential. From selected long term retention measurements (beyond 106 s) we were able to decouple the charge loss mechanisms and to derive an initial guess of the charge distribution profile. Without further adjustments of the parameters, the model reproduces a large set of long term retention measurements on devices featuring different gate stack, initial threshold voltage and operation temperature.
{"title":"Characterization and modeling of long term retention in SONOS non volatile memories","authors":"A. Arreghini, N. Akil, F. Driussi, D. Esseni, L. Selmi, M. van Duuren","doi":"10.1109/ESSDERC.2007.4430964","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430964","url":null,"abstract":"An improved model to predict the charge retention dynamics of SONOS non volatile memory cells has been developed which accounts for the space and energy dependence of the trapped charge in the silicon nitride self consistently with the potential. From selected long term retention measurements (beyond 106 s) we were able to decouple the charge loss mechanisms and to derive an initial guess of the charge distribution profile. Without further adjustments of the parameters, the model reproduces a large set of long term retention measurements on devices featuring different gate stack, initial threshold voltage and operation temperature.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127339162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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