Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765795
A. Hneine, J. Massol, P. Tounsi, P. Austin
This paper will present one of the first implementations in VHDL-AMS of a compact truly distributed modeling approach applied to the Power PIN diode. This approach is based on the unidimensional solution of the ambipolar diffusion equation describing the charges behavior in the low doped zone within the device. The method allows to transform this equation in space and time into a finite set of differential equations in time only. The adaptation of the compact model to VHDL-AMS language is demonstrated by the implentation into Questa ADMS simulator. To validate the compact model, simulation results will be compared with experimental results. The consistency of the results obtained from the simulation of the diode in a simple chopper circuit shows the efficiency and robustness of the model.
{"title":"Distributed modeling approach applied to the power PIN diode using VHDL-AMS","authors":"A. Hneine, J. Massol, P. Tounsi, P. Austin","doi":"10.1109/ESIME.2011.5765795","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765795","url":null,"abstract":"This paper will present one of the first implementations in VHDL-AMS of a compact truly distributed modeling approach applied to the Power PIN diode. This approach is based on the unidimensional solution of the ambipolar diffusion equation describing the charges behavior in the low doped zone within the device. The method allows to transform this equation in space and time into a finite set of differential equations in time only. The adaptation of the compact model to VHDL-AMS language is demonstrated by the implentation into Questa ADMS simulator. To validate the compact model, simulation results will be compared with experimental results. The consistency of the results obtained from the simulation of the diode in a simple chopper circuit shows the efficiency and robustness of the model.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127637715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765766
S. Chiang, T. Hung, Hsien-Chih Ou, K. Chiang
The Insulated Gate Bipolar Transistor (IGBT) module subjected to a power cycle test will induce a heat concentration zone, rapid change of temperature profile and non-uniform temperature distribution on the IGBT chip. The variation of junction temperature can affect the lifetime of the IGBT module. However, the test module contains several components with different scales and material characteristics. As such, it is difficult to analyze the thermal dissipation and temperature distribution of the IGBT chip under power cycle test conditions using conventional finite element modeling technique. A local/global methodology is proposed in this study, in conduction analysis, it only require to construct a local finite element model in conjunction with a set of specified boundary conditions (SBC) where the temperatures are obtained from the computational fluid dynamics (CFD) results, this hybrid modeling technology can make the analysis process easier and more convenient.
{"title":"Electro-thermal analysis of the Insulated Gate Bipolar Transistor module subjected to power cycling test using specified boundary condition technology","authors":"S. Chiang, T. Hung, Hsien-Chih Ou, K. Chiang","doi":"10.1109/ESIME.2011.5765766","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765766","url":null,"abstract":"The Insulated Gate Bipolar Transistor (IGBT) module subjected to a power cycle test will induce a heat concentration zone, rapid change of temperature profile and non-uniform temperature distribution on the IGBT chip. The variation of junction temperature can affect the lifetime of the IGBT module. However, the test module contains several components with different scales and material characteristics. As such, it is difficult to analyze the thermal dissipation and temperature distribution of the IGBT chip under power cycle test conditions using conventional finite element modeling technique. A local/global methodology is proposed in this study, in conduction analysis, it only require to construct a local finite element model in conjunction with a set of specified boundary conditions (SBC) where the temperatures are obtained from the computational fluid dynamics (CFD) results, this hybrid modeling technology can make the analysis process easier and more convenient.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126763984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765798
M.H.M. Koutersa, G.H.M. Gubbelsa, O. O'Halloranb, R. Rongenb, E.R. Weltevredena
In high power automotive electronics copper wire bonding is regarded as most promising alternative for gold wire bonding in 1st level interconnects and therefore subjected to severe functional requirements. In the Cu-Al ball bond interface the growth of intermetallic compounds may deteriorate the wire bond. The thermo-mechanical properties of these intermetallic compounds are crucial in the prediction of the long term behavior. To determine the mechanical properties diffusion couples were aged and 5 separate intermetallic compounds were melted using the pure elements Cu and Al. These samples were annealed in vacuum at high temperature and chemically analyzed in order to identify the intermetallic compounds. The measured hardness, indentation Young's moduli and densities of these intermetallic compounds are presented. Consequences of the thermo-mechanical properties of the intermetallic compounds are crucial for the prediction of the long term mechanical behavior of Cu-Al ball bonds.
{"title":"Mechanical properties of intermetallics formed during thermal aging of Cu-Al ball bonds","authors":"M.H.M. Koutersa, G.H.M. Gubbelsa, O. O'Halloranb, R. Rongenb, E.R. Weltevredena","doi":"10.1109/ESIME.2011.5765798","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765798","url":null,"abstract":"In high power automotive electronics copper wire bonding is regarded as most promising alternative for gold wire bonding in 1st level interconnects and therefore subjected to severe functional requirements. In the Cu-Al ball bond interface the growth of intermetallic compounds may deteriorate the wire bond. The thermo-mechanical properties of these intermetallic compounds are crucial in the prediction of the long term behavior. To determine the mechanical properties diffusion couples were aged and 5 separate intermetallic compounds were melted using the pure elements Cu and Al. These samples were annealed in vacuum at high temperature and chemically analyzed in order to identify the intermetallic compounds. The measured hardness, indentation Young's moduli and densities of these intermetallic compounds are presented. Consequences of the thermo-mechanical properties of the intermetallic compounds are crucial for the prediction of the long term mechanical behavior of Cu-Al ball bonds.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126928700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765858
D. Farley, A. Dasgupta, Y. Zhou, J. Caers, J. D. de Vries
This study focuses on quasi-static mechanical cycling durability of copper traces on printed wiring assemblies (PWAs). PWA specimens populated with Land Grid Array (LGA) components on copper-defined pads were cycled to failure under zero-to-max, three-point bending. Failure is defined in terms of electrical opens due to fatigue damage propagation through the entire cross-section of the trace. Failure statistics were collected and failure analysis was conducted to identify fatigue failures in the copper traces, near the connection to the solder pad.
{"title":"Fatigue model based on average cross-section strain of Cu trace cyclic bending","authors":"D. Farley, A. Dasgupta, Y. Zhou, J. Caers, J. D. de Vries","doi":"10.1109/ESIME.2011.5765858","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765858","url":null,"abstract":"This study focuses on quasi-static mechanical cycling durability of copper traces on printed wiring assemblies (PWAs). PWA specimens populated with Land Grid Array (LGA) components on copper-defined pads were cycled to failure under zero-to-max, three-point bending. Failure is defined in terms of electrical opens due to fatigue damage propagation through the entire cross-section of the trace. Failure statistics were collected and failure analysis was conducted to identify fatigue failures in the copper traces, near the connection to the solder pad.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115389420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765808
M. Janicki, M. Zubert, A. Napieralski
This paper presents a methodology for the creation of reduced thermal models of electronic systems based on the knowledge of the system dynamic temperature response. The registration of thermal responses using equidistant sampling on a logarithmic time scale allows the proper identification of all the time constants in the responses. Knowing the entire time constant spectrum, it is possible to generate a reduced dynamic thermal model in the form of an RC Cauer ladder with a limited number of stages. This simple model assures not only short simulation time and provides excellent accuracy but also allows the identification of certain physical parameters of a system. The methodology is illustrated in the paper based on the example of discrete power devices attached to a heat sink and cooled with forced air flow. The reduced thermal model is suitable for the direct implementation in the SPICE simulator or almost any other multiphysics simulation environment.
{"title":"Generation of reduced thermal models of electronic systems from transient thermal response","authors":"M. Janicki, M. Zubert, A. Napieralski","doi":"10.1109/ESIME.2011.5765808","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765808","url":null,"abstract":"This paper presents a methodology for the creation of reduced thermal models of electronic systems based on the knowledge of the system dynamic temperature response. The registration of thermal responses using equidistant sampling on a logarithmic time scale allows the proper identification of all the time constants in the responses. Knowing the entire time constant spectrum, it is possible to generate a reduced dynamic thermal model in the form of an RC Cauer ladder with a limited number of stages. This simple model assures not only short simulation time and provides excellent accuracy but also allows the identification of certain physical parameters of a system. The methodology is illustrated in the paper based on the example of discrete power devices attached to a heat sink and cooled with forced air flow. The reduced thermal model is suitable for the direct implementation in the SPICE simulator or almost any other multiphysics simulation environment.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121132010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765807
Sun Fenglian, Liu Yang, Wang Jiabing
Compared with widely used SAC305 (Sn-3.0Ag-0.5Cu) solder, low-Ag (Ag≤1%) SAC solder obviously shows advantages in cost and mechanical impact resistance, and disadvantages in worse wettability, higher melting point and degeneration in electromigration, which restrict its application. Therefore, adding some suitable elements to the solder to improve the solderability and mechanical performance is very important for applications. In this paper, the solderability and electromigration behavior of Low-Ag SAC solder were studied. The effect of adding Bi and Ni elements on the wettability, melting temperature and electromigration properties of SAC0705 (Sn-0.7Ag-0.5Cu) soldering on Cu pad were analysed by SEM and DSC investigations. Results indicate that addition of some Bi and Ni elements into SAC0705 could decrease the peak melting point of the solder, improve the wettability of solder on Cu pad obviously, and decrease the IMC grain size in interface. In addition, adding some Bi and Ni elements could restrict the electromigration behavior under high temperature and high density current stressing. It is found that the thermal condition has much more influence on electromigartion behavior. The IMC polarized distribution and copper consumption aggravate sharply under higher temperature and high density current stressing condition.
{"title":"Improving the solderability and electromigration behavior of Low-Ag SnAgCu soldering","authors":"Sun Fenglian, Liu Yang, Wang Jiabing","doi":"10.1109/ESIME.2011.5765807","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765807","url":null,"abstract":"Compared with widely used SAC305 (Sn-3.0Ag-0.5Cu) solder, low-Ag (Ag≤1%) SAC solder obviously shows advantages in cost and mechanical impact resistance, and disadvantages in worse wettability, higher melting point and degeneration in electromigration, which restrict its application. Therefore, adding some suitable elements to the solder to improve the solderability and mechanical performance is very important for applications. In this paper, the solderability and electromigration behavior of Low-Ag SAC solder were studied. The effect of adding Bi and Ni elements on the wettability, melting temperature and electromigration properties of SAC0705 (Sn-0.7Ag-0.5Cu) soldering on Cu pad were analysed by SEM and DSC investigations. Results indicate that addition of some Bi and Ni elements into SAC0705 could decrease the peak melting point of the solder, improve the wettability of solder on Cu pad obviously, and decrease the IMC grain size in interface. In addition, adding some Bi and Ni elements could restrict the electromigration behavior under high temperature and high density current stressing. It is found that the thermal condition has much more influence on electromigartion behavior. The IMC polarized distribution and copper consumption aggravate sharply under higher temperature and high density current stressing condition.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134317704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765805
R. Qian, Yumin Liu, Y. Liu, Steve Martin, O. Jeon
In this paper, a novel power system module (PSM) is developed by integrating the vertical input capacitor inside the package. Comparing with the traditional PSM, the novel PSM has better electrical performance with less parasitic inductance and switching loss, due to a small loop from the input capacitor to the MOSFETs. A comprehensive modeling study is carried out to assess the assembly stress, thermal performance and reliability performance of the novel PSM. The impact of input capacitor height of the novel PSM is studied by building models with different input capacitor height designs. The modeling of the traditional PSM without the input capacitor is also conducted for comparison. The molding cure process is simulated to study the thermal stress induced by the CTE mismatch of different materials. The non-linear elastic plastic material constitutive model is applied to solder, clip and lead frame. The stress on die, solder paste and solder bump is evaluated and analyzed. Thermal characterization of all the package models is conducted to calculate the thermal resistance Rthja according to the JEDEC standards. The matrix method is used to obtain the thermal resistance of all dies, by applying power on different dies separately. The reliability performance is simulated and compared for all package models, including the autoclave (ACLV) test and preconditioning test. An equivalent CTE method is used to simulate the total stress after the ACLV and reflow process, including the hygroscopic stress, vapor pressure induced stress, and the CTE mismatch induced stress. Finally, the possible failure modes of the novel PSM are discussed.
{"title":"Thermal mechanical modeling and assessment for a novel power system module with vertical input capacitor","authors":"R. Qian, Yumin Liu, Y. Liu, Steve Martin, O. Jeon","doi":"10.1109/ESIME.2011.5765805","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765805","url":null,"abstract":"In this paper, a novel power system module (PSM) is developed by integrating the vertical input capacitor inside the package. Comparing with the traditional PSM, the novel PSM has better electrical performance with less parasitic inductance and switching loss, due to a small loop from the input capacitor to the MOSFETs. A comprehensive modeling study is carried out to assess the assembly stress, thermal performance and reliability performance of the novel PSM. The impact of input capacitor height of the novel PSM is studied by building models with different input capacitor height designs. The modeling of the traditional PSM without the input capacitor is also conducted for comparison. The molding cure process is simulated to study the thermal stress induced by the CTE mismatch of different materials. The non-linear elastic plastic material constitutive model is applied to solder, clip and lead frame. The stress on die, solder paste and solder bump is evaluated and analyzed. Thermal characterization of all the package models is conducted to calculate the thermal resistance Rthja according to the JEDEC standards. The matrix method is used to obtain the thermal resistance of all dies, by applying power on different dies separately. The reliability performance is simulated and compared for all package models, including the autoclave (ACLV) test and preconditioning test. An equivalent CTE method is used to simulate the total stress after the ACLV and reflow process, including the hygroscopic stress, vapor pressure induced stress, and the CTE mismatch induced stress. Finally, the possible failure modes of the novel PSM are discussed.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"4657 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125212082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765864
R. Poelma, H. Sadeghian, S. Koh, G.Q. Zhang
In this paper, the buckling behavior of fixed-fixed, both single- and multi- wall carbon nanotubes (CNTs) under axial compressive loads, are studied using analytical continuum theory and molecular dynamics (MD). An approach based on the tethering of atoms, is used to apply the boundary conditions and extract the reaction forces during the MD simulation. Both the analytical and the MD results agree well for slender CNTs (length=diameter = L/D ≥ 9), that show global buckling. The critical buckling load of non slender CNTs (L/D < 9) is overestimated by the analytical model due to the local buckling. Moreover, the effects of the vacancy defect position on the critical buckling load are studied at room temperature and at low temperature (1 K). It is concluded that the defects at the ends of the CNT and close to the middle of the CNT significantly reduce the critical buckling load and strain of CNTs at 1 K. However, the influence of vacancy defects on the critical buckling load and strain appears to be small at room temperature. The MD results can be used for developing more computationally efficient and accurate continuum descriptions of the CNT mechanics in future work.
{"title":"Buckling analysis of carbon nanotubes and the influence of defect position","authors":"R. Poelma, H. Sadeghian, S. Koh, G.Q. Zhang","doi":"10.1109/ESIME.2011.5765864","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765864","url":null,"abstract":"In this paper, the buckling behavior of fixed-fixed, both single- and multi- wall carbon nanotubes (CNTs) under axial compressive loads, are studied using analytical continuum theory and molecular dynamics (MD). An approach based on the tethering of atoms, is used to apply the boundary conditions and extract the reaction forces during the MD simulation. Both the analytical and the MD results agree well for slender CNTs (length=diameter = L/D ≥ 9), that show global buckling. The critical buckling load of non slender CNTs (L/D < 9) is overestimated by the analytical model due to the local buckling. Moreover, the effects of the vacancy defect position on the critical buckling load are studied at room temperature and at low temperature (1 K). It is concluded that the defects at the ends of the CNT and close to the middle of the CNT significantly reduce the critical buckling load and strain of CNTs at 1 K. However, the influence of vacancy defects on the critical buckling load and strain appears to be small at room temperature. The MD results can be used for developing more computationally efficient and accurate continuum descriptions of the CNT mechanics in future work.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"362 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134114121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765842
Lei Liu, Daoguo Yang, G.Q. Zhang, Zhi You, Fengze Hou, Dongjing Liu
Compared with incandescent lamps and fluorescent lamps, nowadays LEDs (Light Emitting Diodes) are power saving, environment-friendly, and have the advantages of long lifetime and flexible color output. Therefore, LEDs are being widely used in many fields. In this paper, three high-power LEDs packaging modules with different packaging structures were selected to do the performance analysis based on the experiments. In the measurement, the LED junction temperature was controlled at seven levels (25°C, 50°C, 65°C, 75°C, 85°C, 95C, 100°C) in sequence. The thermal variation of some photoelectric parameters for LED packaging modules, such as forward voltage, relative flux output, correlated color temperature (CCT), color rending index (Ra), luminous efficiency and spectrum, were focused on and analyzed here. The experimental results demonstrated that the luminous flux, luminous efficacy and forward voltage of LEDs decreased with the increase of the junction temperature, but these three LEDs packaging modules have different varieties on CRI, CCT and spectrum. The related reasons were analyzed briefly in this paper.
{"title":"Thermal performance analysis of photoelectric parameters on high-power LEDs packaging modules","authors":"Lei Liu, Daoguo Yang, G.Q. Zhang, Zhi You, Fengze Hou, Dongjing Liu","doi":"10.1109/ESIME.2011.5765842","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765842","url":null,"abstract":"Compared with incandescent lamps and fluorescent lamps, nowadays LEDs (Light Emitting Diodes) are power saving, environment-friendly, and have the advantages of long lifetime and flexible color output. Therefore, LEDs are being widely used in many fields. In this paper, three high-power LEDs packaging modules with different packaging structures were selected to do the performance analysis based on the experiments. In the measurement, the LED junction temperature was controlled at seven levels (25°C, 50°C, 65°C, 75°C, 85°C, 95C, 100°C) in sequence. The thermal variation of some photoelectric parameters for LED packaging modules, such as forward voltage, relative flux output, correlated color temperature (CCT), color rending index (Ra), luminous efficiency and spectrum, were focused on and analyzed here. The experimental results demonstrated that the luminous flux, luminous efficacy and forward voltage of LEDs decreased with the increase of the junction temperature, but these three LEDs packaging modules have different varieties on CRI, CCT and spectrum. The related reasons were analyzed briefly in this paper.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134246284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765849
S. Koh, A. Saxena, W. V. van Driel, G.Q. Zhang, R. Tummala
ITRS has predicted that integrated chip (IC) packages will have interconnections with I/O pitch of 90 nm by the year 2018. Lead-based solder materials in flip chip technology will not be able to satisfy the thermal mechanical requirement these fine pitches. Of all the known interconnect technologies, nanostructure interconnects such as nanocrystalline Cu are the most promising technology to meet the high mechanical reliability and electrical requirements of next generation devices. However, there is a need to fully characterize their fatigue properties. In this research, numerical analysis has been employed to study the semi-elliptical crack growth and shape evolution in nanostructured interconnects subject to uniaxial fatigue loading. The results indicate that nanocrystalline copper is in fact a suitable candidate for ultra-fine pitch interconnects applications. This study also predicts that crack growth is a relatively small portion of the total fatigue life of interconnects under LCF conditions. Hence, crack initiation life is the main factor in determining the fatigue life of interconnects.
{"title":"Low cycle fatigue crack growth in nanostructure copper","authors":"S. Koh, A. Saxena, W. V. van Driel, G.Q. Zhang, R. Tummala","doi":"10.1109/ESIME.2011.5765849","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765849","url":null,"abstract":"ITRS has predicted that integrated chip (IC) packages will have interconnections with I/O pitch of 90 nm by the year 2018. Lead-based solder materials in flip chip technology will not be able to satisfy the thermal mechanical requirement these fine pitches. Of all the known interconnect technologies, nanostructure interconnects such as nanocrystalline Cu are the most promising technology to meet the high mechanical reliability and electrical requirements of next generation devices. However, there is a need to fully characterize their fatigue properties. In this research, numerical analysis has been employed to study the semi-elliptical crack growth and shape evolution in nanostructured interconnects subject to uniaxial fatigue loading. The results indicate that nanocrystalline copper is in fact a suitable candidate for ultra-fine pitch interconnects applications. This study also predicts that crack growth is a relatively small portion of the total fatigue life of interconnects under LCF conditions. Hence, crack initiation life is the main factor in determining the fatigue life of interconnects.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124177419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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