Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765847
B. Vandevelde, R. Labie, V. Cherman, T. Webers, C. Winters, E. Beyne, F. Dosseul
Two different flip chip bump configurations have been investigated in terms of their thermo-mechanical, electromigration and fusing behaviour. Standard SAC (SnAgCu) solder bumps with a Ni/Au finish on the chip side are compared with Cu pillar bumps soldered with a thin layer of SnAg alloy. For the test structure, the flip chip assembly is integrated in a BGA package. Finite Element Modelling is used to support the experimental work and explain some of the conclusions.
{"title":"Electromigration, fuse and thermo-mechanical performance of solder bump versus Cu pillar flip chip assemblies","authors":"B. Vandevelde, R. Labie, V. Cherman, T. Webers, C. Winters, E. Beyne, F. Dosseul","doi":"10.1109/ESIME.2011.5765847","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765847","url":null,"abstract":"Two different flip chip bump configurations have been investigated in terms of their thermo-mechanical, electromigration and fusing behaviour. Standard SAC (SnAgCu) solder bumps with a Ni/Au finish on the chip side are compared with Cu pillar bumps soldered with a thin layer of SnAg alloy. For the test structure, the flip chip assembly is integrated in a BGA package. Finite Element Modelling is used to support the experimental work and explain some of the conclusions.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"519 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116702960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765765
L. Siegert, G. Fiannaca, F. Roqueta, G. Gautier, C. Anceau
The aim of this work is to determine a joule heating prediction model for thick copper/Low-k interconnects on glass substrate technology. Experiments and simulations have been used to define thermal conductivities of our stack material from thermal resistance study. In a second time, the thermal resistance is used as quantitative response to predict the joule temperature in the strip. The experimental Rthermic results are well fit with a quadratic model which combined with the thermal coefficient of resistance formalism; allow us to define an analytical temperature joule heating formula. This methodology to define an analytical joule heating formula can be widely used to determine the maximum operating conditions and can be implemented in design rules manuals.
{"title":"Electrothermal prediction model of Cu low k interconnection on glass substrate","authors":"L. Siegert, G. Fiannaca, F. Roqueta, G. Gautier, C. Anceau","doi":"10.1109/ESIME.2011.5765765","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765765","url":null,"abstract":"The aim of this work is to determine a joule heating prediction model for thick copper/Low-k interconnects on glass substrate technology. Experiments and simulations have been used to define thermal conductivities of our stack material from thermal resistance study. In a second time, the thermal resistance is used as quantitative response to predict the joule temperature in the strip. The experimental Rthermic results are well fit with a quadratic model which combined with the thermal coefficient of resistance formalism; allow us to define an analytical temperature joule heating formula. This methodology to define an analytical joule heating formula can be widely used to determine the maximum operating conditions and can be implemented in design rules manuals.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117235001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765820
A. Alimardani, N. Manavizadeh, A. Afzali-Kusha, E. Asl-Soleimani
The loss due to lateral current flow in top diffused layer is one of the most important mechanisms of loss associated with top contacts and can be a limiting factor causing the reduction of cell efficiency especially for cells made to operate at high sun concentrations, because of higher level of current density and voltage drop. To optimize the design of grid contact, it is necessary to know the exact distributions of voltage and lateral and vertical current densities. In this work, a common structure of silicon solar cell is simulated at different levels of sun light concentrations where the lateral current density and voltage distributions are examined for different depths of emitter layer and bias voltages. In addition, the effect of lateral distribution of diffused layer on output power and efficiency for different illuminations is described. Also voltage and lateral current distributions in two bias voltages (maximum power voltage and open circuit voltage) and the influence of illumination are modeled by some analytical functions.
{"title":"Simulation of lateral effect in emitter region of silicon solar cells for concentrated sunlight","authors":"A. Alimardani, N. Manavizadeh, A. Afzali-Kusha, E. Asl-Soleimani","doi":"10.1109/ESIME.2011.5765820","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765820","url":null,"abstract":"The loss due to lateral current flow in top diffused layer is one of the most important mechanisms of loss associated with top contacts and can be a limiting factor causing the reduction of cell efficiency especially for cells made to operate at high sun concentrations, because of higher level of current density and voltage drop. To optimize the design of grid contact, it is necessary to know the exact distributions of voltage and lateral and vertical current densities. In this work, a common structure of silicon solar cell is simulated at different levels of sun light concentrations where the lateral current density and voltage distributions are examined for different depths of emitter layer and bias voltages. In addition, the effect of lateral distribution of diffused layer on output power and efficiency for different illuminations is described. Also voltage and lateral current distributions in two bias voltages (maximum power voltage and open circuit voltage) and the influence of illumination are modeled by some analytical functions.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131010502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765804
R. Qian, Y. Liu, Jihwan Kim, S. Martin
In this paper, a comprehensive modeling is carried out to investigate the dynamic behaviors of WL-CSP subjected to both flat and vertical drop impacts. The non-linear dynamic properties include solder, Cu pad and the metal stacking under the UBM. Both of the JEDEC standard flat drop test and the vertical drop test modeling for different solder bump height are studied. The results showed that, in the JEDEC standard flat drop test, Stress of the corner balls at each WL-CSP is much higher than the balls in other locations on the same components. The results showed the vertical drop stress is lower than the flat drop stress. The result of JEDEC standard flat drop test modeling showed that the higher solder joint of the WL-CSP can result in lower plastic impact energy but higher tensile (first principal) stress S1 at solder joint.
{"title":"Board level flat and vertical drop impact reliability for wafer level chip scale package","authors":"R. Qian, Y. Liu, Jihwan Kim, S. Martin","doi":"10.1109/ESIME.2011.5765804","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765804","url":null,"abstract":"In this paper, a comprehensive modeling is carried out to investigate the dynamic behaviors of WL-CSP subjected to both flat and vertical drop impacts. The non-linear dynamic properties include solder, Cu pad and the metal stacking under the UBM. Both of the JEDEC standard flat drop test and the vertical drop test modeling for different solder bump height are studied. The results showed that, in the JEDEC standard flat drop test, Stress of the corner balls at each WL-CSP is much higher than the balls in other locations on the same components. The results showed the vertical drop stress is lower than the flat drop stress. The result of JEDEC standard flat drop test modeling showed that the higher solder joint of the WL-CSP can result in lower plastic impact energy but higher tensile (first principal) stress S1 at solder joint.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131025723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765812
M. Deluca, R. Bermejo, M. Pletz, M. Morianz, J. Stahr, P. Supancic, R. Danzer
The ongoing trend to further miniaturise electronic devices in Printed Circuit Board (PCB) technologies has pointed out the embedding of components as a principal design strategy. The reliability of the PCB relies on the functionality of the embedded components as well as on their structural integrity in order to survive the embedding process. In the present work, the biaxial strength of metallised silicon chips used in PCB technologies has been tested on both the substrate and the metallised side, evidencing a significant influence of the metallic contacts on the strength and the mechanical reliability of the component. Specimens tested with the metallised side under tension underwent an early failure (lower fracture load), whereby a statistical analysis of the strength distribution evidenced the presence of a narrower critical defect size distribution (i.e. higher mechanical reliability). This phenomenon was explained by means of (i) finite elements (FE) simulations of the loading conditions, and (ii) Focussed Ion Beam (FIB) analyses of the metal-silicon interface. It was concluded that the presence of a stress concentration in the interfacial area during loading induces pre-cracks which can act as critical defects upon load enhancement, thus causing failure for a very well defined range of loads.
{"title":"Local strength measurement technique for miniaturised silicon-based components","authors":"M. Deluca, R. Bermejo, M. Pletz, M. Morianz, J. Stahr, P. Supancic, R. Danzer","doi":"10.1109/ESIME.2011.5765812","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765812","url":null,"abstract":"The ongoing trend to further miniaturise electronic devices in Printed Circuit Board (PCB) technologies has pointed out the embedding of components as a principal design strategy. The reliability of the PCB relies on the functionality of the embedded components as well as on their structural integrity in order to survive the embedding process. In the present work, the biaxial strength of metallised silicon chips used in PCB technologies has been tested on both the substrate and the metallised side, evidencing a significant influence of the metallic contacts on the strength and the mechanical reliability of the component. Specimens tested with the metallised side under tension underwent an early failure (lower fracture load), whereby a statistical analysis of the strength distribution evidenced the presence of a narrower critical defect size distribution (i.e. higher mechanical reliability). This phenomenon was explained by means of (i) finite elements (FE) simulations of the loading conditions, and (ii) Focussed Ion Beam (FIB) analyses of the metal-silicon interface. It was concluded that the presence of a stress concentration in the interfacial area during loading induces pre-cracks which can act as critical defects upon load enhancement, thus causing failure for a very well defined range of loads.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131620132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765811
H. Karamitaheri, M. Pourfath, R. Faez, H. Kosina
In this work, we present a theoretical investigation of the thermal conductivity of hydrogen-passivated graphene antidot lattices. Using a fourth nearest-neighbor force constant method, we evaluate the phonon dispersion of hydrogen-passivated graphene antidot lattices with circular, hexagonal, rectangular and triangular shapes. Ballistic transport models are used to evaluate the thermal conductivity. The calculations indicate that the thermal conductivity of hydrogen-passivated graphene antidot lattices can be one fourth of that of a pristine graphene sheet. This reduction is stronger for right-triangular and iso-triangular antidots among others, all with the same area, due to longer boundaries and the smallest distance between the neighboring dots.
{"title":"Hydrogen-passivated graphene antidot structures for thermoelectric applications","authors":"H. Karamitaheri, M. Pourfath, R. Faez, H. Kosina","doi":"10.1109/ESIME.2011.5765811","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765811","url":null,"abstract":"In this work, we present a theoretical investigation of the thermal conductivity of hydrogen-passivated graphene antidot lattices. Using a fourth nearest-neighbor force constant method, we evaluate the phonon dispersion of hydrogen-passivated graphene antidot lattices with circular, hexagonal, rectangular and triangular shapes. Ballistic transport models are used to evaluate the thermal conductivity. The calculations indicate that the thermal conductivity of hydrogen-passivated graphene antidot lattices can be one fourth of that of a pristine graphene sheet. This reduction is stronger for right-triangular and iso-triangular antidots among others, all with the same area, due to longer boundaries and the smallest distance between the neighboring dots.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"154 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133005653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765829
E. Marcault, M. Breil, A. Bourennane, P. Tounsi, P. Dupuy
Based on 2D mechanical and physical simulations, we explore the impact of solder joint ageing at the origin of power assembly failures, on the electrical characteristics of multi IGBT cells. Electrical characteristics variations are analyzed with the aim of using them for health monitoring of embedded power assemblies.
{"title":"Impact of the solder joint ageing on IGBT I–V characteristics using 2D physical simulations","authors":"E. Marcault, M. Breil, A. Bourennane, P. Tounsi, P. Dupuy","doi":"10.1109/ESIME.2011.5765829","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765829","url":null,"abstract":"Based on 2D mechanical and physical simulations, we explore the impact of solder joint ageing at the origin of power assembly failures, on the electrical characteristics of multi IGBT cells. Electrical characteristics variations are analyzed with the aim of using them for health monitoring of embedded power assemblies.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133925271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765844
Fengze Hou, Daoguo Yang, G.Q. Zhang, Yang Hai, Dongjing Liu, Lei Liu
In this paper, a 3 W high power LED array system with an in-line pin fin heat sink is designed, fabricated, and investigated for thermal transient analysis. Preliminary finite element simulation is conducted by ANSYS, and LED array average junction temperature is about 40.9°C. In the experiment, electrical test method is used to evaluate the heat dissipation effect of the LED array system. Experiment results show that the system works well. The cumulative thermal resistance of the system is about 6.7K/W, and corresponding LED array average junction temperature is about 40.5°C. It is found that the simulation result is consistent with the experimental result. The error is about 1%. It is also found that, in order to get accurate thermal resistance of every kind of material in the heat flow path, we should analyze the curves of cumulative and differential structure function simultaneously.
{"title":"Thermal transient analysis of LED array system with in-line pin fin heat sink","authors":"Fengze Hou, Daoguo Yang, G.Q. Zhang, Yang Hai, Dongjing Liu, Lei Liu","doi":"10.1109/ESIME.2011.5765844","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765844","url":null,"abstract":"In this paper, a 3 W high power LED array system with an in-line pin fin heat sink is designed, fabricated, and investigated for thermal transient analysis. Preliminary finite element simulation is conducted by ANSYS, and LED array average junction temperature is about 40.9°C. In the experiment, electrical test method is used to evaluate the heat dissipation effect of the LED array system. Experiment results show that the system works well. The cumulative thermal resistance of the system is about 6.7K/W, and corresponding LED array average junction temperature is about 40.5°C. It is found that the simulation result is consistent with the experimental result. The error is about 1%. It is also found that, in order to get accurate thermal resistance of every kind of material in the heat flow path, we should analyze the curves of cumulative and differential structure function simultaneously.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121077025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765853
T. Falat, B. Platek, J. Felba
Currently there is a lot of ongoing research towards estimation the thermal conductivity of carbon nanotubes (CNT). In the current paper thermal conductivity of SWNT were studied by using non-equilibrium molecular dynamics (NEMD) simulations (implemented in Materials Studio software, Accelerys Inc.). The NEMD technique is a direct approach which includes the computation of heat transport coefficients from flux-force relations, analogous to the macroscopic definition in irreversible thermodynamics. Simulations in nano- and atomic-scale can cause problems with model validation and with algorithm verification. The novel approach based on simulation of known material such as silicon were applied. The current paper focuses on the obtained results of model validation and verification of simulation algorithm.
{"title":"Non-equilibrium molecular dynamics simulation of heat transfer in carbon nanotubes - verification and model validation","authors":"T. Falat, B. Platek, J. Felba","doi":"10.1109/ESIME.2011.5765853","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765853","url":null,"abstract":"Currently there is a lot of ongoing research towards estimation the thermal conductivity of carbon nanotubes (CNT). In the current paper thermal conductivity of SWNT were studied by using non-equilibrium molecular dynamics (NEMD) simulations (implemented in Materials Studio software, Accelerys Inc.). The NEMD technique is a direct approach which includes the computation of heat transport coefficients from flux-force relations, analogous to the macroscopic definition in irreversible thermodynamics. Simulations in nano- and atomic-scale can cause problems with model validation and with algorithm verification. The novel approach based on simulation of known material such as silicon were applied. The current paper focuses on the obtained results of model validation and verification of simulation algorithm.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115680727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765780
E. Almagro, B. B. Hornales, Marvin R. Gestole
This paper presents the results of a numerical analysis on the electrical interconnect options of a Power QFN (PQFN) package, to explore and compare the RDS(ON) performance at DC condition. The modeling involves the PQFN 5mm × 6mm package which initially uses Aluminum wire bonds for interconnection. Competition in the market in terms of better electrical performance packages challenge semiconductor companies to venture into new technology, innovation, process, wafer fabrication, package design changes. For the PQFN, apart from having a thin die with low specific RDS(ON), it is necessary to choose an interconnect which is also electrically efficient. Among the choices aside from the traditional Aluminum round wires are Aluminum ribbon bonding and Cu clip bonding. The comparison is purely based on the electrical performance and the study does not include the cost factors and other material related effects such as stress performance, etc. A commercial FEA code, ANSYS®, is utilized in this study while Solidworks® is used for CAD.
{"title":"FEA study on electrical interconnects for a power QFN package","authors":"E. Almagro, B. B. Hornales, Marvin R. Gestole","doi":"10.1109/ESIME.2011.5765780","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765780","url":null,"abstract":"This paper presents the results of a numerical analysis on the electrical interconnect options of a Power QFN (PQFN) package, to explore and compare the RDS(ON) performance at DC condition. The modeling involves the PQFN 5mm × 6mm package which initially uses Aluminum wire bonds for interconnection. Competition in the market in terms of better electrical performance packages challenge semiconductor companies to venture into new technology, innovation, process, wafer fabrication, package design changes. For the PQFN, apart from having a thin die with low specific RDS(ON), it is necessary to choose an interconnect which is also electrically efficient. Among the choices aside from the traditional Aluminum round wires are Aluminum ribbon bonding and Cu clip bonding. The comparison is purely based on the electrical performance and the study does not include the cost factors and other material related effects such as stress performance, etc. A commercial FEA code, ANSYS®, is utilized in this study while Solidworks® is used for CAD.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114775356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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