Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765760
K. Nakahira, Hironori Tago, H. Kishi, Ken Suzuki, H. Miura, M. Yoshimaru, K. Tatsuuma
The embedded strain gauges in a PQC-TEG were applied to the measurement of the change of the residual stress in a transistor structure with a 50-nm wide gate during thin film processing. The change of the residual stress was successfully monitored through the process such as the deposition and etching of thin films. In addition, the fluctuation of the process such as the intrinsic stress of thin films and the height and the width of the etched structures was also detected by the statistical analysis of the measured data. The sensitivity of the measurement was 1 MPa and it was validated that the amplitude of the fluctuation exceeded 100 MPa. This technique is also effective for detecting the spatial distribution of the stress in a wafer and its fluctuation among wafers.
{"title":"Evaluation of the change of the residual stress in nano-scale transistors during the deposition and fine patterning processes of thin films","authors":"K. Nakahira, Hironori Tago, H. Kishi, Ken Suzuki, H. Miura, M. Yoshimaru, K. Tatsuuma","doi":"10.1109/ESIME.2011.5765760","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765760","url":null,"abstract":"The embedded strain gauges in a PQC-TEG were applied to the measurement of the change of the residual stress in a transistor structure with a 50-nm wide gate during thin film processing. The change of the residual stress was successfully monitored through the process such as the deposition and etching of thin films. In addition, the fluctuation of the process such as the intrinsic stress of thin films and the height and the width of the etched structures was also detected by the statistical analysis of the measured data. The sensitivity of the measurement was 1 MPa and it was validated that the amplitude of the fluctuation exceeded 100 MPa. This technique is also effective for detecting the spatial distribution of the stress in a wafer and its fluctuation among wafers.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126793222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765834
K. Sinha, D. Farley, T. Kahnert, A. Dasgupta, J. Caers, X.J. Zhao
In the conversion towards Pb-free electronics, there has been increasing interest in conductive adhesive interconnects, as they combine Pb-free materials with an attractive, low temperature, processing. One such promising packaging concept is direct bonding of flip-chip dies onto printed wiring boards (PWBs), with adhesive bonds between a gold-bumped flip-chip IC and matching gold-plated copper pads on a substrate. The goal is to achieve very high I/O densities per unit area, that are currently difficult to achieve, but are critical enablers for next-generation flexible electronic system. The fabrication process relies on adhesive joining methods and requires the simultaneous application of adhesive, pressure, temperature, and time to form the interconnection. The reliability of this interconnection under cyclic thermal excursions is traditionally believed to be governed by stress relaxation mechanisms in the adhesive. However, experiments conducted in this study suggest that under typical bonding conditions, a metallurgical bond can be established between these mating gold surfaces, due to cold-welding. If true, this implies a significantly different reliability mechanism for this interconnection method, and this mechanism must be understood so we can harness it for optimum reliability. The aim of this research work is to improve the effectiveness of interconnection processes for Au bumped flip-chip ICs. If successful, this study will enable significant cost-effective improvements in the reliability of wafer-level IC packaging technologies.
{"title":"Au-Au ‘cold-weld’ bond strength in adhesively bonded flip-chip interconnects","authors":"K. Sinha, D. Farley, T. Kahnert, A. Dasgupta, J. Caers, X.J. Zhao","doi":"10.1109/ESIME.2011.5765834","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765834","url":null,"abstract":"In the conversion towards Pb-free electronics, there has been increasing interest in conductive adhesive interconnects, as they combine Pb-free materials with an attractive, low temperature, processing. One such promising packaging concept is direct bonding of flip-chip dies onto printed wiring boards (PWBs), with adhesive bonds between a gold-bumped flip-chip IC and matching gold-plated copper pads on a substrate. The goal is to achieve very high I/O densities per unit area, that are currently difficult to achieve, but are critical enablers for next-generation flexible electronic system. The fabrication process relies on adhesive joining methods and requires the simultaneous application of adhesive, pressure, temperature, and time to form the interconnection. The reliability of this interconnection under cyclic thermal excursions is traditionally believed to be governed by stress relaxation mechanisms in the adhesive. However, experiments conducted in this study suggest that under typical bonding conditions, a metallurgical bond can be established between these mating gold surfaces, due to cold-welding. If true, this implies a significantly different reliability mechanism for this interconnection method, and this mechanism must be understood so we can harness it for optimum reliability. The aim of this research work is to improve the effectiveness of interconnection processes for Au bumped flip-chip ICs. If successful, this study will enable significant cost-effective improvements in the reliability of wafer-level IC packaging technologies.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"358 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126692430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765822
Mario Gonzalez, J. Govaerts, R. Labie, I. De Wolf, K. Baert
This paper firstly summarizes the process flow developed at IMEC to integrate and interconnect thin back-contact solar cells into modules. Secondly, the process flow is simulated by Finite Element Modelling to determine critical process steps that may lead to early failures. A virtual Design of Experiment (DOE) is used to determine the best geometry and materials properties in order to minimise the induced stresses in the cells and the interconnections. The variables of this DOE are the silicon, the glue and the encapsulant thickness and the Elastic Modulus of the glue and encapsulant. The results of this DOE are presented in forms of Response Surface Models and it is observed that Young's Modulus of encapsulant and the thickness of the solar cells are the mayor contributors to the stresses in the silicon cells. Furthermore, an analysis of the changes in distance between adjacent cells at different temperatures indicates that the stiffness of the encapsulant material will play an important role on the mechanical behavior of the metallic solar cells interconnections.
{"title":"Thermo-mechanical challenges of advanced solar cell modules","authors":"Mario Gonzalez, J. Govaerts, R. Labie, I. De Wolf, K. Baert","doi":"10.1109/ESIME.2011.5765822","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765822","url":null,"abstract":"This paper firstly summarizes the process flow developed at IMEC to integrate and interconnect thin back-contact solar cells into modules. Secondly, the process flow is simulated by Finite Element Modelling to determine critical process steps that may lead to early failures. A virtual Design of Experiment (DOE) is used to determine the best geometry and materials properties in order to minimise the induced stresses in the cells and the interconnections. The variables of this DOE are the silicon, the glue and the encapsulant thickness and the Elastic Modulus of the glue and encapsulant. The results of this DOE are presented in forms of Response Surface Models and it is observed that Young's Modulus of encapsulant and the thickness of the solar cells are the mayor contributors to the stresses in the silicon cells. Furthermore, an analysis of the changes in distance between adjacent cells at different temperatures indicates that the stiffness of the encapsulant material will play an important role on the mechanical behavior of the metallic solar cells interconnections.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127942268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765817
N. Manavizadeh, M. Pourfath, F. Raissi, E. Asl-Soleimani
The performance of nanoscale Field Effect Diode as a function of the doping concentration and the gate voltage is investigated. Our numerical results show that the Ion/Ioff ratio which is a significant parameter in digital application can be varied from 101 to 104 as the doping concentration of source/drain regions increased from 1016 to 1021cm−3. The figures of merit including intrinsic gate delay time and energy-delay product have been studied for the field effect diodes which are interesting candidates for future logic application.
{"title":"A comprehensive study of nanoscale Field Effect Diodes","authors":"N. Manavizadeh, M. Pourfath, F. Raissi, E. Asl-Soleimani","doi":"10.1109/ESIME.2011.5765817","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765817","url":null,"abstract":"The performance of nanoscale Field Effect Diode as a function of the doping concentration and the gate voltage is investigated. Our numerical results show that the I<inf>on</inf>/I<inf>off</inf> ratio which is a significant parameter in digital application can be varied from 10<sup>1</sup> to 10<sup>4</sup> as the doping concentration of source/drain regions increased from 10<sup>16</sup> to 10<sup>21</sup>cm<sup>−3</sup>. The figures of merit including intrinsic gate delay time and energy-delay product have been studied for the field effect diodes which are interesting candidates for future logic application.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133100742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765825
A. Alsakarneh, L. Moore, J. Barrett
Presented here is the use and optimization of mutli-layer viscoelastic buffer materials to protect embedded electronic systems from high mechanical forces such as impacts. The test vehicle was a solid sports ball, Figure 1. The embedded system was first encapsulated using standard epoxy encapsulant, then further encapsulated with two different buffer materials (a soft and a hard rubber) before the entire system was embedded in the ball. The ball (from the Irish game of hurling) has an original polyurethane/cork core encased in a leather outer skin and is 70 mm. in diameter and weighs 110g. The multi-layer buffering system reduces the imposed stress on the epoxy-encapsulated embedded system, so that the stress transmitted to the electronics is significantly reduced. From this point of view, the stress experienced at the embedded system edge was taken as the objective function to be minimized within the overall constraint that the modified ball must closely retain its original size, weight and “bounce” i.e. its Coefficient of Restitution (CoR). This is a specific example of the more general embedded systems problem of embedding, say, a system such as a wireless sensor node in a material or structure without significantly changing the material or structure mechanical properties and reliability. A numerical model, using ANSYS 11.0, was developed and used in a simulation-based designed experiment of eight runs. The element SOLID92 was used to model the plastic and electronic structures. The optimized multilayered structure reduced the stress on the embedded system by 50% in comparison to the original un-buffered structure and reduced stress by 25% in comparison to the non-optimized buffer system. The optimized structure was within 90% of the original one for weight and 85 % for CoR. This work has defined a design methodology for buffer layers that significantly increase the protection of embedded electronic systems from high mechanical forces without major impact on the host object mechanical properties. The methodology is particularly applicable to the mechanical design of smart objects and structures.
{"title":"Numerical modelling and optimization of an electronic system embedded in multi-layered viscoelastic materials under shock loads","authors":"A. Alsakarneh, L. Moore, J. Barrett","doi":"10.1109/ESIME.2011.5765825","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765825","url":null,"abstract":"Presented here is the use and optimization of mutli-layer viscoelastic buffer materials to protect embedded electronic systems from high mechanical forces such as impacts. The test vehicle was a solid sports ball, Figure 1. The embedded system was first encapsulated using standard epoxy encapsulant, then further encapsulated with two different buffer materials (a soft and a hard rubber) before the entire system was embedded in the ball. The ball (from the Irish game of hurling) has an original polyurethane/cork core encased in a leather outer skin and is 70 mm. in diameter and weighs 110g. The multi-layer buffering system reduces the imposed stress on the epoxy-encapsulated embedded system, so that the stress transmitted to the electronics is significantly reduced. From this point of view, the stress experienced at the embedded system edge was taken as the objective function to be minimized within the overall constraint that the modified ball must closely retain its original size, weight and “bounce” i.e. its Coefficient of Restitution (CoR). This is a specific example of the more general embedded systems problem of embedding, say, a system such as a wireless sensor node in a material or structure without significantly changing the material or structure mechanical properties and reliability. A numerical model, using ANSYS 11.0, was developed and used in a simulation-based designed experiment of eight runs. The element SOLID92 was used to model the plastic and electronic structures. The optimized multilayered structure reduced the stress on the embedded system by 50% in comparison to the original un-buffered structure and reduced stress by 25% in comparison to the non-optimized buffer system. The optimized structure was within 90% of the original one for weight and 85 % for CoR. This work has defined a design methodology for buffer layers that significantly increase the protection of embedded electronic systems from high mechanical forces without major impact on the host object mechanical properties. The methodology is particularly applicable to the mechanical design of smart objects and structures.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133565450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765863
M. Mayer
The risk of chip damage due to ultrasonic stresses in ball bonding needs to be managed while assuring a high bond strength. Chips with low-k dielectrics are less robust than those with SiO2, and if novel Cu or Pd coated Cu bonding wire is used, larger stresses are common during bonding. A finite element model can predict stresses at all locations under the pad including those due to the dynamics of the bonding tool. An experimental verification of these tool dynamics has not been done and is suggested using integrated piezo-resistive stress microsensors on a custom made testchip. The suitability of such a stress sensor design is discussed.
{"title":"Ultrasonic stresses in thermosonic ball bonding","authors":"M. Mayer","doi":"10.1109/ESIME.2011.5765863","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765863","url":null,"abstract":"The risk of chip damage due to ultrasonic stresses in ball bonding needs to be managed while assuring a high bond strength. Chips with low-k dielectrics are less robust than those with SiO2, and if novel Cu or Pd coated Cu bonding wire is used, larger stresses are common during bonding. A finite element model can predict stresses at all locations under the pad including those due to the dynamics of the bonding tool. An experimental verification of these tool dynamics has not been done and is suggested using integrated piezo-resistive stress microsensors on a custom made testchip. The suitability of such a stress sensor design is discussed.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131885832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765815
T. Hauck
The author studied the behavior of power packages exposed to repeatedly high current loads. Self-heating of the power transistors can cause a tremendous temperature rise in the vicinity of the active device. The resulting temperature gradient and the thermal mismatch of materials induce mechanical strains and stresses in the power package. The stress level can in some cases exceed the yield limit of the metallization layer on the die. Repetitive current peaks will then cause a fatigue phenomenon that can cause a device failure.
{"title":"Cyclic loading and fatigue in power packages","authors":"T. Hauck","doi":"10.1109/ESIME.2011.5765815","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765815","url":null,"abstract":"The author studied the behavior of power packages exposed to repeatedly high current loads. Self-heating of the power transistors can cause a tremendous temperature rise in the vicinity of the active device. The resulting temperature gradient and the thermal mismatch of materials induce mechanical strains and stresses in the power package. The stress level can in some cases exceed the yield limit of the metallization layer on the die. Repetitive current peaks will then cause a fatigue phenomenon that can cause a device failure.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129646141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765791
B. Curran, I. Ndip, J. Bauer, S. Guttowski, K. Lang, H. Reichl
Organic dielectric materials will absorb moisture when in direct contact with a liquid or a humid environment. The dielectric then becomes a two-phase dielectric composite with new dielectric characteristics. Using the Lichtenecker Equation, the composite dielectric permittivity and loss characteristics are modeled. The loss modeling includes the polymer dielectric loss characteristics, as well as the conductive loss of the moisture. The model is also used to predict the frequency dispersion of the relative permittivity at lower frequencies caused by the conductivity of the moisture. The modeling is validated using high frequency measurements of interdigital capacitors, which correspond to the modeling within 5% across the entire examined frequency range.
{"title":"The impact of moisture absorption on the electrical characteristics of organic dielectric materials","authors":"B. Curran, I. Ndip, J. Bauer, S. Guttowski, K. Lang, H. Reichl","doi":"10.1109/ESIME.2011.5765791","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765791","url":null,"abstract":"Organic dielectric materials will absorb moisture when in direct contact with a liquid or a humid environment. The dielectric then becomes a two-phase dielectric composite with new dielectric characteristics. Using the Lichtenecker Equation, the composite dielectric permittivity and loss characteristics are modeled. The loss modeling includes the polymer dielectric loss characteristics, as well as the conductive loss of the moisture. The model is also used to predict the frequency dispersion of the relative permittivity at lower frequencies caused by the conductivity of the moisture. The modeling is validated using high frequency measurements of interdigital capacitors, which correspond to the modeling within 5% across the entire examined frequency range.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123720642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765800
J. Lo, Rong Zhang, S. W. Ricky, Zelin Wang, Hong Kong
In the fabrication of system-in-package (SiP) devices, wafer bonding is a common yet very important process. The technologies widely used nowadays for wafer bonding include direct wafer bonding and intermediate layer bonding. Fusion bonding, one of the direct wafer bonding techniques, requires a processing temperature up to 800–1000°C to create strong covalent bonds between wafers. Some devices, however, cannot withstand such high temperature. Also, the stress generated due to different coefficients of thermal expansion is directly associated with the bonding temperature. Therefore, a low temperature wafer bonding technique is in demand. In this study, an innovative adhesive bonding method is proposed. Patterned trenches are fabricated on one side of the wafer and completely filled with silicone adhesive. The proposed wafer bonding method has several advantages over the traditional adhesive boning method. The trenches provide air escape paths. It also enchances the adhesion strength of the bonded wafers. Test vehicles are fabricated to demonstrate the proposed wafer bonding method with trenches. Shear tests are conducted to measure the mechanical performance of the proposed method. Results show that, when the sample is sheared perpendicularly to the trenches, the shear strength of the sample is 25% higher than that of the sample without trenches.
{"title":"Evaluation of polymer wafer bonding with silicone adhesive and patterned trenches","authors":"J. Lo, Rong Zhang, S. W. Ricky, Zelin Wang, Hong Kong","doi":"10.1109/ESIME.2011.5765800","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765800","url":null,"abstract":"In the fabrication of system-in-package (SiP) devices, wafer bonding is a common yet very important process. The technologies widely used nowadays for wafer bonding include direct wafer bonding and intermediate layer bonding. Fusion bonding, one of the direct wafer bonding techniques, requires a processing temperature up to 800–1000°C to create strong covalent bonds between wafers. Some devices, however, cannot withstand such high temperature. Also, the stress generated due to different coefficients of thermal expansion is directly associated with the bonding temperature. Therefore, a low temperature wafer bonding technique is in demand. In this study, an innovative adhesive bonding method is proposed. Patterned trenches are fabricated on one side of the wafer and completely filled with silicone adhesive. The proposed wafer bonding method has several advantages over the traditional adhesive boning method. The trenches provide air escape paths. It also enchances the adhesion strength of the bonded wafers. Test vehicles are fabricated to demonstrate the proposed wafer bonding method with trenches. Shear tests are conducted to measure the mechanical performance of the proposed method. Results show that, when the sample is sheared perpendicularly to the trenches, the shear strength of the sample is 25% higher than that of the sample without trenches.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"54 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130313192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765852
S. Y. Y. Leung, M. Sadeghinia, H. Pape, L. Ernst
Delamination between copper and epoxy molding compound (EMC) is one of the common failure modes in packages due to relatively weak adhesion at the interface. Delamination is difficult to predict because a package is often with a complex structure design constructed with different materials and under combined normal and shear loading. Development of cohesive zone elements applied in FEM has emerged into the application of cohesive zones as an effective tool for crack propagation simulation. In this study, a methodology to obtain useful parameters for cohesive zone modeling from experimental measurements is proposed. The approach is demonstrated with the adhesive joint between epoxy molding compound and copper that was under residual stresses and applied mixed-mode loading. The proposed approach to determine the traction-separation function does not rely on the uncertainties of crack tip stresses. The predicted load-displacement result is matched with experimental measurement results at the crack propagation region. Package delamination can be predicted by implementing the proposed testing and modeling scheme within the cohesive zone model.
{"title":"Prediction of mixed-mode interfacial fracture from cohesive zone finite element model: Testing and determination of fracture process parameters","authors":"S. Y. Y. Leung, M. Sadeghinia, H. Pape, L. Ernst","doi":"10.1109/ESIME.2011.5765852","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765852","url":null,"abstract":"Delamination between copper and epoxy molding compound (EMC) is one of the common failure modes in packages due to relatively weak adhesion at the interface. Delamination is difficult to predict because a package is often with a complex structure design constructed with different materials and under combined normal and shear loading. Development of cohesive zone elements applied in FEM has emerged into the application of cohesive zones as an effective tool for crack propagation simulation. In this study, a methodology to obtain useful parameters for cohesive zone modeling from experimental measurements is proposed. The approach is demonstrated with the adhesive joint between epoxy molding compound and copper that was under residual stresses and applied mixed-mode loading. The proposed approach to determine the traction-separation function does not rely on the uncertainties of crack tip stresses. The predicted load-displacement result is matched with experimental measurement results at the crack propagation region. Package delamination can be predicted by implementing the proposed testing and modeling scheme within the cohesive zone model.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116937569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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