Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765760
K. Nakahira, Hironori Tago, H. Kishi, Ken Suzuki, H. Miura, M. Yoshimaru, K. Tatsuuma
The embedded strain gauges in a PQC-TEG were applied to the measurement of the change of the residual stress in a transistor structure with a 50-nm wide gate during thin film processing. The change of the residual stress was successfully monitored through the process such as the deposition and etching of thin films. In addition, the fluctuation of the process such as the intrinsic stress of thin films and the height and the width of the etched structures was also detected by the statistical analysis of the measured data. The sensitivity of the measurement was 1 MPa and it was validated that the amplitude of the fluctuation exceeded 100 MPa. This technique is also effective for detecting the spatial distribution of the stress in a wafer and its fluctuation among wafers.
{"title":"Evaluation of the change of the residual stress in nano-scale transistors during the deposition and fine patterning processes of thin films","authors":"K. Nakahira, Hironori Tago, H. Kishi, Ken Suzuki, H. Miura, M. Yoshimaru, K. Tatsuuma","doi":"10.1109/ESIME.2011.5765760","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765760","url":null,"abstract":"The embedded strain gauges in a PQC-TEG were applied to the measurement of the change of the residual stress in a transistor structure with a 50-nm wide gate during thin film processing. The change of the residual stress was successfully monitored through the process such as the deposition and etching of thin films. In addition, the fluctuation of the process such as the intrinsic stress of thin films and the height and the width of the etched structures was also detected by the statistical analysis of the measured data. The sensitivity of the measurement was 1 MPa and it was validated that the amplitude of the fluctuation exceeded 100 MPa. This technique is also effective for detecting the spatial distribution of the stress in a wafer and its fluctuation among wafers.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126793222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765799
Y. Liu, D. Kinzer
Power electronic packaging is one of the fastest changing areas of technology in the power electronic industry due to the rapid advances in power integrated circuit (IC) fabrication and the demands of a growing market in almost all areas of power electronic application such as portable electronics, consumer electronics, home electronics, computing electronics, automotive, railway and high/strong power industry. However, due to the intrinsic high power dissipation, the performance requirement for power products are extremely high, especially in handling harsh thermal and electrical environments. The design rules and material and structure layout of power packaging are quite different from regular IC packaging. This talk will present a state-of-art and in-depth overview of recent advances, challenges and opportunities in power electronic packaging design and modeling. A review of recent advances in power electronic packaging is presented based on the development of power device integration. The talk will cover in more detail how challenges in both semiconductor content and advanced power package design and materials have co-enabled significant advances in power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Along with new power packaging development, modeling is a key to assure successful package design. An overview of the power package modeling is presented. Challenges of power semiconductor packaging and modeling in both next generation design and assembly processes are presented and discussed.
{"title":"Challenges of power electronic packaging and modeling","authors":"Y. Liu, D. Kinzer","doi":"10.1109/ESIME.2011.5765799","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765799","url":null,"abstract":"Power electronic packaging is one of the fastest changing areas of technology in the power electronic industry due to the rapid advances in power integrated circuit (IC) fabrication and the demands of a growing market in almost all areas of power electronic application such as portable electronics, consumer electronics, home electronics, computing electronics, automotive, railway and high/strong power industry. However, due to the intrinsic high power dissipation, the performance requirement for power products are extremely high, especially in handling harsh thermal and electrical environments. The design rules and material and structure layout of power packaging are quite different from regular IC packaging. This talk will present a state-of-art and in-depth overview of recent advances, challenges and opportunities in power electronic packaging design and modeling. A review of recent advances in power electronic packaging is presented based on the development of power device integration. The talk will cover in more detail how challenges in both semiconductor content and advanced power package design and materials have co-enabled significant advances in power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Along with new power packaging development, modeling is a key to assure successful package design. An overview of the power package modeling is presented. Challenges of power semiconductor packaging and modeling in both next generation design and assembly processes are presented and discussed.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114298386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765796
B. B. Hornales
Packaging engineers, in the search for the perfect packaging technology, are turning to three-dimensional packaging technologies that stack multiple dies/chips within a single package. Prevailing problems with stacked dies and clips are the tilting of the chips or clips due to the unbalanced bond line thickness of different solder attachments at different height levels or unbalanced weight distribution of the components inside the package. This could be a result of offset pads or inaccurate solder volume which results to uneven BLTs or solder joints, which all boils down to not having adequate modeling tools at hand to foresee potential tilting issues in a complicated solder joint system constrained in one package. This paper addresses this issue by utilizing an FEA modeling tool that can model the solder joint system of any stacked or clip packages. The tilting of the die is successfully modeled and the BLT predicted correlates well within the actual result. The mechanism of chip tilting was investigated and correlated with actual cross-section result. The availability of the modeling tool to successfully model multi-body solder joint system is a breakthrough in package tilting modeling efforts. Optimization of the solder joint system of any package is now possible with the Tool.
{"title":"Optimization of solder joint configuration in multi-chip packaging system","authors":"B. B. Hornales","doi":"10.1109/ESIME.2011.5765796","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765796","url":null,"abstract":"Packaging engineers, in the search for the perfect packaging technology, are turning to three-dimensional packaging technologies that stack multiple dies/chips within a single package. Prevailing problems with stacked dies and clips are the tilting of the chips or clips due to the unbalanced bond line thickness of different solder attachments at different height levels or unbalanced weight distribution of the components inside the package. This could be a result of offset pads or inaccurate solder volume which results to uneven BLTs or solder joints, which all boils down to not having adequate modeling tools at hand to foresee potential tilting issues in a complicated solder joint system constrained in one package. This paper addresses this issue by utilizing an FEA modeling tool that can model the solder joint system of any stacked or clip packages. The tilting of the die is successfully modeled and the BLT predicted correlates well within the actual result. The mechanism of chip tilting was investigated and correlated with actual cross-section result. The availability of the modeling tool to successfully model multi-body solder joint system is a breakthrough in package tilting modeling efforts. Optimization of the solder joint system of any package is now possible with the Tool.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126400968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765817
N. Manavizadeh, M. Pourfath, F. Raissi, E. Asl-Soleimani
The performance of nanoscale Field Effect Diode as a function of the doping concentration and the gate voltage is investigated. Our numerical results show that the Ion/Ioff ratio which is a significant parameter in digital application can be varied from 101 to 104 as the doping concentration of source/drain regions increased from 1016 to 1021cm−3. The figures of merit including intrinsic gate delay time and energy-delay product have been studied for the field effect diodes which are interesting candidates for future logic application.
{"title":"A comprehensive study of nanoscale Field Effect Diodes","authors":"N. Manavizadeh, M. Pourfath, F. Raissi, E. Asl-Soleimani","doi":"10.1109/ESIME.2011.5765817","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765817","url":null,"abstract":"The performance of nanoscale Field Effect Diode as a function of the doping concentration and the gate voltage is investigated. Our numerical results show that the I<inf>on</inf>/I<inf>off</inf> ratio which is a significant parameter in digital application can be varied from 10<sup>1</sup> to 10<sup>4</sup> as the doping concentration of source/drain regions increased from 10<sup>16</sup> to 10<sup>21</sup>cm<sup>−3</sup>. The figures of merit including intrinsic gate delay time and energy-delay product have been studied for the field effect diodes which are interesting candidates for future logic application.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133100742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765825
A. Alsakarneh, L. Moore, J. Barrett
Presented here is the use and optimization of mutli-layer viscoelastic buffer materials to protect embedded electronic systems from high mechanical forces such as impacts. The test vehicle was a solid sports ball, Figure 1. The embedded system was first encapsulated using standard epoxy encapsulant, then further encapsulated with two different buffer materials (a soft and a hard rubber) before the entire system was embedded in the ball. The ball (from the Irish game of hurling) has an original polyurethane/cork core encased in a leather outer skin and is 70 mm. in diameter and weighs 110g. The multi-layer buffering system reduces the imposed stress on the epoxy-encapsulated embedded system, so that the stress transmitted to the electronics is significantly reduced. From this point of view, the stress experienced at the embedded system edge was taken as the objective function to be minimized within the overall constraint that the modified ball must closely retain its original size, weight and “bounce” i.e. its Coefficient of Restitution (CoR). This is a specific example of the more general embedded systems problem of embedding, say, a system such as a wireless sensor node in a material or structure without significantly changing the material or structure mechanical properties and reliability. A numerical model, using ANSYS 11.0, was developed and used in a simulation-based designed experiment of eight runs. The element SOLID92 was used to model the plastic and electronic structures. The optimized multilayered structure reduced the stress on the embedded system by 50% in comparison to the original un-buffered structure and reduced stress by 25% in comparison to the non-optimized buffer system. The optimized structure was within 90% of the original one for weight and 85 % for CoR. This work has defined a design methodology for buffer layers that significantly increase the protection of embedded electronic systems from high mechanical forces without major impact on the host object mechanical properties. The methodology is particularly applicable to the mechanical design of smart objects and structures.
{"title":"Numerical modelling and optimization of an electronic system embedded in multi-layered viscoelastic materials under shock loads","authors":"A. Alsakarneh, L. Moore, J. Barrett","doi":"10.1109/ESIME.2011.5765825","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765825","url":null,"abstract":"Presented here is the use and optimization of mutli-layer viscoelastic buffer materials to protect embedded electronic systems from high mechanical forces such as impacts. The test vehicle was a solid sports ball, Figure 1. The embedded system was first encapsulated using standard epoxy encapsulant, then further encapsulated with two different buffer materials (a soft and a hard rubber) before the entire system was embedded in the ball. The ball (from the Irish game of hurling) has an original polyurethane/cork core encased in a leather outer skin and is 70 mm. in diameter and weighs 110g. The multi-layer buffering system reduces the imposed stress on the epoxy-encapsulated embedded system, so that the stress transmitted to the electronics is significantly reduced. From this point of view, the stress experienced at the embedded system edge was taken as the objective function to be minimized within the overall constraint that the modified ball must closely retain its original size, weight and “bounce” i.e. its Coefficient of Restitution (CoR). This is a specific example of the more general embedded systems problem of embedding, say, a system such as a wireless sensor node in a material or structure without significantly changing the material or structure mechanical properties and reliability. A numerical model, using ANSYS 11.0, was developed and used in a simulation-based designed experiment of eight runs. The element SOLID92 was used to model the plastic and electronic structures. The optimized multilayered structure reduced the stress on the embedded system by 50% in comparison to the original un-buffered structure and reduced stress by 25% in comparison to the non-optimized buffer system. The optimized structure was within 90% of the original one for weight and 85 % for CoR. This work has defined a design methodology for buffer layers that significantly increase the protection of embedded electronic systems from high mechanical forces without major impact on the host object mechanical properties. The methodology is particularly applicable to the mechanical design of smart objects and structures.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133565450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765863
M. Mayer
The risk of chip damage due to ultrasonic stresses in ball bonding needs to be managed while assuring a high bond strength. Chips with low-k dielectrics are less robust than those with SiO2, and if novel Cu or Pd coated Cu bonding wire is used, larger stresses are common during bonding. A finite element model can predict stresses at all locations under the pad including those due to the dynamics of the bonding tool. An experimental verification of these tool dynamics has not been done and is suggested using integrated piezo-resistive stress microsensors on a custom made testchip. The suitability of such a stress sensor design is discussed.
{"title":"Ultrasonic stresses in thermosonic ball bonding","authors":"M. Mayer","doi":"10.1109/ESIME.2011.5765863","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765863","url":null,"abstract":"The risk of chip damage due to ultrasonic stresses in ball bonding needs to be managed while assuring a high bond strength. Chips with low-k dielectrics are less robust than those with SiO2, and if novel Cu or Pd coated Cu bonding wire is used, larger stresses are common during bonding. A finite element model can predict stresses at all locations under the pad including those due to the dynamics of the bonding tool. An experimental verification of these tool dynamics has not been done and is suggested using integrated piezo-resistive stress microsensors on a custom made testchip. The suitability of such a stress sensor design is discussed.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131885832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765815
T. Hauck
The author studied the behavior of power packages exposed to repeatedly high current loads. Self-heating of the power transistors can cause a tremendous temperature rise in the vicinity of the active device. The resulting temperature gradient and the thermal mismatch of materials induce mechanical strains and stresses in the power package. The stress level can in some cases exceed the yield limit of the metallization layer on the die. Repetitive current peaks will then cause a fatigue phenomenon that can cause a device failure.
{"title":"Cyclic loading and fatigue in power packages","authors":"T. Hauck","doi":"10.1109/ESIME.2011.5765815","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765815","url":null,"abstract":"The author studied the behavior of power packages exposed to repeatedly high current loads. Self-heating of the power transistors can cause a tremendous temperature rise in the vicinity of the active device. The resulting temperature gradient and the thermal mismatch of materials induce mechanical strains and stresses in the power package. The stress level can in some cases exceed the yield limit of the metallization layer on the die. Repetitive current peaks will then cause a fatigue phenomenon that can cause a device failure.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129646141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765852
S. Y. Y. Leung, M. Sadeghinia, H. Pape, L. Ernst
Delamination between copper and epoxy molding compound (EMC) is one of the common failure modes in packages due to relatively weak adhesion at the interface. Delamination is difficult to predict because a package is often with a complex structure design constructed with different materials and under combined normal and shear loading. Development of cohesive zone elements applied in FEM has emerged into the application of cohesive zones as an effective tool for crack propagation simulation. In this study, a methodology to obtain useful parameters for cohesive zone modeling from experimental measurements is proposed. The approach is demonstrated with the adhesive joint between epoxy molding compound and copper that was under residual stresses and applied mixed-mode loading. The proposed approach to determine the traction-separation function does not rely on the uncertainties of crack tip stresses. The predicted load-displacement result is matched with experimental measurement results at the crack propagation region. Package delamination can be predicted by implementing the proposed testing and modeling scheme within the cohesive zone model.
{"title":"Prediction of mixed-mode interfacial fracture from cohesive zone finite element model: Testing and determination of fracture process parameters","authors":"S. Y. Y. Leung, M. Sadeghinia, H. Pape, L. Ernst","doi":"10.1109/ESIME.2011.5765852","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765852","url":null,"abstract":"Delamination between copper and epoxy molding compound (EMC) is one of the common failure modes in packages due to relatively weak adhesion at the interface. Delamination is difficult to predict because a package is often with a complex structure design constructed with different materials and under combined normal and shear loading. Development of cohesive zone elements applied in FEM has emerged into the application of cohesive zones as an effective tool for crack propagation simulation. In this study, a methodology to obtain useful parameters for cohesive zone modeling from experimental measurements is proposed. The approach is demonstrated with the adhesive joint between epoxy molding compound and copper that was under residual stresses and applied mixed-mode loading. The proposed approach to determine the traction-separation function does not rely on the uncertainties of crack tip stresses. The predicted load-displacement result is matched with experimental measurement results at the crack propagation region. Package delamination can be predicted by implementing the proposed testing and modeling scheme within the cohesive zone model.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116937569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765791
B. Curran, I. Ndip, J. Bauer, S. Guttowski, K. Lang, H. Reichl
Organic dielectric materials will absorb moisture when in direct contact with a liquid or a humid environment. The dielectric then becomes a two-phase dielectric composite with new dielectric characteristics. Using the Lichtenecker Equation, the composite dielectric permittivity and loss characteristics are modeled. The loss modeling includes the polymer dielectric loss characteristics, as well as the conductive loss of the moisture. The model is also used to predict the frequency dispersion of the relative permittivity at lower frequencies caused by the conductivity of the moisture. The modeling is validated using high frequency measurements of interdigital capacitors, which correspond to the modeling within 5% across the entire examined frequency range.
{"title":"The impact of moisture absorption on the electrical characteristics of organic dielectric materials","authors":"B. Curran, I. Ndip, J. Bauer, S. Guttowski, K. Lang, H. Reichl","doi":"10.1109/ESIME.2011.5765791","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765791","url":null,"abstract":"Organic dielectric materials will absorb moisture when in direct contact with a liquid or a humid environment. The dielectric then becomes a two-phase dielectric composite with new dielectric characteristics. Using the Lichtenecker Equation, the composite dielectric permittivity and loss characteristics are modeled. The loss modeling includes the polymer dielectric loss characteristics, as well as the conductive loss of the moisture. The model is also used to predict the frequency dispersion of the relative permittivity at lower frequencies caused by the conductivity of the moisture. The modeling is validated using high frequency measurements of interdigital capacitors, which correspond to the modeling within 5% across the entire examined frequency range.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123720642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Hui, Y. Yakoubi, M. Lenczner, S. Cogan, A. Meister, M. Favre, R. Couturier, S. Domas
In this paper, we present new tools and results developed for Arrays of Microsystems and especially for Atomic Force Microscope (AFM) array design. For modeling, we developed a two-scale model of cantilever arrays in elastodynamics. A robust optimization toolbox is interfaced to aid for design before the microfabrication process. A model based algorithm of static state estimation using measurement of mechanical displacements by interferometry is stated. Quantization of interferometry data processing is analyzed for FPGA implementation. A robust H∞ filtering problem of the coupled cantilevers is solved for time-invariant system with random noise effects. Our solution allows semi-decentralized computing based on functional calculus that can be implemented by networks of distributed electronic circuits as shown in a previous paper.
{"title":"Modeling, filtering and optimization for AFM arrays","authors":"H. Hui, Y. Yakoubi, M. Lenczner, S. Cogan, A. Meister, M. Favre, R. Couturier, S. Domas","doi":"10.1109/DMEMS.2012.15","DOIUrl":"https://doi.org/10.1109/DMEMS.2012.15","url":null,"abstract":"In this paper, we present new tools and results developed for Arrays of Microsystems and especially for Atomic Force Microscope (AFM) array design. For modeling, we developed a two-scale model of cantilever arrays in elastodynamics. A robust optimization toolbox is interfaced to aid for design before the microfabrication process. A model based algorithm of static state estimation using measurement of mechanical displacements by interferometry is stated. Quantization of interferometry data processing is analyzed for FPGA implementation. A robust H∞ filtering problem of the coupled cantilevers is solved for time-invariant system with random noise effects. Our solution allows semi-decentralized computing based on functional calculus that can be implemented by networks of distributed electronic circuits as shown in a previous paper.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127699498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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