Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765814
M. Pletz, R. Bermejo, P. Supancic, J. Stahr, M. Morianz
During laminating of Printed Circuit Boards (PCB) bending stresses in the embedded components can be generated due to pressure induced by the resin flow over them, which can lead to their fracture. In addition, the cooling of the PCB after curing of the resin can be even more important for the loading of the component. Here, the different coefficients of thermal expansion of the involved materials (i.e. pre-pregs, glass, resin, ceramic component) are the key parameters that can introduce residual stresses in the system. In this work the crucial steps in the integration of ceramic components into multi-layer PCBs have been investigated in terms of the mechanical stresses in the embedded components. In order to find the key parameters, the main process steps (i.e. laminating and cooling from the curing temperature) have been assessed using simple analytical and numerical FE models. The geometry used consists of several pre-preg layers (modelled as glass and resin layers) embedding a ceramic component. The stresses in the components are analysed and the most important parameters in terms of geometry and material properties are discussed.
{"title":"Numerical investigation of the process of embedding components into Printed Circuit Boards","authors":"M. Pletz, R. Bermejo, P. Supancic, J. Stahr, M. Morianz","doi":"10.1109/ESIME.2011.5765814","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765814","url":null,"abstract":"During laminating of Printed Circuit Boards (PCB) bending stresses in the embedded components can be generated due to pressure induced by the resin flow over them, which can lead to their fracture. In addition, the cooling of the PCB after curing of the resin can be even more important for the loading of the component. Here, the different coefficients of thermal expansion of the involved materials (i.e. pre-pregs, glass, resin, ceramic component) are the key parameters that can introduce residual stresses in the system. In this work the crucial steps in the integration of ceramic components into multi-layer PCBs have been investigated in terms of the mechanical stresses in the embedded components. In order to find the key parameters, the main process steps (i.e. laminating and cooling from the curing temperature) have been assessed using simple analytical and numerical FE models. The geometry used consists of several pre-preg layers (modelled as glass and resin layers) embedding a ceramic component. The stresses in the components are analysed and the most important parameters in terms of geometry and material properties are discussed.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125763544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765802
P. He, H. Fan, M. Yuen
Cu/Epoxy is known as one of the weakest joint in the electronic packages. Due to the lack of adhesion, the copper and epoxy encapsulant interface is prone to delaminate, and failure will happen in electronic devices. To solve this problem, the thiol-based self-assembled molecular (SAM) treatment is introduced by our group. The benzene ring will give the hydrophobic characteristic to the surface up on the formation of thiol layer. The selected thiol functional group will react with copper substrate. The other end of benzenethiol materials are designed to react with epoxy composite to build a chemical bridge between copper and epoxy.
{"title":"Investigation of benzenethiol (BT) materials as adhesion promoter for Cu/Epoxy interface using molecular dynamic simulation","authors":"P. He, H. Fan, M. Yuen","doi":"10.1109/ESIME.2011.5765802","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765802","url":null,"abstract":"Cu/Epoxy is known as one of the weakest joint in the electronic packages. Due to the lack of adhesion, the copper and epoxy encapsulant interface is prone to delaminate, and failure will happen in electronic devices. To solve this problem, the thiol-based self-assembled molecular (SAM) treatment is introduced by our group. The benzene ring will give the hydrophobic characteristic to the surface up on the formation of thiol layer. The selected thiol functional group will react with copper substrate. The other end of benzenethiol materials are designed to react with epoxy composite to build a chemical bridge between copper and epoxy.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126980658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765841
A. Kozlov, D. Randjelović, Z. Djuric
An analytical method is developed to determine the frequency response of thermal microsensors on various input actions. The method has the following algorithm. In a microsensor, the domain of modelling is marked out. This domain is divided into the regions with homogeneous parameters. For each region the non-steady-state heat conduction equation is obtained that is solved by means of the time Fourier transform. The heat flux densities between the regions are determined using adjoint boundary conditions in the frequency domain. After that, the analytical expression for the frequency response of the microsensor is obtained. The model is applied to the concrete membrane thermal microsensors, for which the modulus and argument of the frequency response and the time dependency of the output voltage for the step pulse input signal are determined.
{"title":"Analytical modelling of transient processes in thermal microsensors","authors":"A. Kozlov, D. Randjelović, Z. Djuric","doi":"10.1109/ESIME.2011.5765841","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765841","url":null,"abstract":"An analytical method is developed to determine the frequency response of thermal microsensors on various input actions. The method has the following algorithm. In a microsensor, the domain of modelling is marked out. This domain is divided into the regions with homogeneous parameters. For each region the non-steady-state heat conduction equation is obtained that is solved by means of the time Fourier transform. The heat flux densities between the regions are determined using adjoint boundary conditions in the frequency domain. After that, the analytical expression for the frequency response of the microsensor is obtained. The model is applied to the concrete membrane thermal microsensors, for which the modulus and argument of the frequency response and the time dependency of the output voltage for the step pulse input signal are determined.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115585472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765818
J. Jakovenko, R. Werkhoven, J. Formánek, J. Kunen, P. Bolt, P. Kulha
This work deals with thermal simulation and characterization of solid state lightening (SSL) LED Lamp in order to get precise 3D thermal models for further lamp thermal optimization. Simulations are performed with ANSYS-CFX and CoventorWare software tools. The simulated thermal distribution has been validated with thermal measurement on a commercial 8W LED lamp. Materials parametric study has been carried out to discover problematic parts for heat transfer from power LEDs to ambient. The objectives are to predict the thermal management by simulation of LED lamp and environment and to get more insight in the effect of lamp shape and materials used in order to design more effective LED lamps.
{"title":"Thermal simulation and validation of 8W LED Lamp","authors":"J. Jakovenko, R. Werkhoven, J. Formánek, J. Kunen, P. Bolt, P. Kulha","doi":"10.1109/ESIME.2011.5765818","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765818","url":null,"abstract":"This work deals with thermal simulation and characterization of solid state lightening (SSL) LED Lamp in order to get precise 3D thermal models for further lamp thermal optimization. Simulations are performed with ANSYS-CFX and CoventorWare software tools. The simulated thermal distribution has been validated with thermal measurement on a commercial 8W LED lamp. Materials parametric study has been carried out to discover problematic parts for heat transfer from power LEDs to ambient. The objectives are to predict the thermal management by simulation of LED lamp and environment and to get more insight in the effect of lamp shape and materials used in order to design more effective LED lamps.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124155796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765839
Kai Zhang, D. Xiao, Xiaohua Zhang, H. Fan, Z. Gao, M. Yuen
With the increasing application of high power LEDs in general lighting, more effective cooling solutions should be considered to maintain a better performance and reliability with lower LED junction temperature. In this paper, it is discussed firstly in detail how to effectively take advantage of high thermal performance materials, such as CNTs, to improve the heat conduction in LED packages. Secondly, the air flow velocity field generated by piezoelectric fans is simulated using 3D fluid structure interaction method (FSI) and verified with experimental data. A cooler with a piezoelectric fan inside is designed as a preliminary study on how to apply piezoelectric fans in LED active cooling.
{"title":"Thermal performance of LED packages for solid state lighting with novel cooling solutions","authors":"Kai Zhang, D. Xiao, Xiaohua Zhang, H. Fan, Z. Gao, M. Yuen","doi":"10.1109/ESIME.2011.5765839","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765839","url":null,"abstract":"With the increasing application of high power LEDs in general lighting, more effective cooling solutions should be considered to maintain a better performance and reliability with lower LED junction temperature. In this paper, it is discussed firstly in detail how to effectively take advantage of high thermal performance materials, such as CNTs, to improve the heat conduction in LED packages. Secondly, the air flow velocity field generated by piezoelectric fans is simulated using 3D fluid structure interaction method (FSI) and verified with experimental data. A cooler with a piezoelectric fan inside is designed as a preliminary study on how to apply piezoelectric fans in LED active cooling.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121292632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765776
Ting-Hsin Kuo, Yen-Fu Su, Chung-Jung Wu, K. Chiang
This study assesses the reliability life of 3D chip stacking packaging developed by the Industrial Technology Research Institute (ITRI). The simulation results show that the trends of stress of through silicon via (TSV) structures with different chip stacking numbers are nearly constant during thermal stress analysis. Therefore, the simplified two-layer chip stacking model is adopted to analyze the thermal-mechanical behavior of TSV. Subsequent thermal cycle simulations show that the maximum equivalent plastic strain occurs at the bottom trace near the substrate. The Engelmaier model is selected to predict the fatigue life of TSV, and it shows that the simulation results match experimental results. The effects of the substrate material and underfill are also discussed. TSV structures with BT substrates, which can replace silicon substrates, could effectively protect bottom traces and prevent fractures occurring from copper trace. In addition, when a TSV structure with an underfill is subjected to thermal cycle conditions, chips and vias experience more stress, but copper traces are protected by the underfill. No apparent alteration in reliability performance is detected.
{"title":"Stress/stain assessment and reliability prediction of through silicon via and trace line structures of 3D packaging","authors":"Ting-Hsin Kuo, Yen-Fu Su, Chung-Jung Wu, K. Chiang","doi":"10.1109/ESIME.2011.5765776","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765776","url":null,"abstract":"This study assesses the reliability life of 3D chip stacking packaging developed by the Industrial Technology Research Institute (ITRI). The simulation results show that the trends of stress of through silicon via (TSV) structures with different chip stacking numbers are nearly constant during thermal stress analysis. Therefore, the simplified two-layer chip stacking model is adopted to analyze the thermal-mechanical behavior of TSV. Subsequent thermal cycle simulations show that the maximum equivalent plastic strain occurs at the bottom trace near the substrate. The Engelmaier model is selected to predict the fatigue life of TSV, and it shows that the simulation results match experimental results. The effects of the substrate material and underfill are also discussed. TSV structures with BT substrates, which can replace silicon substrates, could effectively protect bottom traces and prevent fractures occurring from copper trace. In addition, when a TSV structure with an underfill is subjected to thermal cycle conditions, chips and vias experience more stress, but copper traces are protected by the underfill. No apparent alteration in reliability performance is detected.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"384 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122352993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765796
B. B. Hornales
Packaging engineers, in the search for the perfect packaging technology, are turning to three-dimensional packaging technologies that stack multiple dies/chips within a single package. Prevailing problems with stacked dies and clips are the tilting of the chips or clips due to the unbalanced bond line thickness of different solder attachments at different height levels or unbalanced weight distribution of the components inside the package. This could be a result of offset pads or inaccurate solder volume which results to uneven BLTs or solder joints, which all boils down to not having adequate modeling tools at hand to foresee potential tilting issues in a complicated solder joint system constrained in one package. This paper addresses this issue by utilizing an FEA modeling tool that can model the solder joint system of any stacked or clip packages. The tilting of the die is successfully modeled and the BLT predicted correlates well within the actual result. The mechanism of chip tilting was investigated and correlated with actual cross-section result. The availability of the modeling tool to successfully model multi-body solder joint system is a breakthrough in package tilting modeling efforts. Optimization of the solder joint system of any package is now possible with the Tool.
{"title":"Optimization of solder joint configuration in multi-chip packaging system","authors":"B. B. Hornales","doi":"10.1109/ESIME.2011.5765796","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765796","url":null,"abstract":"Packaging engineers, in the search for the perfect packaging technology, are turning to three-dimensional packaging technologies that stack multiple dies/chips within a single package. Prevailing problems with stacked dies and clips are the tilting of the chips or clips due to the unbalanced bond line thickness of different solder attachments at different height levels or unbalanced weight distribution of the components inside the package. This could be a result of offset pads or inaccurate solder volume which results to uneven BLTs or solder joints, which all boils down to not having adequate modeling tools at hand to foresee potential tilting issues in a complicated solder joint system constrained in one package. This paper addresses this issue by utilizing an FEA modeling tool that can model the solder joint system of any stacked or clip packages. The tilting of the die is successfully modeled and the BLT predicted correlates well within the actual result. The mechanism of chip tilting was investigated and correlated with actual cross-section result. The availability of the modeling tool to successfully model multi-body solder joint system is a breakthrough in package tilting modeling efforts. Optimization of the solder joint system of any package is now possible with the Tool.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126400968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765835
S. Douglas, J. Meng, J. Akman, İ. Yildiz, M. Al-Bassyiouni, A. Dasgupta
The continuing increase of functionality and miniaturization in handheld electronics has resulted in a decrease in the size and weight of the product. Therefore, internal structures such as printed wiring boards (PWBs) are becoming more slender, thus increasing the likelihood of unintentionally causing contact between the PWB and other internal structures like battery compartments, displays, and other circuit cards, or the interior of the case. Other researchers have concluded that secondary impact against the case of a portable device can be one of the causes for internal structures to experience highly amplified contact stresses and accelerations and cause damage to the subsystems. In this study, the term secondary impact, refers to subsequent impacts between multiple masses in a system after the system has been subjected to an event like a drop or impact. In this paper, the drop test specimen consists of a PWB populated with multiple functional MEMS components. Secondary impacts, between the test PWB and the fixture underneath, are used to generate very high accelerations (20,000 G) for drop testing. This acceleration level is typically well above those encountered in life-cycle conditions or in typical qualification testing. The velocity and acceleration of different locations on the test PWB are investigated with the help of parametric drop testing and dynamic finite element analysis, to determine its response to the magnitude of the impact with the fixture during drop testing. The MEMS components are functionally tested to understand the role of the impact acceleration on failure. The clearance between the PWB and the fixture are parametrically varied in the study to understand the role of the clearance. The experiments and simulations show interesting results because of the participation of multiple dynamic modes.
{"title":"The effect of secondary impacts on PWB-level drop tests at high impact accelerations","authors":"S. Douglas, J. Meng, J. Akman, İ. Yildiz, M. Al-Bassyiouni, A. Dasgupta","doi":"10.1109/ESIME.2011.5765835","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765835","url":null,"abstract":"The continuing increase of functionality and miniaturization in handheld electronics has resulted in a decrease in the size and weight of the product. Therefore, internal structures such as printed wiring boards (PWBs) are becoming more slender, thus increasing the likelihood of unintentionally causing contact between the PWB and other internal structures like battery compartments, displays, and other circuit cards, or the interior of the case. Other researchers have concluded that secondary impact against the case of a portable device can be one of the causes for internal structures to experience highly amplified contact stresses and accelerations and cause damage to the subsystems. In this study, the term secondary impact, refers to subsequent impacts between multiple masses in a system after the system has been subjected to an event like a drop or impact. In this paper, the drop test specimen consists of a PWB populated with multiple functional MEMS components. Secondary impacts, between the test PWB and the fixture underneath, are used to generate very high accelerations (20,000 G) for drop testing. This acceleration level is typically well above those encountered in life-cycle conditions or in typical qualification testing. The velocity and acceleration of different locations on the test PWB are investigated with the help of parametric drop testing and dynamic finite element analysis, to determine its response to the magnitude of the impact with the fixture during drop testing. The MEMS components are functionally tested to understand the role of the impact acceleration on failure. The clearance between the PWB and the fixture are parametrically varied in the study to understand the role of the clearance. The experiments and simulations show interesting results because of the participation of multiple dynamic modes.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116773661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765787
S. Ho, A. Tay
Absorption of moisture by plastic packages increases the susceptibility of packages to interfacial delamination. Accurate determination of moisture concentration can be important. In this numerical study, a plastic package is subjected to level 1 moisture preconditioning and is subsequently exposed to solder reflow process. Local moisture concentration and fracture mechanics parameters (energy release rate, ERR and mode mixity) are determined through finite element simulation. The impact of the thickness of the package, the die attach layer, the assumption of the independence of saturated moisture concentration (Csat) on temperature and the assumption of spatial isothermal condition are analyzed. When Csat is assumed to be independent of temperature (standard method), the local moisture concentration remains the same or decreases during solder reflow depending on the thickness, whereas when Csat is dependent on temperature, the local moisture concentration can increase during solder reflow. Limited influence on the fracture mechanics parameters is observed. Under spatial isothermal condition, when the temperature of the package is assumed to be equal to the oven temperature, the local moisture concentration is relatively similar to that obtained from the standard method. However, the combined ERR resulting from thermal stress, hygro stress and vapor pressure is more than that obtained from the standard method. Generally, the die attach layer does not result in significant changes in local moisture concentration but in its absence, the ERR is generally higher than the standard method.
{"title":"Moisture diffusion modeling and its impact on fracture mechanics parameters with regard to a PQFP","authors":"S. Ho, A. Tay","doi":"10.1109/ESIME.2011.5765787","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765787","url":null,"abstract":"Absorption of moisture by plastic packages increases the susceptibility of packages to interfacial delamination. Accurate determination of moisture concentration can be important. In this numerical study, a plastic package is subjected to level 1 moisture preconditioning and is subsequently exposed to solder reflow process. Local moisture concentration and fracture mechanics parameters (energy release rate, ERR and mode mixity) are determined through finite element simulation. The impact of the thickness of the package, the die attach layer, the assumption of the independence of saturated moisture concentration (Csat) on temperature and the assumption of spatial isothermal condition are analyzed. When Csat is assumed to be independent of temperature (standard method), the local moisture concentration remains the same or decreases during solder reflow depending on the thickness, whereas when Csat is dependent on temperature, the local moisture concentration can increase during solder reflow. Limited influence on the fracture mechanics parameters is observed. Under spatial isothermal condition, when the temperature of the package is assumed to be equal to the oven temperature, the local moisture concentration is relatively similar to that obtained from the standard method. However, the combined ERR resulting from thermal stress, hygro stress and vapor pressure is more than that obtained from the standard method. Generally, the die attach layer does not result in significant changes in local moisture concentration but in its absence, the ERR is generally higher than the standard method.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114841869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-04-18DOI: 10.1109/ESIME.2011.5765799
Y. Liu, D. Kinzer
Power electronic packaging is one of the fastest changing areas of technology in the power electronic industry due to the rapid advances in power integrated circuit (IC) fabrication and the demands of a growing market in almost all areas of power electronic application such as portable electronics, consumer electronics, home electronics, computing electronics, automotive, railway and high/strong power industry. However, due to the intrinsic high power dissipation, the performance requirement for power products are extremely high, especially in handling harsh thermal and electrical environments. The design rules and material and structure layout of power packaging are quite different from regular IC packaging. This talk will present a state-of-art and in-depth overview of recent advances, challenges and opportunities in power electronic packaging design and modeling. A review of recent advances in power electronic packaging is presented based on the development of power device integration. The talk will cover in more detail how challenges in both semiconductor content and advanced power package design and materials have co-enabled significant advances in power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Along with new power packaging development, modeling is a key to assure successful package design. An overview of the power package modeling is presented. Challenges of power semiconductor packaging and modeling in both next generation design and assembly processes are presented and discussed.
{"title":"Challenges of power electronic packaging and modeling","authors":"Y. Liu, D. Kinzer","doi":"10.1109/ESIME.2011.5765799","DOIUrl":"https://doi.org/10.1109/ESIME.2011.5765799","url":null,"abstract":"Power electronic packaging is one of the fastest changing areas of technology in the power electronic industry due to the rapid advances in power integrated circuit (IC) fabrication and the demands of a growing market in almost all areas of power electronic application such as portable electronics, consumer electronics, home electronics, computing electronics, automotive, railway and high/strong power industry. However, due to the intrinsic high power dissipation, the performance requirement for power products are extremely high, especially in handling harsh thermal and electrical environments. The design rules and material and structure layout of power packaging are quite different from regular IC packaging. This talk will present a state-of-art and in-depth overview of recent advances, challenges and opportunities in power electronic packaging design and modeling. A review of recent advances in power electronic packaging is presented based on the development of power device integration. The talk will cover in more detail how challenges in both semiconductor content and advanced power package design and materials have co-enabled significant advances in power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Along with new power packaging development, modeling is a key to assure successful package design. An overview of the power package modeling is presented. Challenges of power semiconductor packaging and modeling in both next generation design and assembly processes are presented and discussed.","PeriodicalId":115489,"journal":{"name":"2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114298386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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