Due to their near-ideal intrinsic features, double-gate (DG) MOSFETs (with thin, fully depleted (FD) Si-film (SOI) bodies) are of interest for possible future CMOS IC applications with L/sub eff/ approaching the lateral scaling limit (/spl sim/20 nm) (Fossum and Chong, 1998; Wong et al. 1998). Much of this interest stems from the two-channel property of the symmetrical-gate DG device and the implied higher current drive. More important, we believe, is the electrical coupling of the two gates through the FD Si film. This coupling underlies the inherent suppression of SCEs and the excellent subthreshold slope, which translate to high I/sub on//I/sub off/ ratios. In fact, as we show in this paper, the coupling can be exploited more in asymmetrical-gate DG MOSFETs (Fossum and Chong, 1998; Tanaka et al. 1994) than in symmetrical ones. We rely on numerical device simulations, using MEDICI and its hydrodynamic-transport option, and SOISPICE circuit simulations, using the UFSOI/FD MOSFET model (Fossum et al. 1998), to convey insight regarding performance and optimal design of DG MOSFETs and to reveal the inherent superiority of asymmetrical gates.
由于其接近理想的固有特性，双栅(DG) mosfet(具有薄的，完全耗尽(FD)硅膜(SOI)体)对于L/sub /接近横向缩放极限(/spl sim/20 nm)的未来CMOS IC应用很有兴趣(Fossum和Chong, 1998;Wong et al. 1998)。这种兴趣很大程度上源于对称栅DG器件的双通道特性和隐含的高电流驱动。我们认为，更重要的是两个栅极通过FD Si薄膜的电耦合。这种耦合是ses固有抑制和出色的亚阈值斜率的基础，这转化为高I/sub on//I/sub off/比率。事实上，正如我们在本文中所展示的，这种耦合可以在非对称栅DG mosfet中得到更多的利用(Fossum和Chong, 1998;Tanaka et al. 1994)。我们依靠数值器件模拟，使用MEDICI及其流体动力输运选项，以及SOISPICE电路模拟，使用UFSOI/FD MOSFET模型(Fossum et al. 1998)，来传达关于DG MOSFET的性能和优化设计的见解，并揭示不对称栅极的固有优势。
{"title":"Optimal double-gate MOSFETs: symmetrical or asymmetrical gates?","authors":"Keunwoo Kim, J. Fossum","doi":"10.1109/SOI.1999.819871","DOIUrl":"https://doi.org/10.1109/SOI.1999.819871","url":null,"abstract":"Due to their near-ideal intrinsic features, double-gate (DG) MOSFETs (with thin, fully depleted (FD) Si-film (SOI) bodies) are of interest for possible future CMOS IC applications with L/sub eff/ approaching the lateral scaling limit (/spl sim/20 nm) (Fossum and Chong, 1998; Wong et al. 1998). Much of this interest stems from the two-channel property of the symmetrical-gate DG device and the implied higher current drive. More important, we believe, is the electrical coupling of the two gates through the FD Si film. This coupling underlies the inherent suppression of SCEs and the excellent subthreshold slope, which translate to high I/sub on//I/sub off/ ratios. In fact, as we show in this paper, the coupling can be exploited more in asymmetrical-gate DG MOSFETs (Fossum and Chong, 1998; Tanaka et al. 1994) than in symmetrical ones. We rely on numerical device simulations, using MEDICI and its hydrodynamic-transport option, and SOISPICE circuit simulations, using the UFSOI/FD MOSFET model (Fossum et al. 1998), to convey insight regarding performance and optimal design of DG MOSFETs and to reveal the inherent superiority of asymmetrical gates.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130463550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper reviews recent developments in SOI based photonic integrated circuits. Waveguide technology and passive optical devices, including periodic waveguides, are discussed.
本文综述了近年来基于SOI的光子集成电路的研究进展。讨论了波导技术和无源光器件，包括周期波导。
{"title":"Advances in silicon-on-insulator photonic integrated circuit (SOIPIC) technology","authors":"M. Naydenkov, B. Jalali","doi":"10.1109/SOI.1999.819856","DOIUrl":"https://doi.org/10.1109/SOI.1999.819856","url":null,"abstract":"This paper reviews recent developments in SOI based photonic integrated circuits. Waveguide technology and passive optical devices, including periodic waveguides, are discussed.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129780929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Allen, D. Fenner, W. Skinner, R. Chandonnet, S.E. Deziel, R. Torti, N. Toyoda
A significant reliability aspect regarding commercial application of SOI is the consistency of the device gate oxide integrity (GOI). This research focuses on the smoothing of SIMOX SOI surfaces for advanced CMOS applications with improved GOI and reliability. As shown in an atomic force microscope (AFM) image, as-received samples of full dose single-implant SIMOX annealed in an Ar ambient show a distinct [100] tiling with a measured peak-to-valley surface roughness ranging from /spl sim/55 /spl Aring/ to /spl sim/70 /spl Aring/. These [100] faceted surface features result from silicon surface bond reconstruction during the 1310/spl deg/C SIMOX anneal temperature into their lowest free energy configuration. For the specific samples examined, the facets were typically 0.5 /spl mu/m in diameter with a mean deviation R(a) of 7.1 /spl Aring/ and R(rms) at 8.9 /spl Aring/. In order to reduce the faceting features as well as the surface roughness, a gas cluster ion beam (GCIB) method of surface smoothing was applied to the full dose single implant SIMOX samples.
{"title":"SIMOX SOI surface smoothing for gate oxide integrity and reliability","authors":"L. Allen, D. Fenner, W. Skinner, R. Chandonnet, S.E. Deziel, R. Torti, N. Toyoda","doi":"10.1109/SOI.1999.819880","DOIUrl":"https://doi.org/10.1109/SOI.1999.819880","url":null,"abstract":"A significant reliability aspect regarding commercial application of SOI is the consistency of the device gate oxide integrity (GOI). This research focuses on the smoothing of SIMOX SOI surfaces for advanced CMOS applications with improved GOI and reliability. As shown in an atomic force microscope (AFM) image, as-received samples of full dose single-implant SIMOX annealed in an Ar ambient show a distinct [100] tiling with a measured peak-to-valley surface roughness ranging from /spl sim/55 /spl Aring/ to /spl sim/70 /spl Aring/. These [100] faceted surface features result from silicon surface bond reconstruction during the 1310/spl deg/C SIMOX anneal temperature into their lowest free energy configuration. For the specific samples examined, the facets were typically 0.5 /spl mu/m in diameter with a mean deviation R(a) of 7.1 /spl Aring/ and R(rms) at 8.9 /spl Aring/. In order to reduce the faceting features as well as the surface roughness, a gas cluster ion beam (GCIB) method of surface smoothing was applied to the full dose single implant SIMOX samples.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"42 18","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120855630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fabrication of high-dose SIMOX (typically 1.8/spl times/10/sup 18/ cm/sup 2/ at 200 keV) is a maturing materials technology with increasing commercial usage. However, lower-dose SIMOX (2 to 4/spl times/10/sup 17/ cm/sup 2/) has the potential to be more economical, as well as allow device designers a choice of oxide thickness, but film uniformity and quality must be as good or better than standard high-dose material. A variety of approaches to produce low-dose SIMOX have been used which include: low dose implant plus ITOX (internal thermal oxidation), which uses a second high temperature anneal with high oxygen concentration (Nakashima et al. 1996; Mrstik et al. 1995); multiple energy implants (Alles, 1997); lower energy implantation (Anc et al. 1998); rapid ramping to the high temperature anneal range (Ogura, 1998); N pre-implantation (Meyappan et al. 1995); and very-low dose, post-implant amorphization prior to high temperature annealing (Holland et al. 1996; Bagchi et al. 1997). For the last technique, it was reported there were changes in the precipitation mechanisms that control BOX development. The first was elimination of multiply-faulted defects as sites for preferred nucleation and growth of oxides which form a discontinuous upper layer of precipitates in untreated material. The second was enhanced diffusion of oxygen along defects and phase boundaries in the amorphized region to the single BOX layer that was developing. In this research, we extend the work on post-implant-amorphized low-dose SIMOX by reporting effects of a single-step high oxygen concentration anneal on its BOX microstructure.
高剂量SIMOX的制造(通常为1.8/spl倍/10/sup 18/ cm/sup 2/在200 keV下)是一种成熟的材料技术，商业用途越来越多。然而，低剂量SIMOX(2至4/spl倍/10/sup 17/ cm/sup 2/)具有更经济的潜力，以及允许设备设计人员选择氧化物厚度，但薄膜均匀性和质量必须与标准高剂量材料一样好或更好。已经使用了多种生产低剂量SIMOX的方法，包括:低剂量植入物加ITOX(内部热氧化)，它使用高氧浓度的第二次高温退火(Nakashima等人，1996;Mrstik et al. 1995);多重能量植入(Alles, 1997);低能量注入(Anc et al. 1998);迅速上升到高温退火范围(Ogura, 1998);N植入前(Meyappan et al. 1995);以及非常低的剂量，在高温退火之前植入后非晶化(Holland et al. 1996;Bagchi et al. 1997)。对于最后一种技术，据报道，控制BOX发展的沉淀机制发生了变化。首先是消除多重缺陷作为氧化物优先成核和生长的场所，这些氧化物在未经处理的材料中形成不连续的上层沉淀。二是氧沿非晶区缺陷和相边界向正在形成的单BOX层扩散增强。在本研究中，我们通过报告单步高氧浓度退火对其BOX微观结构的影响，扩展了植入后非晶化低剂量SIMOX的工作。
{"title":"Effect of single-step, high-oxygen-concentration annealing on buried oxide layer microstructure in post-implant-amorphized, low-dose SIMOX material","authors":"L. Chen, S. Bagchi, S. Krause, P. Roitman","doi":"10.1109/SOI.1999.819883","DOIUrl":"https://doi.org/10.1109/SOI.1999.819883","url":null,"abstract":"Fabrication of high-dose SIMOX (typically 1.8/spl times/10/sup 18/ cm/sup 2/ at 200 keV) is a maturing materials technology with increasing commercial usage. However, lower-dose SIMOX (2 to 4/spl times/10/sup 17/ cm/sup 2/) has the potential to be more economical, as well as allow device designers a choice of oxide thickness, but film uniformity and quality must be as good or better than standard high-dose material. A variety of approaches to produce low-dose SIMOX have been used which include: low dose implant plus ITOX (internal thermal oxidation), which uses a second high temperature anneal with high oxygen concentration (Nakashima et al. 1996; Mrstik et al. 1995); multiple energy implants (Alles, 1997); lower energy implantation (Anc et al. 1998); rapid ramping to the high temperature anneal range (Ogura, 1998); N pre-implantation (Meyappan et al. 1995); and very-low dose, post-implant amorphization prior to high temperature annealing (Holland et al. 1996; Bagchi et al. 1997). For the last technique, it was reported there were changes in the precipitation mechanisms that control BOX development. The first was elimination of multiply-faulted defects as sites for preferred nucleation and growth of oxides which form a discontinuous upper layer of precipitates in untreated material. The second was enhanced diffusion of oxygen along defects and phase boundaries in the amorphized region to the single BOX layer that was developing. In this research, we extend the work on post-implant-amorphized low-dose SIMOX by reporting effects of a single-step high oxygen concentration anneal on its BOX microstructure.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121169178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Joshi, W. Hwang, S.C. Wilson, G. Shahidi, C. Chuang
Summary form only given. High performance register files are essential in fixed or floating point units of a high performance microprocessor. In this paper, the frequency dependent behavior of access time and pulse width of the dynamic register file and the circuit techniques to achieve robust operation in 1.8 V, 0.25 /spl mu/m partially depleted (PD) SOI technology are addressed.
{"title":"Frequency dependent behavior of a high performance dynamic register file in 1.8 V, 0.25 /spl mu/m SOI technology","authors":"R. Joshi, W. Hwang, S.C. Wilson, G. Shahidi, C. Chuang","doi":"10.1109/SOI.1999.819862","DOIUrl":"https://doi.org/10.1109/SOI.1999.819862","url":null,"abstract":"Summary form only given. High performance register files are essential in fixed or floating point units of a high performance microprocessor. In this paper, the frequency dependent behavior of access time and pulse width of the dynamic register file and the circuit techniques to achieve robust operation in 1.8 V, 0.25 /spl mu/m partially depleted (PD) SOI technology are addressed.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130477903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. van Meer, J. Lyu, S. Kubicek, L. Geenen, K. De Meyer
Summary form only given. Silicon-on-insulator (SOI) CMOS technology has proven to be compatible with bulk CMOS in many ways, ranging from circuit design and layout to wafer processing. In addition, partially-depleted (PD) SOI technology has been suggested as a method for achieving a high circuit performance at low supply voltage and low power (Jacobs et al, 1998). Unlike fully-depleted (FD) SOI transistors, PD SOI devices have the advantage of a threshold voltage V/sub T/ which is insensitive to variations in the silicon thickness uniformity. Based on device physics, the long-channel threshold voltage V/sub T/ is equal to the V/sub T/ of the bulk transistor as long as the channel doping concentrations are equal. Therefore, PD SOI CMOS design appears to be very similar to conventional bulk. Often, the design of a PD SOI CMOS technology is started from a present and well-known baseline bulk CMOS technology. During device fabrication, it is assumed, however, that the diffusivity of the channel dopants in the vertical direction in SOI is similar to bulk, which is fundamentally incorrect. In order to investigate the threshold voltage difference between PD SOI and bulk, SOI CMOS transistors have been fabricated on BESOI wafers with buried oxide and silicon layer thicknesses of 350 and 125 nm, respectively. In order to obtain a straight comparison with the bulk CMOS technology, each SOI wafer has a bulk counterpart for which the process conditions have been exactly the same.
只提供摘要形式。绝缘体上硅(SOI) CMOS技术已被证明在许多方面与体CMOS兼容，从电路设计和布局到晶圆加工。此外，部分耗尽(PD) SOI技术被认为是在低电源电压和低功率下实现高电路性能的一种方法(Jacobs等人，1998)。与完全耗尽(FD) SOI晶体管不同，PD SOI器件具有阈值电压V/sub T/的优势，对硅厚度均匀性的变化不敏感。根据器件物理原理，只要通道掺杂浓度相等，长通道阈值电压V/sub T/等于本体晶体管的V/sub T/。因此，PD SOI CMOS设计看起来与传统的体芯片非常相似。通常，PD SOI CMOS技术的设计是从目前已知的基线批量CMOS技术开始的。然而，在器件制造过程中，假设SOI中沟道掺杂剂在垂直方向上的扩散率与体相似，这从根本上是不正确的。为了研究PD SOI和本体之间的阈值电压差异，在埋地氧化层厚度为350 nm和硅层厚度分别为125 nm的BESOI晶圆上制备了SOI CMOS晶体管。为了获得与体CMOS技术的直接比较，每个SOI晶圆都有一个体对应，其工艺条件完全相同。
{"title":"Threshold voltage design incompatibility between partially-depleted SOI and bulk CMOS transistors","authors":"H. van Meer, J. Lyu, S. Kubicek, L. Geenen, K. De Meyer","doi":"10.1109/SOI.1999.819844","DOIUrl":"https://doi.org/10.1109/SOI.1999.819844","url":null,"abstract":"Summary form only given. Silicon-on-insulator (SOI) CMOS technology has proven to be compatible with bulk CMOS in many ways, ranging from circuit design and layout to wafer processing. In addition, partially-depleted (PD) SOI technology has been suggested as a method for achieving a high circuit performance at low supply voltage and low power (Jacobs et al, 1998). Unlike fully-depleted (FD) SOI transistors, PD SOI devices have the advantage of a threshold voltage V/sub T/ which is insensitive to variations in the silicon thickness uniformity. Based on device physics, the long-channel threshold voltage V/sub T/ is equal to the V/sub T/ of the bulk transistor as long as the channel doping concentrations are equal. Therefore, PD SOI CMOS design appears to be very similar to conventional bulk. Often, the design of a PD SOI CMOS technology is started from a present and well-known baseline bulk CMOS technology. During device fabrication, it is assumed, however, that the diffusivity of the channel dopants in the vertical direction in SOI is similar to bulk, which is fundamentally incorrect. In order to investigate the threshold voltage difference between PD SOI and bulk, SOI CMOS transistors have been fabricated on BESOI wafers with buried oxide and silicon layer thicknesses of 350 and 125 nm, respectively. In order to obtain a straight comparison with the bulk CMOS technology, each SOI wafer has a bulk counterpart for which the process conditions have been exactly the same.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123433174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ghavam G. Shahidi, A. Ajmera, Fariborz Assaderaghi, R. Bolam, Andres Bryant, M. Coffey, H. Hovel, J. Lasky, E. Leobandung, H.-S. Lo, M. Maloney, D. Moy, Werner A. Rausch, D. Sadana, Dominic J. Schepis, M. Sherony, J. Sleight, Lawrence F. Wagner, K. Wu, Bijan Davari, T. Chen
Partially-depleted deep sub-micron CMOS on SOI technology is becoming a mainstream technology. This technology offers 20-35% performance gain over a bulk technology implemented with the same lithography. In this paper, the challenges of mainstreaming the SOI technology in device, material, technology and circuit terms are described.
{"title":"Mainstreaming of the SOI technology","authors":"Ghavam G. Shahidi, A. Ajmera, Fariborz Assaderaghi, R. Bolam, Andres Bryant, M. Coffey, H. Hovel, J. Lasky, E. Leobandung, H.-S. Lo, M. Maloney, D. Moy, Werner A. Rausch, D. Sadana, Dominic J. Schepis, M. Sherony, J. Sleight, Lawrence F. Wagner, K. Wu, Bijan Davari, T. Chen","doi":"10.1109/SOI.1999.819828","DOIUrl":"https://doi.org/10.1109/SOI.1999.819828","url":null,"abstract":"Partially-depleted deep sub-micron CMOS on SOI technology is becoming a mainstream technology. This technology offers 20-35% performance gain over a bulk technology implemented with the same lithography. In this paper, the challenges of mainstreaming the SOI technology in device, material, technology and circuit terms are described.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121467443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Hirano, S. Maeda, T. Matsumoto, K. Nii, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, H. Kawashima, S. Maegawa, M. Inuishi, T. Nishimura
Transistor performance improvement has been strongly required for work toward highly integrated intelligent system LSIs. To meet this demand, silicon on insulator (SOI) has become of major interest for next generation devices, because it can offer durable device scaling as compared with bulk devices (Schepis et al. 1997). The critical issues for SOI are floating-body effects such as deterioration in drain current (Matsumoto et al. 1999), dynamic threshold voltage instability (Lu et al. 1997), and increased soft error rate (Wada et al. 1998). These have restricted the application of floating SOI, especially to analog circuits. Some circuit modifications and body contact insertions are necessary. A full body-fixing structure is another approach and some techniques have been proposed (Koh et al. 1997; Iwamatsu et al. 1995). However, when using these techniques, there have been some shortcomings in terms of scalability and layout compatibility. In this report, we propose a partial trench isolation (PTI) technique in which the body potential is fixed through the region under the trench oxide. With the PTI technology, we can eliminate floating-body effects while maintaining SOI-inherent merits and can realize scalable deep sub-quarter micron LSIs using accumulated bulk-design properties without layout modification. Moreover, the feasibility for ULSIs is demonstrated by a fully functional 4 Mbit SRAM.
为了实现高度集成的智能系统lsi，晶体管性能的改进是非常必要的。为了满足这一需求，绝缘体上硅(SOI)已成为下一代设备的主要兴趣，因为与批量设备相比，它可以提供持久的设备缩放(Schepis et al. 1997)。SOI的关键问题是浮体效应，如漏极电流恶化(Matsumoto et al. 1999)、动态阈值电压不稳定(Lu et al. 1997)和软错误率增加(Wada et al. 1998)。这些限制了浮动SOI的应用，特别是在模拟电路中。一些电路修改和身体接触插入是必要的。完整的身体固定结构是另一种方法，已经提出了一些技术(Koh等人，1997;Iwamatsu et al. 1995)。然而，当使用这些技术时，在可伸缩性和布局兼容性方面存在一些缺点。在本报告中，我们提出了一种局部沟槽隔离(PTI)技术，其中身体电位通过沟槽氧化物下的区域固定。使用PTI技术，我们可以在保持soi固有优点的同时消除浮体效应，并且可以在不修改布局的情况下利用累积的批量设计特性实现可扩展的深亚四分之一微米lsi。此外，一个功能齐全的4mbit SRAM证明了ulsi的可行性。
{"title":"Bulk-layout-compatible 0.18 /spl mu/m SOI-CMOS technology using body-fixed partial trench isolation (PTI)","authors":"Y. Hirano, S. Maeda, T. Matsumoto, K. Nii, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, H. Kawashima, S. Maegawa, M. Inuishi, T. Nishimura","doi":"10.1109/SOI.1999.819887","DOIUrl":"https://doi.org/10.1109/SOI.1999.819887","url":null,"abstract":"Transistor performance improvement has been strongly required for work toward highly integrated intelligent system LSIs. To meet this demand, silicon on insulator (SOI) has become of major interest for next generation devices, because it can offer durable device scaling as compared with bulk devices (Schepis et al. 1997). The critical issues for SOI are floating-body effects such as deterioration in drain current (Matsumoto et al. 1999), dynamic threshold voltage instability (Lu et al. 1997), and increased soft error rate (Wada et al. 1998). These have restricted the application of floating SOI, especially to analog circuits. Some circuit modifications and body contact insertions are necessary. A full body-fixing structure is another approach and some techniques have been proposed (Koh et al. 1997; Iwamatsu et al. 1995). However, when using these techniques, there have been some shortcomings in terms of scalability and layout compatibility. In this report, we propose a partial trench isolation (PTI) technique in which the body potential is fixed through the region under the trench oxide. With the PTI technology, we can eliminate floating-body effects while maintaining SOI-inherent merits and can realize scalable deep sub-quarter micron LSIs using accumulated bulk-design properties without layout modification. Moreover, the feasibility for ULSIs is demonstrated by a fully functional 4 Mbit SRAM.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"470 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123384601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Swaminathan, N. Fong, P. Lauzon, Hong-Kui Yang, M. Maliepaard, C. Plett, M. Snelgrove
A second-order double-sampled analog-to-digital /spl Sigma//spl Delta/ modulator is implemented in a 0.25 /spl mu/m fully-depleted silicon-on-insulator (FDSOI) CMOS process. FDSOI has a better subthreshold swing and reduced short-channel effect compared to traditional bulk CMOS, and therefore the threshold voltage and hence the supply voltage can be lowered for low power applications.
{"title":"A low power /spl Sigma//spl Delta/ analog-to-digital modulator with 50 MHz sampling rate in a 0.25 /spl mu/m SOI CMOS technology","authors":"A. Swaminathan, N. Fong, P. Lauzon, Hong-Kui Yang, M. Maliepaard, C. Plett, M. Snelgrove","doi":"10.1109/SOI.1999.819835","DOIUrl":"https://doi.org/10.1109/SOI.1999.819835","url":null,"abstract":"A second-order double-sampled analog-to-digital /spl Sigma//spl Delta/ modulator is implemented in a 0.25 /spl mu/m fully-depleted silicon-on-insulator (FDSOI) CMOS process. FDSOI has a better subthreshold swing and reduced short-channel effect compared to traditional bulk CMOS, and therefore the threshold voltage and hence the supply voltage can be lowered for low power applications.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123053978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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