The purpose of this work was to study the effects of oxygen implant conditions and post-implant processes on the photoluminescence (PL) behavior of the BOX layer of SIMOX structures. The effect of heat treatment of pseudo-SIMOX structures (top Si layer removed) is also reported; this point is relevant to the defect structure of BOX layers. An important aspect of this work is that the samples used in this work have been extensively studied by various electrical and other techniques so that the PL spectra could be correlated with the results of those studies.
{"title":"The effects of preparation conditions of SIMOX samples on the photoluminescence spectra of their buried oxide layer","authors":"W. Skorupa, L. Rebohle, A. Revesz, H. Hughes","doi":"10.1109/SOI.1999.819885","DOIUrl":"https://doi.org/10.1109/SOI.1999.819885","url":null,"abstract":"The purpose of this work was to study the effects of oxygen implant conditions and post-implant processes on the photoluminescence (PL) behavior of the BOX layer of SIMOX structures. The effect of heat treatment of pseudo-SIMOX structures (top Si layer removed) is also reported; this point is relevant to the defect structure of BOX layers. An important aspect of this work is that the samples used in this work have been extensively studied by various electrical and other techniques so that the PL spectra could be correlated with the results of those studies.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115260570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The application of SOI-CMOS to low-voltage, battery-powered devices is facing the practical trade-off between low threshold voltage and off-state leakage current. For typical portable electronic equipment, the specification for standby power dissipation restricts the MOSFET off-current to I/sub doff/<10 pA//spl mu/m, which should be compared with I/sub doff//spl sim/1 nA//spl mu/m in high-speed microprocessors (Leonbandung et al., 1998). In this paper, we investigate the off-current mechanism in SOI MOSFETs and its relationship with the IC's standby current for quantitative modeling. The model parameter extraction techniques are also described.
{"title":"The off leakage in SOI-MOS transistors and the impact on the standby current of ULSI's","authors":"A. Adan, K. Higashi, K. Nimi, T. Ashida","doi":"10.1109/SOI.1999.819845","DOIUrl":"https://doi.org/10.1109/SOI.1999.819845","url":null,"abstract":"Summary form only given. The application of SOI-CMOS to low-voltage, battery-powered devices is facing the practical trade-off between low threshold voltage and off-state leakage current. For typical portable electronic equipment, the specification for standby power dissipation restricts the MOSFET off-current to I/sub doff/<10 pA//spl mu/m, which should be compared with I/sub doff//spl sim/1 nA//spl mu/m in high-speed microprocessors (Leonbandung et al., 1998). In this paper, we investigate the off-current mechanism in SOI MOSFETs and its relationship with the IC's standby current for quantitative modeling. The model parameter extraction techniques are also described.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121937528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. At NASA, the focus for smaller, less costly missions has encouraged the development of microspacecraft. MEMS technology advances in terms of sensors, propulsion systems, and instruments make the notion of a specialized microspacecraft feasible in the immediate future. Emerging MEMS technology offers the integration of recent advances in micromachining and nanofabrication techniques with microelectronics in a mass-producible format, and is viewed as the next step in device and instrument miniaturization. MEMS technology has the potential to enable or enhance NASA missions in numerous ways. The technology allows component and system miniaturization, where the primary benefit is reduction in size, mass and power. MEMS technology also provides new capabilities and enhanced performance, with the greatest impact in performance, regardless of system size. Finally, with the availability of mass-produced, miniature MEMS instrumentation comes the opportunity to rethink fundamental measurement paradigms. It is now possible to expand horizons from a single instrument perspective to one involving multi-node or distributed systems. Distributed systems and missions give a new system in which functionality is enabled by a multiplicity of elements. In the future, integration of electronics, photonics, and micromechanical functionalities into "instruments-on-a-chip" will provide the ultimate size, cost, function and performance advantages. This presentation discusses recent developments and applications of MEMS technologies and devices for space applications.
{"title":"MEMS for space applications","authors":"T. Tang","doi":"10.1109/SOI.1999.819857","DOIUrl":"https://doi.org/10.1109/SOI.1999.819857","url":null,"abstract":"Summary form only given. At NASA, the focus for smaller, less costly missions has encouraged the development of microspacecraft. MEMS technology advances in terms of sensors, propulsion systems, and instruments make the notion of a specialized microspacecraft feasible in the immediate future. Emerging MEMS technology offers the integration of recent advances in micromachining and nanofabrication techniques with microelectronics in a mass-producible format, and is viewed as the next step in device and instrument miniaturization. MEMS technology has the potential to enable or enhance NASA missions in numerous ways. The technology allows component and system miniaturization, where the primary benefit is reduction in size, mass and power. MEMS technology also provides new capabilities and enhanced performance, with the greatest impact in performance, regardless of system size. Finally, with the availability of mass-produced, miniature MEMS instrumentation comes the opportunity to rethink fundamental measurement paradigms. It is now possible to expand horizons from a single instrument perspective to one involving multi-node or distributed systems. Distributed systems and missions give a new system in which functionality is enabled by a multiplicity of elements. In the future, integration of electronics, photonics, and micromechanical functionalities into \"instruments-on-a-chip\" will provide the ultimate size, cost, function and performance advantages. This presentation discusses recent developments and applications of MEMS technologies and devices for space applications.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127256713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Voldman, D. Hui, L. Warriner, D. Young, R. Williams, J. Howard, V. Gross, W. Rausch, E. Leobangdung, M. Sherony, N. Rohrer, C. Akrout, F. Assaderaghi, G. Shahidi
Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) semiconductor technology is perceived as a major roadblock for the SOI technology to become a viable mainstream contender for high-performance advanced CMOS semiconductor chips (Hu, 1994; Colinge, 1991). In this paper, our results in four successive SOI technology generations demonstrate that excellent ESD protection levels are achievable in SOI chips with no additional masking steps, process implants, costs or ESD design area. ESD results also show that the ESD robustness of the SOI ESD device is improving with partially depleted SOI MOSFET scaling from 0.25 to 0.12 /spl mu/m L/sub eff/ technology generations (Shahidi et al., 1999; Voldman et al., 1995, 1997, 1999). By allowing the ESD network minimum design to scale with the technology, improved ESD results are evident in each generation with no indication of any SOI-specific ESD limitations. For future technology generations below 1.5 V V/sub DD/ power supply, continued improvement is anticipated due to buried-oxide scaling, lower trigger voltages, dynamic threshold voltage MOSFET (DTMOS) techniques and ESD I/O design learning (Voldman et al, 1997; Assaderaghi et al., 1994). ESD protection of partially depleted SOI technology is not a problem or technology concern using our proposed ESD methodology.
绝缘体上硅(SOI)半导体技术中的静电放电(ESD)保护被认为是SOI技术成为高性能先进CMOS半导体芯片可行的主流竞争者的主要障碍(Hu, 1994;Colinge, 1991)。在本文中，我们对连续四代SOI技术的研究结果表明，在SOI芯片中，无需额外的屏蔽步骤、工艺植入、成本或ESD设计面积，即可实现出色的ESD保护水平。ESD结果还表明，随着部分耗尽的SOI MOSFET从0.25到0.12 /spl mu/m L/sub /技术世代，SOI ESD器件的ESD稳健性正在提高(Shahidi et al.， 1999;Voldman et al.， 1995,1997,1999)。通过允许ESD网络最小设计随技术扩展，每一代的ESD效果都得到了明显改善，没有任何特定于soi的ESD限制。对于低于1.5 V/sub DD/电源的未来技术世代，由于埋地氧化缩放、较低触发电压、动态阈值电压MOSFET (DTMOS)技术和ESD I/O设计学习，预计将继续改进(Voldman等，1997;Assaderaghi et al.， 1994)。使用我们提出的ESD方法，部分耗尽SOI技术的ESD保护不是一个问题或技术关注。
{"title":"Electrostatic discharge protection in silicon-on-insulator technology","authors":"S. Voldman, D. Hui, L. Warriner, D. Young, R. Williams, J. Howard, V. Gross, W. Rausch, E. Leobangdung, M. Sherony, N. Rohrer, C. Akrout, F. Assaderaghi, G. Shahidi","doi":"10.1109/SOI.1999.819858","DOIUrl":"https://doi.org/10.1109/SOI.1999.819858","url":null,"abstract":"Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) semiconductor technology is perceived as a major roadblock for the SOI technology to become a viable mainstream contender for high-performance advanced CMOS semiconductor chips (Hu, 1994; Colinge, 1991). In this paper, our results in four successive SOI technology generations demonstrate that excellent ESD protection levels are achievable in SOI chips with no additional masking steps, process implants, costs or ESD design area. ESD results also show that the ESD robustness of the SOI ESD device is improving with partially depleted SOI MOSFET scaling from 0.25 to 0.12 /spl mu/m L/sub eff/ technology generations (Shahidi et al., 1999; Voldman et al., 1995, 1997, 1999). By allowing the ESD network minimum design to scale with the technology, improved ESD results are evident in each generation with no indication of any SOI-specific ESD limitations. For future technology generations below 1.5 V V/sub DD/ power supply, continued improvement is anticipated due to buried-oxide scaling, lower trigger voltages, dynamic threshold voltage MOSFET (DTMOS) techniques and ESD I/O design learning (Voldman et al, 1997; Assaderaghi et al., 1994). ESD protection of partially depleted SOI technology is not a problem or technology concern using our proposed ESD methodology.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128779989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Circuit design using partially depleted (PD) SOI FETs must take into account a variable gate delay which is dependent on the switching history of the circuits (Gautier et al, 1997; Houston and Unnikrishnan, 1998). In order to fully exploit the advantages of SOI, it is important to understand and analyze such 'history effects' and consider them for an optimized design strategy. In this paper, we describe a methodology suitable to analyze PD SOI CMOS circuits, including a new algorithm for dynamic equilibrium computations, a task that is not practicable with standard circuit simulators because of the very slow evolution of the body potential (time constants up to ms (Assaderaghi et al., 1996)). Simulation results for a 0.2 /spl mu/m technology are given, showing the importance of design and application parameters with regard to the history effect.
使用部分耗尽(PD) SOI fet的电路设计必须考虑取决于电路开关历史的可变门延迟(Gautier等人，1997;Houston and Unnikrishnan, 1998)。为了充分利用SOI的优势，理解和分析这种“历史效应”并考虑它们来优化设计策略是很重要的。在本文中，我们描述了一种适合分析PD SOI CMOS电路的方法，包括一种用于动态平衡计算的新算法，由于身体电位的演变非常缓慢(时间常数高达ms (Assaderaghi et al.， 1996))，这一任务在标准电路模拟器中是不可行的。给出了0.2 /spl mu/m工艺的仿真结果，说明了设计和应用参数对历史效应的重要性。
{"title":"Detailed analysis of the gate delay variability in partially depleted SOI CMOS circuits","authors":"I. Aller, K. Kroell","doi":"10.1109/SOI.1999.819848","DOIUrl":"https://doi.org/10.1109/SOI.1999.819848","url":null,"abstract":"Circuit design using partially depleted (PD) SOI FETs must take into account a variable gate delay which is dependent on the switching history of the circuits (Gautier et al, 1997; Houston and Unnikrishnan, 1998). In order to fully exploit the advantages of SOI, it is important to understand and analyze such 'history effects' and consider them for an optimized design strategy. In this paper, we describe a methodology suitable to analyze PD SOI CMOS circuits, including a new algorithm for dynamic equilibrium computations, a task that is not practicable with standard circuit simulators because of the very slow evolution of the body potential (time constants up to ms (Assaderaghi et al., 1996)). Simulation results for a 0.2 /spl mu/m technology are given, showing the importance of design and application parameters with regard to the history effect.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133714984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
AC floating body effects have significantly impacted SOI analog circuit performance, such as degraded linearity due to the kink on output conductance (G/sub DS/) (Tseng et al., 1998) and higher phase noise due to low-frequency (LF) noise overshoot (Tseng et al., 1998). This is especially true for partially-depleted (PD) SOI MOSFETs. Recent high density integration of CMOS on a single chip increases the power dissipation density, resulting in an increased operating temperature. Only a few papers address the influence of high temperature operation for SOI analog applications (Dessard et al., 1998; Eggermont et al., 1996). In this study, AC floating body effects are explored in a wide temperature range (from 218 K to 423 K).
交流浮体效应显著影响了SOI模拟电路的性能，例如由于输出电导(G/sub DS/)的扭转而导致线性度下降(Tseng et al.， 1998)，以及由于低频(LF)噪声超调而导致的更高相位噪声(Tseng et al.， 1998)。对于部分耗尽(PD) SOI mosfet尤其如此。最近CMOS在单芯片上的高密度集成增加了功耗密度，导致工作温度升高。只有少数几篇论文讨论了高温运行对SOI模拟应用的影响(Dessard等人，1998;Eggermont et al.， 1996)。在本研究中，交流浮体效应在较宽的温度范围内(从218 K到423 K)进行了探索。
{"title":"Temperature dependence of AC floating body effects in PD SOI nMOS","authors":"Y. Tseng, W.M. Huang, C. Hwang, P. Welch, J. Woo","doi":"10.1109/SOI.1999.819841","DOIUrl":"https://doi.org/10.1109/SOI.1999.819841","url":null,"abstract":"AC floating body effects have significantly impacted SOI analog circuit performance, such as degraded linearity due to the kink on output conductance (G/sub DS/) (Tseng et al., 1998) and higher phase noise due to low-frequency (LF) noise overshoot (Tseng et al., 1998). This is especially true for partially-depleted (PD) SOI MOSFETs. Recent high density integration of CMOS on a single chip increases the power dissipation density, resulting in an increased operating temperature. Only a few papers address the influence of high temperature operation for SOI analog applications (Dessard et al., 1998; Eggermont et al., 1996). In this study, AC floating body effects are explored in a wide temperature range (from 218 K to 423 K).","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121466934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we have demonstrated the product performance of critical elements of an integrated RFIC. Key requirements and advantages of SOI have been correlated. A highly integrated SOI RFIC with over 100 passive components was shown to have performance suitable for CDMA handsets. We have also shown that SOI can deliver advantageous products.
{"title":"Single chip wireless systems using SOI","authors":"R. Reedy, J. Cable, D. Kelly","doi":"10.1109/SOI.1999.819833","DOIUrl":"https://doi.org/10.1109/SOI.1999.819833","url":null,"abstract":"In this paper, we have demonstrated the product performance of critical elements of an integrated RFIC. Key requirements and advantages of SOI have been correlated. A highly integrated SOI RFIC with over 100 passive components was shown to have performance suitable for CDMA handsets. We have also shown that SOI can deliver advantageous products.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114164821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The floating body effect is one of the most serious problems for applications of partially depleted (PD) SOI MOSFETs. In particular, the dynamic pass leakage caused by the floating body effect (Assaderaghi et al., 1996) degrades retention time in SOI DRAMs (Kim et al., 1996) and produces timing errors in dynamic circuits (Canada et al., 1999). Two mechanisms have been considered so far as the origin of dynamic pass leakage: (1) parasitic bipolar current (Assaderaghi et al., 1997; Wei and Antoniadis, 1996) and (2) subthreshold current (Kim et al., 1996; Morishita et al., 1995), as shown here, taking SOI DRAM cells as an example. However, no experimental data have been reported that distinguish between these two currents, and the mechanism of the dynamic pass leakage has not been reported. In this paper, the parasitic bipolar current and subthreshold current have been successfully separated in the transient measurements and the origin of the dynamic pass leakage has been clarified, to our knowledge, for the first time.
浮体效应是影响部分耗尽SOI mosfet应用的最严重问题之一。特别是，由浮体效应引起的动态通漏(Assaderaghi et al.， 1996)降低了SOI dram的保持时间(Kim et al.， 1996)，并在动态电路中产生时序误差(Canada et al.， 1999)。到目前为止，有两种机制被认为是动态通漏的起源:(1)寄生双极电流(Assaderaghi et al.， 1997;Wei and Antoniadis, 1996)和(2)阈下电流(Kim et al.， 1996;Morishita et al.， 1995)，如图所示，以SOI DRAM单元为例。然而，目前还没有实验数据来区分这两种电流，动态通漏的机理也没有报道。本文在瞬态测量中成功地分离了寄生双极电流和亚阈值电流，并首次阐明了动态通漏的来源。
{"title":"Mechanisms of dynamic pass leakage current in partially depleted SOI MOSFETs","authors":"T. Saraya, T. Hiramoto","doi":"10.1109/SOI.1999.819864","DOIUrl":"https://doi.org/10.1109/SOI.1999.819864","url":null,"abstract":"The floating body effect is one of the most serious problems for applications of partially depleted (PD) SOI MOSFETs. In particular, the dynamic pass leakage caused by the floating body effect (Assaderaghi et al., 1996) degrades retention time in SOI DRAMs (Kim et al., 1996) and produces timing errors in dynamic circuits (Canada et al., 1999). Two mechanisms have been considered so far as the origin of dynamic pass leakage: (1) parasitic bipolar current (Assaderaghi et al., 1997; Wei and Antoniadis, 1996) and (2) subthreshold current (Kim et al., 1996; Morishita et al., 1995), as shown here, taking SOI DRAM cells as an example. However, no experimental data have been reported that distinguish between these two currents, and the mechanism of the dynamic pass leakage has not been reported. In this paper, the parasitic bipolar current and subthreshold current have been successfully separated in the transient measurements and the origin of the dynamic pass leakage has been clarified, to our knowledge, for the first time.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121015148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Silicon-on-insulator (SOI) technology has been developed for electronics in harsh environments and more recently for low power electronics. Over the past few years, DARPA's Advanced Microelectronics Program has sponsored considerable research on 25 nm silicon transistors suitable for highly integrated circuits. Many of the device research efforts under the program are exploiting SOI. The program is described here.
{"title":"Advanced Microelectronics: the role of SOI","authors":"D. Radack","doi":"10.1109/SOI.1999.819832","DOIUrl":"https://doi.org/10.1109/SOI.1999.819832","url":null,"abstract":"Silicon-on-insulator (SOI) technology has been developed for electronics in harsh environments and more recently for low power electronics. Over the past few years, DARPA's Advanced Microelectronics Program has sponsored considerable research on 25 nm silicon transistors suitable for highly integrated circuits. Many of the device research efforts under the program are exploiting SOI. The program is described here.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127198726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Saraswat, S. Souri, V. Subramanian, A. Joshi, A.W. Wang
Summary form only given. Interconnect delays are increasingly dominating IC performance due to increased chip size and reductions in minimum feature size. Despite new materials like Cu with low-k dielectrics, interconnect delay is expected to be substantial below the 130 nm technology node, severely limiting chip performance. The need therefore exists for alternative technologies to overcome this problem. One such promising technique is 3D ICs with multiple active Si layers. In a 3D structure, a large number of information signal paths could be transferred from horizontal to vertical interconnects. 3D device integration in multiple Si layers obtainable via technologies like crystallization of amorphous Si and wafer bonding can potentially reduce chip area by increasing transistor packing density and reducing wiring requirements for wire-pitch limited ICs. Recently, we have estimated chip area for 3D ICs and demonstrated significant reductions in interconnect delay for a 0.18 /spl mu/m technology chip with 8 million gates (Souri et al., 1999). In this work, we generalize this analysis using NTRS technology projections down to the 50 nm node. The performance analysis incorporates the effects of increasing the number of active layers, moving repeaters from the substrate to upper active layers and optimizing wiring networks. Interconnect delay as a function of technology is calculated using data projected by the NTRS for 2D ICs. Also shown are delays for 3D ICs with 2 active layers, where wire pitches are increased to match the 2D IC areas, calculated using the 3D chip area estimation model. Interconnect delay is reduced by 64%.
只提供摘要形式。由于芯片尺寸的增加和最小特征尺寸的减小，互连延迟日益主导IC性能。尽管铜等新材料具有低k介电介质，但预计在130纳米技术节点以下的互连延迟会很大，严重限制了芯片的性能。因此，需要有替代技术来克服这一问题。其中一个很有前途的技术是具有多个有源硅层的3D集成电路。在三维结构中，大量的信息信号路径可以从水平互连点传递到垂直互连点。通过非晶硅结晶和晶圆键合等技术，可以在多个硅层中集成3D器件，通过增加晶体管封装密度和降低线间距有限的集成电路的布线要求，可以潜在地减少芯片面积。最近，我们估计了3D集成电路的芯片面积，并证明了具有800万个门的0.18 /spl mu/m技术芯片的互连延迟显着减少(Souri et al.， 1999)。在这项工作中，我们使用NTRS技术投影将该分析推广到50 nm节点。性能分析包括增加有源层数量、将中继器从基片移动到上层有源层和优化布线网络的影响。互连延迟作为技术的函数是使用NTRS对2D集成电路的投影数据计算的。还显示了具有2个有源层的3D IC的延迟，其中导线间距增加以匹配2D IC面积，使用3D芯片面积估计模型计算。互连延迟减少了64%。
{"title":"Novel 3-D structures [ICs]","authors":"K. Saraswat, S. Souri, V. Subramanian, A. Joshi, A.W. Wang","doi":"10.1109/SOI.1999.819855","DOIUrl":"https://doi.org/10.1109/SOI.1999.819855","url":null,"abstract":"Summary form only given. Interconnect delays are increasingly dominating IC performance due to increased chip size and reductions in minimum feature size. Despite new materials like Cu with low-k dielectrics, interconnect delay is expected to be substantial below the 130 nm technology node, severely limiting chip performance. The need therefore exists for alternative technologies to overcome this problem. One such promising technique is 3D ICs with multiple active Si layers. In a 3D structure, a large number of information signal paths could be transferred from horizontal to vertical interconnects. 3D device integration in multiple Si layers obtainable via technologies like crystallization of amorphous Si and wafer bonding can potentially reduce chip area by increasing transistor packing density and reducing wiring requirements for wire-pitch limited ICs. Recently, we have estimated chip area for 3D ICs and demonstrated significant reductions in interconnect delay for a 0.18 /spl mu/m technology chip with 8 million gates (Souri et al., 1999). In this work, we generalize this analysis using NTRS technology projections down to the 50 nm node. The performance analysis incorporates the effects of increasing the number of active layers, moving repeaters from the substrate to upper active layers and optimizing wiring networks. Interconnect delay as a function of technology is calculated using data projected by the NTRS for 2D ICs. Also shown are delays for 3D ICs with 2 active layers, where wire pitches are increased to match the 2D IC areas, calculated using the 3D chip area estimation model. Interconnect delay is reduced by 64%.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133676143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：