Intrinsic and extrinsic threshold voltage (V/sub ts/) fluctuations in fully depleted (FD) single gate (SG) and dual gate (DG) SOI MOSFETs as well as partially depleted (PD) SOI MOSFETs are investigated using novel 3D compact physical models. Threshold voltage maximum deviations due to intrinsic random dopant placement can escalate to more than /spl plusmn/100% for sub-100 nm technology generations. Much smaller (<1.5 mV) intrinsic threshold voltage fluctuations in undoped SOI MOSFETs are explored.
利用新颖的三维紧凑物理模型研究了完全耗尽(FD)单门(SG)和双门(DG) SOI mosfet以及部分耗尽(PD) SOI mosfet的内在和外在阈值电压(V/sub /)波动。对于sub-100 nm技术世代，由于内在随机掺杂物放置导致的阈值电压最大偏差可以升级到超过/spl plusmn/100%。在未掺杂的SOI mosfet中探索了更小(<1.5 mV)的固有阈值电压波动。
{"title":"SOI MOSFET fluctuation limits on gigascale integration (GSI)","authors":"Xinghai Tang, V. De, Lihui Wang, J. Meindl","doi":"10.1109/SOI.1999.819849","DOIUrl":"https://doi.org/10.1109/SOI.1999.819849","url":null,"abstract":"Intrinsic and extrinsic threshold voltage (V/sub ts/) fluctuations in fully depleted (FD) single gate (SG) and dual gate (DG) SOI MOSFETs as well as partially depleted (PD) SOI MOSFETs are investigated using novel 3D compact physical models. Threshold voltage maximum deviations due to intrinsic random dopant placement can escalate to more than /spl plusmn/100% for sub-100 nm technology generations. Much smaller (<1.5 mV) intrinsic threshold voltage fluctuations in undoped SOI MOSFETs are explored.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122816341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Sakaguchi, K. Yanagita, H. Kurisu, H. Suzuki, K. Ohmi, T. Yonehara
The ELTRAN/sup (R)/ SOI wafer process (Yonehara et al, 1994) has effectively used porous Si in the epitaxial and etching processes. In addition, porous Si again plays the other significant role in cost reduction. If the bonded pairs are split at the porous Si layers and the wasted starting materials (device wafers) are reused for the next device wafers, the manufacturing cost can be dramatically reduced. The splitting technique was developed and demonstrated using double layered porous Si in conjunction with water jets. The mechanism of splitting was investigated from the viewpoint of the stress in porous Si. The dynamic stress configuration was observed and controlled for the splitting of double porous Si layers. By reusing the device wafers, three-cycled ELTRAN/sup (R)/ wafers were successfully fabricated from one device wafer. SOI quality was found not to be degraded by the device wafer reuse and to be comparable to that of the conventional process.
ELTRAN/sup (R)/ SOI晶圆工艺(Yonehara et al .， 1994)在外延和蚀刻工艺中有效地使用了多孔硅。此外，多孔硅在降低成本方面也起着重要作用。如果在多孔硅层上将键合对分开，并且浪费的起始材料(器件晶片)可以在下一个器件晶片中重复使用，则可以大大降低制造成本。利用双层多孔硅与水射流相结合，开发并演示了劈裂技术。从多孔硅的应力角度研究了其劈裂机理。观察并控制了双孔硅层劈裂时的动态应力分布。通过重复利用器件晶圆，成功地在一个器件晶圆上制备了三循环ELTRAN/sup (R)/晶圆。结果发现，该装置晶圆的重复使用不会降低SOI的质量，并可与传统工艺相媲美。
{"title":"ELTRAN/sup (R)/ by water-jet splitting in stress-controlled porous Si","authors":"K. Sakaguchi, K. Yanagita, H. Kurisu, H. Suzuki, K. Ohmi, T. Yonehara","doi":"10.1109/SOI.1999.819877","DOIUrl":"https://doi.org/10.1109/SOI.1999.819877","url":null,"abstract":"The ELTRAN/sup (R)/ SOI wafer process (Yonehara et al, 1994) has effectively used porous Si in the epitaxial and etching processes. In addition, porous Si again plays the other significant role in cost reduction. If the bonded pairs are split at the porous Si layers and the wasted starting materials (device wafers) are reused for the next device wafers, the manufacturing cost can be dramatically reduced. The splitting technique was developed and demonstrated using double layered porous Si in conjunction with water jets. The mechanism of splitting was investigated from the viewpoint of the stress in porous Si. The dynamic stress configuration was observed and controlled for the splitting of double porous Si layers. By reusing the device wafers, three-cycled ELTRAN/sup (R)/ wafers were successfully fabricated from one device wafer. SOI quality was found not to be degraded by the device wafer reuse and to be comparable to that of the conventional process.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127096329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
CMOS active pixel sensors (APS) use the advantages of mature CMOS manufacturing technology and are competing with the currently dominant CCD technology in the state-of-the-art imaging applications that require low power, high integration and complex functionality. SOI technology has been proven to be advantageous in many applications compared with conventional bulk technology. However, image sensor integration on SOI substrates suffers from low quantum efficiency, which inhibits the development of SOI imaging systems. To overcome the barrier, CMOS compatible devices with self-amplification have been reported (Zhang et al. 1998; Yamamoto et al. 1996). However, the use of the high gain properties required a stable process and an accurate model for predicting the output, which are both not yet available. In this paper, we have investigated the performance of a hybrid active pixel structure. In this approach, the photodiode is built on the bottom substrate, while the reset transistor and the in-pixel amplifying transistor are built on the top silicon film. The performance of the APS is expected to be similar to the bulk technology, with potentially higher speed due to the lower capacitance that the photodiode has to drive in SOI technology. However, as a minimal deviation from the conventional SOI CMOS process is used to fabricate the APS, the photodiode is less optimized than current bulk technology. The operation of the APS in different configurations under different light intensities was studied and is reported.
CMOS有源像素传感器(APS)利用成熟的CMOS制造技术的优势，在需要低功耗、高集成度和复杂功能的最先进成像应用中，与目前占主导地位的CCD技术竞争。SOI技术已被证明在许多应用中与传统的散装技术相比具有优势。然而，在SOI衬底上集成图像传感器存在量子效率低的问题，这阻碍了SOI成像系统的发展。为了克服这一障碍，已经报道了具有自放大功能的CMOS兼容器件(Zhang et al. 1998;Yamamoto et al. 1996)。然而，高增益特性的使用需要一个稳定的过程和一个准确的模型来预测输出，这两者都还没有实现。本文研究了一种混合有源像元结构的性能。在这种方法中，光电二极管建在底部衬底上，而复位晶体管和像素内放大晶体管建在顶部硅膜上。APS的性能预计将与本体技术相似，由于SOI技术中光电二极管必须驱动的电容较低，因此可能具有更高的速度。然而，由于使用与传统SOI CMOS工艺的最小偏差来制造APS，因此光电二极管不如当前的批量技术优化。研究并报道了不同光强下不同结构下APS的运行情况。
{"title":"Building hybrid active pixels for CMOS imager on SOI substrate","authors":"Weiquan Zhang, M. Chan, Hongmei Wang, P. K. Ko","doi":"10.1109/SOI.1999.819873","DOIUrl":"https://doi.org/10.1109/SOI.1999.819873","url":null,"abstract":"CMOS active pixel sensors (APS) use the advantages of mature CMOS manufacturing technology and are competing with the currently dominant CCD technology in the state-of-the-art imaging applications that require low power, high integration and complex functionality. SOI technology has been proven to be advantageous in many applications compared with conventional bulk technology. However, image sensor integration on SOI substrates suffers from low quantum efficiency, which inhibits the development of SOI imaging systems. To overcome the barrier, CMOS compatible devices with self-amplification have been reported (Zhang et al. 1998; Yamamoto et al. 1996). However, the use of the high gain properties required a stable process and an accurate model for predicting the output, which are both not yet available. In this paper, we have investigated the performance of a hybrid active pixel structure. In this approach, the photodiode is built on the bottom substrate, while the reset transistor and the in-pixel amplifying transistor are built on the top silicon film. The performance of the APS is expected to be similar to the bulk technology, with potentially higher speed due to the lower capacitance that the photodiode has to drive in SOI technology. However, as a minimal deviation from the conventional SOI CMOS process is used to fabricate the APS, the photodiode is less optimized than current bulk technology. The operation of the APS in different configurations under different light intensities was studied and is reported.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134455770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Portable wireless communication applications have provided a relentless driving force for semiconductor manufacturers to deliver high performance circuits operating with drastically reduced supply voltage and power. To ultimately enable a single chip solution, process technology for these circuits must support all functions within the radio, from digital microcontrollers to RF downconversion. The literature reflects previous work that soundly demonstrates the advantages of thin-film-silicon-on-insulator (TFSOI) in low power digital baseband circuits such as microcontroller CPUs, SRAM, DRAM and ALUs (Huang et al. 1997). More recently, results of receiver functions such as low noise amplifiers, mixers, and VCOs implemented in TFSOI have been reported (Harada et al. 1997; Dekker et al. 1997; Tseng et al. 1998). Lack of a successful demonstration of a power amplifier has been one element preventing implementation of a complete TFSOI RF transceiver. This paper reports the results of the first demonstration of power amplifiers on TFSOI, using n-channel RF MOSFET devices.
便携式无线通信应用为半导体制造商提供了在大幅降低电源电压和功率的情况下运行的高性能电路提供了不懈的推动力。为了最终实现单芯片解决方案，这些电路的工艺技术必须支持无线电中的所有功能，从数字微控制器到射频下变频。文献反映了先前的工作，充分证明了薄膜绝缘体上硅(TFSOI)在低功耗数字基带电路(如微控制器cpu、SRAM、DRAM和alu)中的优势(Huang et al. 1997)。最近，在TFSOI中实现的低噪声放大器、混频器和vco等接收功能的结果已被报道(Harada et al. 1997;Dekker et al. 1997;Tseng et al. 1998)。缺乏功率放大器的成功演示一直是阻碍实现完整的TFSOI射频收发器的一个因素。本文报道了在TFSOI上使用n沟道射频MOSFET器件的功率放大器的首次演示结果。
{"title":"Power amplifiers on thin-film-silicon-on-insulator (TFSOI) technology","authors":"D. Ngo, W.M. Huang, J. Ford, D. Spooner","doi":"10.1109/SOI.1999.819888","DOIUrl":"https://doi.org/10.1109/SOI.1999.819888","url":null,"abstract":"Portable wireless communication applications have provided a relentless driving force for semiconductor manufacturers to deliver high performance circuits operating with drastically reduced supply voltage and power. To ultimately enable a single chip solution, process technology for these circuits must support all functions within the radio, from digital microcontrollers to RF downconversion. The literature reflects previous work that soundly demonstrates the advantages of thin-film-silicon-on-insulator (TFSOI) in low power digital baseband circuits such as microcontroller CPUs, SRAM, DRAM and ALUs (Huang et al. 1997). More recently, results of receiver functions such as low noise amplifiers, mixers, and VCOs implemented in TFSOI have been reported (Harada et al. 1997; Dekker et al. 1997; Tseng et al. 1998). Lack of a successful demonstration of a power amplifier has been one element preventing implementation of a complete TFSOI RF transceiver. This paper reports the results of the first demonstration of power amplifiers on TFSOI, using n-channel RF MOSFET devices.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114153764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have fabricated a partially-depleted SOI laterally diffused MOSFET (LDMOSFET) that is designed for use in radio frequency (RF) power amplifiers (PA) for portable applications. The device is fabricated on thin film SIMOX wafers and is suitable for integration with SOI CMOS. A high breakdown voltage is attained using a simple body contact scheme and the RF performance is exceptional.
{"title":"A RF power LDMOS device on SOI","authors":"J. Fiorenza, J. D. del Alamo, D. Antoniadis","doi":"10.1109/SOI.1999.819870","DOIUrl":"https://doi.org/10.1109/SOI.1999.819870","url":null,"abstract":"We have fabricated a partially-depleted SOI laterally diffused MOSFET (LDMOSFET) that is designed for use in radio frequency (RF) power amplifiers (PA) for portable applications. The device is fabricated on thin film SIMOX wafers and is suitable for integration with SOI CMOS. A high breakdown voltage is attained using a simple body contact scheme and the RF performance is exceptional.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121980995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Separation by implantation of oxygen (SIMOX) substrates implanted with stoichiometric doses of oxygen (1.8/spl times/10/sup 18/O/sup +//cm/sup 2/) at high energy (180-200 keV) and annealed at high temperatures have been accepted in silicon technology. Four times lower doses and extended annealing schemes were shown to form 100 nm thick buried oxides (Nakashima et al. 1993; Izumi, 1997) with application in commercial processes. The need for lower cost SOI wafers and thinner layers in future fully-depleted circuits continuously stimulates efforts to develop lower dose, thin buried oxide processes (Giles et al. 1994; Meyyappan et al. 1995; Holland et al. 1996). This work aims to demonstrate the formation of SIMOX layers in large area wafers with further reduced oxygen doses at energies below 100 keV. At the low energy peak of oxygen, the distribution is shallower and the full width at half maximum of this distribution is smaller than that for high energy implantation. Implantation at 65 keV generates near factor of 2 lower lattice damage per ion compared to 200 keV implantation. This allows more favorable conditions for formation of a stoichiometric buried oxide at low energy rather than at high energy. In addition, the manufacturability is improved due to the direct tailoring of the layer thickness for the criteria of fully depleted circuits at the basic process.
用化学计量剂量的氧(1.8/spl次/10/sup 18/O/sup +//cm/sup 2/)注入高能(180-200 keV)并在高温下退火的SIMOX底物，在硅技术中已被接受。四倍的低剂量和扩展的退火方案显示形成100纳米厚的埋藏氧化物(Nakashima等人，1993;Izumi, 1997)在商业过程中的应用。在未来的全耗尽电路中，对低成本SOI晶圆和更薄层的需求不断刺激人们努力开发低剂量、薄埋氧化工艺(Giles et al. 1994;Meyyappan et al. 1995;Holland et al. 1996)。这项工作旨在证明在能量低于100 keV的情况下，进一步降低氧剂量，在大面积晶圆中形成SIMOX层。在氧的低能峰处，分布较浅，半峰处全宽小于高能注入时的分布。与200 keV注入相比，65 keV注入对每个离子的晶格损伤降低了近2倍。这使得在低能而不是高能下形成化学计量埋藏氧化物的条件更为有利。此外，由于在基本工艺中直接为完全耗尽电路的标准定制层厚度，可制造性得到了改善。
{"title":"Thin-layer SIMOX for future applications","authors":"M. Anc, R. Dolan, J. Jiao, T. Nakai","doi":"10.1109/SOI.1999.819875","DOIUrl":"https://doi.org/10.1109/SOI.1999.819875","url":null,"abstract":"Separation by implantation of oxygen (SIMOX) substrates implanted with stoichiometric doses of oxygen (1.8/spl times/10/sup 18/O/sup +//cm/sup 2/) at high energy (180-200 keV) and annealed at high temperatures have been accepted in silicon technology. Four times lower doses and extended annealing schemes were shown to form 100 nm thick buried oxides (Nakashima et al. 1993; Izumi, 1997) with application in commercial processes. The need for lower cost SOI wafers and thinner layers in future fully-depleted circuits continuously stimulates efforts to develop lower dose, thin buried oxide processes (Giles et al. 1994; Meyyappan et al. 1995; Holland et al. 1996). This work aims to demonstrate the formation of SIMOX layers in large area wafers with further reduced oxygen doses at energies below 100 keV. At the low energy peak of oxygen, the distribution is shallower and the full width at half maximum of this distribution is smaller than that for high energy implantation. Implantation at 65 keV generates near factor of 2 lower lattice damage per ion compared to 200 keV implantation. This allows more favorable conditions for formation of a stoichiometric buried oxide at low energy rather than at high energy. In addition, the manufacturability is improved due to the direct tailoring of the layer thickness for the criteria of fully depleted circuits at the basic process.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121114342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Kuang, M. J. Saccamango, P. Lu, C. Chuang, F. Assaderaghi
It has been reported (Kuang et al., 1997; Lu et al., 1997) that SOI passgate circuits suffer history effects and adverse initial-cycle parasitic bipolar currents, which cause difficulties in circuit timing and limit direct design reuse from original bulk circuits. SOI device body history can also induce transfer characteristics mismatch in dual-railed static or dynamic CMOS circuits, resulting in speed degradation or functional failures. This paper describes an efficient technique to alleviate initial-cycle bipolar currents while retaining the low-V/sub t/ floating body feature when the SOI devices concerned are on. We also present a dynamic body discharge technique to eliminate the mismatch problems in cross-coupled SOI CMOS topologies, for use in a variety of circuit families such as cascade voltage switch logic, latch-type sense amplifiers and analog operational amplifiers.
已有报道(Kuang et al.， 1997;Lu et al.， 1997)指出，SOI通道电路受到历史效应和不利的初始周期寄生双极电流的影响，这导致电路定时困难，并限制了原始批量电路的直接设计重用。在双轨静态或动态CMOS电路中，SOI器件的本体历史也会导致传输特性不匹配，从而导致速度下降或功能故障。本文描述了一种有效的技术，以减轻初始周期双极电流，同时保持低v /sub /浮体特性时，有关的SOI器件。我们还提出了一种动态体放电技术，以消除交叉耦合SOI CMOS拓扑中的失配问题，可用于各种电路系列，如级联电压开关逻辑，锁存型检测放大器和模拟运算放大器。
{"title":"A dynamic body discharge technique for SOI circuit applications","authors":"J. Kuang, M. J. Saccamango, P. Lu, C. Chuang, F. Assaderaghi","doi":"10.1109/SOI.1999.819861","DOIUrl":"https://doi.org/10.1109/SOI.1999.819861","url":null,"abstract":"It has been reported (Kuang et al., 1997; Lu et al., 1997) that SOI passgate circuits suffer history effects and adverse initial-cycle parasitic bipolar currents, which cause difficulties in circuit timing and limit direct design reuse from original bulk circuits. SOI device body history can also induce transfer characteristics mismatch in dual-railed static or dynamic CMOS circuits, resulting in speed degradation or functional failures. This paper describes an efficient technique to alleviate initial-cycle bipolar currents while retaining the low-V/sub t/ floating body feature when the SOI devices concerned are on. We also present a dynamic body discharge technique to eliminate the mismatch problems in cross-coupled SOI CMOS topologies, for use in a variety of circuit families such as cascade voltage switch logic, latch-type sense amplifiers and analog operational amplifiers.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116826049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. Sub-1 V CMOS/SOI circuit technology is the most effective candidate for ultra-low-power applications in future ULSIs. We have proposed a triple-V/sub th/ CMOS/SIMOX circuit (Fujii et al., 1998; Douseki et al., 1998) that operates at an ultra low supply voltage of less than 0.5 V. The circuit consists of fully-depleted low- and medium-V/sub th/ CMOS logic gates and partially-depleted high-V/sub th/ power switch transistors. The low-V/sub th/ CMOS logic gates in critical paths and medium-V/sub th/ logic gates in noncritical paths achieve fast operation and leakage current reduction in the active mode. In addition, high-V/sub th/ power-switch transistors dramatically cut the leakage current in the standby mode. To improve circuit performance, the delay time of the critical path in the low-V/sub th/ logic blocks should be reduced and lowand medium-V/sub th/ logic gates should be assigned without any loss of speed. In this paper, we describe a triple-V/sub th/ 54/spl times/54-b multiplier that uses a 108-b adder with a source-controlled transmission-gate multiplexer in the critical path and a Wallace tree block in which low- and medium-V/sub th/ logic gates are automatically assigned using EDA tools.
{"title":"A 0.5-V, 3-mW, 54/spl times/54-b multiplier with a triple-V/sub th/ CMOS/SIMOX circuit scheme","authors":"K. Fujii, T. Douseki","doi":"10.1109/SOI.1999.819859","DOIUrl":"https://doi.org/10.1109/SOI.1999.819859","url":null,"abstract":"Summary form only given. Sub-1 V CMOS/SOI circuit technology is the most effective candidate for ultra-low-power applications in future ULSIs. We have proposed a triple-V/sub th/ CMOS/SIMOX circuit (Fujii et al., 1998; Douseki et al., 1998) that operates at an ultra low supply voltage of less than 0.5 V. The circuit consists of fully-depleted low- and medium-V/sub th/ CMOS logic gates and partially-depleted high-V/sub th/ power switch transistors. The low-V/sub th/ CMOS logic gates in critical paths and medium-V/sub th/ logic gates in noncritical paths achieve fast operation and leakage current reduction in the active mode. In addition, high-V/sub th/ power-switch transistors dramatically cut the leakage current in the standby mode. To improve circuit performance, the delay time of the critical path in the low-V/sub th/ logic blocks should be reduced and lowand medium-V/sub th/ logic gates should be assigned without any loss of speed. In this paper, we describe a triple-V/sub th/ 54/spl times/54-b multiplier that uses a 108-b adder with a source-controlled transmission-gate multiplexer in the critical path and a Wallace tree block in which low- and medium-V/sub th/ logic gates are automatically assigned using EDA tools.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130608210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Ernst, D. Munteanu, S. Cristoloveanu, T. Ouisse, N. Hefyene, S. Horiguchi, Y. Ono, Y. Takahashi, K. Murase
The fabrication of very thin Si films is an absolute priority for successfully scaling down the channel length of SOI MOSFETs below 50-100nm. While "ultra-thin" is a generic terminology for Si films 30-50 nm thick, the focus of this paper is on much thinner films, in the terminal range of 1-5 nm. N-channel MOSFETs, fabricated at NTT (Japan) on low-dose SIMOX substrates (62 nm thick buried oxide) have elevated, thicker source and drain, natural (residual) body doping, thick gate oxide (50 nm) and long channel (30 /spl mu/m to attenuate the parasitic influence of series resistances and device topology). The transistor body has been thinned by sacrificial oxidation.
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In this paper, potential three-dimensional SOI CMOS VLSI circuit structures are laid out. Chip area, layout complexities, process costs, and impact on circuit performance are compared and discussed.
{"title":"Architecture and performance of 3-dimensional SOI circuits","authors":"R. Zhang, K. Roy, D. Janes","doi":"10.1109/SOI.1999.819850","DOIUrl":"https://doi.org/10.1109/SOI.1999.819850","url":null,"abstract":"In this paper, potential three-dimensional SOI CMOS VLSI circuit structures are laid out. Chip area, layout complexities, process costs, and impact on circuit performance are compared and discussed.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120900221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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