This paper describes a current memory cell integrated in a fully depleted SOI process. The circuit was designed to maintain its performance up to 225/spl deg/C. An application of the memory is demonstrated by measurements of a current doubler for an A/D converter.
{"title":"A SOI current memory for analog signal processing at high temperature","authors":"L. Portmann, M. Declercq","doi":"10.1109/SOI.1999.819837","DOIUrl":"https://doi.org/10.1109/SOI.1999.819837","url":null,"abstract":"This paper describes a current memory cell integrated in a fully depleted SOI process. The circuit was designed to maintain its performance up to 225/spl deg/C. An application of the memory is demonstrated by measurements of a current doubler for an A/D converter.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122323668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. Rozeau, J. Jomaah, C. Boussey, C. Raynaud, J. Pelloie, F. Balestra
During the past decade, several works have shown that SOI technologies are very promising for radiofrequency applications (Eggert et al., 1997). In this work, we compare two different types of SOI architecture, i.e. fully- and partially-depleted MOSFETs, operating at RF range and under low-voltage conditions.
{"title":"Comparison between fully- and partially-depleted SOI MOSFET's for low-power radio-frequency applications","authors":"O. Rozeau, J. Jomaah, C. Boussey, C. Raynaud, J. Pelloie, F. Balestra","doi":"10.1109/SOI.1999.819839","DOIUrl":"https://doi.org/10.1109/SOI.1999.819839","url":null,"abstract":"During the past decade, several works have shown that SOI technologies are very promising for radiofrequency applications (Eggert et al., 1997). In this work, we compare two different types of SOI architecture, i.e. fully- and partially-depleted MOSFETs, operating at RF range and under low-voltage conditions.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117157162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fringing fields into the buried oxide and substrate depletion region stand as a key limiting factor for SOI MOSFET channel length reduction beyond 0.1 /spl mu/m. In fully-depleted (FD) SOI transistors, they cause a strong DIBL enhancement and a parasitic back channel conduction. On the other hand, in partially-depleted (PD) devices, the back channel control is even more difficult. The understanding and modeling of this phenomenon is of major interest, especially for RF SOI applications on high resistivity substrates where the depleted substrates behave as dielectrics. Various solutions to reduce these drawbacks are envisaged, such as buried oxide shrinking or double gate devices (Colinge, 1997; Cristoloveanu and Li, 1995). Thus far, the fringing field effect was ignored or merely included in FD analytical models by use of adjustable parameters. This paper presents a simple physical model for the evaluation of short channel effects induced by the BOX and substrate depletion. We analyze the lateral drain field penetration in the BOX and substrate, and calculate the related fringing capacitances. The model serves to anticipate the buried oxide scaling and substrate resistivity effects and to suggest the "ground plane" (GP) concept (Ernst and Cristoloveanu, 1999; Wong et al, 1998) as a suitable architecture for deep sub-micron SOI MOSFETs.
埋藏氧化物和衬底耗尽区的边缘场是SOI MOSFET沟道长度降低到0.1 /spl mu/m以上的关键限制因素。在完全耗尽(FD) SOI晶体管中，它们会导致强DIBL增强和寄生反通道传导。另一方面，在部分耗尽(PD)器件中，反向通道控制更加困难。对这种现象的理解和建模是主要的兴趣，特别是对于RF SOI在高电阻率衬底上的应用，其中耗尽衬底表现为介电体。设想了各种减少这些缺点的解决方案，例如埋藏氧化物收缩或双栅装置(Colinge, 1997;Cristoloveanu and Li, 1995)。到目前为止，边缘场效应被忽略或仅仅通过使用可调参数纳入FD分析模型。本文提出了一个简单的物理模型，用于评价由BOX和衬底损耗引起的短通道效应。我们分析了横向漏场在箱体和衬底中的渗透情况，并计算了相关的边缘电容。该模型用于预测埋藏氧化物结垢和衬底电阻率效应，并提出“接地面”(GP)概念(Ernst and Cristoloveanu, 1999;Wong et al .， 1998)作为深亚微米SOI mosfet的合适架构。
{"title":"Buried oxide fringing capacitance: a new physical model and its implication on SOI device scaling and architecture","authors":"T. Ernst, S. Cristoloveanu","doi":"10.1109/SOI.1999.819847","DOIUrl":"https://doi.org/10.1109/SOI.1999.819847","url":null,"abstract":"Fringing fields into the buried oxide and substrate depletion region stand as a key limiting factor for SOI MOSFET channel length reduction beyond 0.1 /spl mu/m. In fully-depleted (FD) SOI transistors, they cause a strong DIBL enhancement and a parasitic back channel conduction. On the other hand, in partially-depleted (PD) devices, the back channel control is even more difficult. The understanding and modeling of this phenomenon is of major interest, especially for RF SOI applications on high resistivity substrates where the depleted substrates behave as dielectrics. Various solutions to reduce these drawbacks are envisaged, such as buried oxide shrinking or double gate devices (Colinge, 1997; Cristoloveanu and Li, 1995). Thus far, the fringing field effect was ignored or merely included in FD analytical models by use of adjustable parameters. This paper presents a simple physical model for the evaluation of short channel effects induced by the BOX and substrate depletion. We analyze the lateral drain field penetration in the BOX and substrate, and calculate the related fringing capacitances. The model serves to anticipate the buried oxide scaling and substrate resistivity effects and to suggest the \"ground plane\" (GP) concept (Ernst and Cristoloveanu, 1999; Wong et al, 1998) as a suitable architecture for deep sub-micron SOI MOSFETs.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114312770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Raynaud, O. Faynot, J. Pelloie, F. Martin, S. Tedesco, J. Cluzel, A. Grouillet, B. Dal'zotto, D. Vanhoenacker
Scalability of SOI technology into 0.13 /spl mu/m 1.2 V CMOS has been demonstrated for partially-depleted (PD) devices (Leobandung et al., 1998). Propagation delay versus active power can be greatly reduced by using fully-depleted (FD) devices, because threshold voltage (V/sub t/) and junction capacitance (increased by halo implant in case of bulk and PD devices) are lower. However, this advantage is possible only if transconductance is not degraded by high S/D resistance and if SCE and DIBL are well controlled, essentially by reducing silicon thickness. Furthermore, sensitivity of electrical parameters to silicon thickness (tsi) for FD devices is often mentioned as a critical process issue due to SOI substrate thickness nonuniformity. In this paper, we show (with both 2D simulations and measurements) that V/sub t/ control can be improved by a low energy S/D implant for enhancement-mode (EM) devices. S/D resistance can also be maintained at a low enough level by using a recessed-channel process, which allows the proper reduction of tsi exactly under the gate (Raynaud et al., 1998). Using a TiSi/sub 2/ salicide process on gate and elevated S/D regions, we have measured a maximum oscillation frequency f/sub max/ of 48 GHz at 0.9 V for 0.25 /spl mu/m NMOS. Finally, we show that, due to a balance between different physical effects, the distribution of critical parameters for digital applications (saturation and off currents, propagation delay and power consumption) is not degraded by silicon thickness nonuniformity.
SOI技术在0.13 /spl mu/m 1.2 V CMOS中的可扩展性已被证明用于部分耗尽(PD)器件(Leobandung et al.， 1998)。由于阈值电压(V/sub /)和结电容(在散装和PD器件的情况下通过光晕植入而增加)较低，因此使用全耗尽(FD)器件可以大大降低与有功功率相比的传播延迟。然而，只有当高S/D电阻不会降低跨导性，并且SCE和DIBL得到很好的控制(主要是通过减少硅厚度)时，这种优势才有可能实现。此外，由于SOI衬底厚度不均匀性，FD器件的电参数对硅厚度(tsi)的敏感性经常被认为是一个关键的工艺问题。在本文中，我们展示了(通过二维模拟和测量)通过低能量S/D植入增强模式(EM)器件可以改善V/sub / t/控制。S/D电阻也可以通过使用凹槽通道工艺保持在足够低的水平，这允许在栅极下适当降低tsi(雷诺等人，1998)。在栅极和提升S/D区域上使用TiSi/sub 2/ salicide工艺，我们测量了0.25 /spl mu/m NMOS在0.9 V下的最大振荡频率f/sub max/为48 GHz。最后，我们表明，由于不同物理效应之间的平衡，数字应用的关键参数(饱和和关闭电流，传播延迟和功耗)的分布不会因硅厚度不均匀性而降低。
{"title":"Scalability of fully-depleted SOI technology into 0.13 /spl mu/m 1.2 V-1 V CMOS generation","authors":"C. Raynaud, O. Faynot, J. Pelloie, F. Martin, S. Tedesco, J. Cluzel, A. Grouillet, B. Dal'zotto, D. Vanhoenacker","doi":"10.1109/SOI.1999.819865","DOIUrl":"https://doi.org/10.1109/SOI.1999.819865","url":null,"abstract":"Scalability of SOI technology into 0.13 /spl mu/m 1.2 V CMOS has been demonstrated for partially-depleted (PD) devices (Leobandung et al., 1998). Propagation delay versus active power can be greatly reduced by using fully-depleted (FD) devices, because threshold voltage (V/sub t/) and junction capacitance (increased by halo implant in case of bulk and PD devices) are lower. However, this advantage is possible only if transconductance is not degraded by high S/D resistance and if SCE and DIBL are well controlled, essentially by reducing silicon thickness. Furthermore, sensitivity of electrical parameters to silicon thickness (tsi) for FD devices is often mentioned as a critical process issue due to SOI substrate thickness nonuniformity. In this paper, we show (with both 2D simulations and measurements) that V/sub t/ control can be improved by a low energy S/D implant for enhancement-mode (EM) devices. S/D resistance can also be maintained at a low enough level by using a recessed-channel process, which allows the proper reduction of tsi exactly under the gate (Raynaud et al., 1998). Using a TiSi/sub 2/ salicide process on gate and elevated S/D regions, we have measured a maximum oscillation frequency f/sub max/ of 48 GHz at 0.9 V for 0.25 /spl mu/m NMOS. Finally, we show that, due to a balance between different physical effects, the distribution of critical parameters for digital applications (saturation and off currents, propagation delay and power consumption) is not degraded by silicon thickness nonuniformity.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124831423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The behavior in silicon for heavy metal elements, which have great influence on device process yield, has been studied for polished wafers and epitaxial wafers. Since thickness uniformity and crystal quality of SOI (silicon on insulator) layers have been improved for thin film SOI wafers, they will be applied to CMOS LSI devices in the near future. However, the behavior of impurities such as heavy metal elements in thin film SOI has not been investigated because of the difficulty of chemical analysis due to the thin film silicon layer and due to addition of contamination during evaluation. In this work, the behavior of Cu in thin film SOI and the BOX (buried oxide layer) was investigated for the first time by using radioactive isotope tracers, which can avoid the evaluation error by contamination from circumstances and step etching.
{"title":"Study of Cu diffusion in ultra thin bonded SOI wafers evaluated by using radioactive isotope tracers","authors":"J. Furihata, M. Nakano, K. Mitani","doi":"10.1109/SOI.1999.819884","DOIUrl":"https://doi.org/10.1109/SOI.1999.819884","url":null,"abstract":"The behavior in silicon for heavy metal elements, which have great influence on device process yield, has been studied for polished wafers and epitaxial wafers. Since thickness uniformity and crystal quality of SOI (silicon on insulator) layers have been improved for thin film SOI wafers, they will be applied to CMOS LSI devices in the near future. However, the behavior of impurities such as heavy metal elements in thin film SOI has not been investigated because of the difficulty of chemical analysis due to the thin film silicon layer and due to addition of contamination during evaluation. In this work, the behavior of Cu in thin film SOI and the BOX (buried oxide layer) was investigated for the first time by using radioactive isotope tracers, which can avoid the evaluation error by contamination from circumstances and step etching.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116461623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wafer bonding and etch-back has been used to manufacture a silicon material intended as substrate for high frequency applications. The space charge region surrounding the bonded silicon/silicon interface depletes the silicon, thereby causing semi-insulating behaviour at high frequencies. The formed material was characterized using measurements on metal transmission lines and the results were compared to similar measurements on SIMOX and bulk silicon wafers.
{"title":"High frequency losses in transmission lines made on SIMOX, bulk silicon and depleted silicon/silicon structures formed by wafer bonding","authors":"M. Johansson, M. Bergh, S. Bengtsson","doi":"10.1109/SOI.1999.819843","DOIUrl":"https://doi.org/10.1109/SOI.1999.819843","url":null,"abstract":"Wafer bonding and etch-back has been used to manufacture a silicon material intended as substrate for high frequency applications. The space charge region surrounding the bonded silicon/silicon interface depletes the silicon, thereby causing semi-insulating behaviour at high frequencies. The formed material was characterized using measurements on metal transmission lines and the results were compared to similar measurements on SIMOX and bulk silicon wafers.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126264220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SOI structures are becoming progressively thinner as device dimensions are scaled down. Although thinner layers of Si and SiO/sub 2/ can be made directly by (a) reducing the dose and energy of oxygen ions in the SIMOX process, and (b) using lower H/sup +/ implant energy in the SmartCut/sup TM/ wafer (Bruel, 1995), there are limits to how thin Si films can be made in that way. Therefore, direct thinning methods are often used to obtain the final thickness of Si on the buried oxide (BOX) layer. Sacrificial oxidation is frequently used, a process in which oxidation consumes Si and the oxide is removed by wet etching in a HF solution. Direct wet etching of Si is not used since the etch rates are not as well controlled as oxidation rates, and significant roughening of the surface may occur. In this paper, we discuss application of a conventional SC1 surface cleaning procedure for adjusting silicon film thickness. We also note that silicon removal during cleaning steps must be taken into account when processing thin SOI films.
{"title":"Thinning of Si in SOI wafers by the SC1 standard clean","authors":"G. Celler, D. Barr, J. Rosamilia","doi":"10.1109/SOI.1999.819879","DOIUrl":"https://doi.org/10.1109/SOI.1999.819879","url":null,"abstract":"SOI structures are becoming progressively thinner as device dimensions are scaled down. Although thinner layers of Si and SiO/sub 2/ can be made directly by (a) reducing the dose and energy of oxygen ions in the SIMOX process, and (b) using lower H/sup +/ implant energy in the SmartCut/sup TM/ wafer (Bruel, 1995), there are limits to how thin Si films can be made in that way. Therefore, direct thinning methods are often used to obtain the final thickness of Si on the buried oxide (BOX) layer. Sacrificial oxidation is frequently used, a process in which oxidation consumes Si and the oxide is removed by wet etching in a HF solution. Direct wet etching of Si is not used since the etch rates are not as well controlled as oxidation rates, and significant roughening of the surface may occur. In this paper, we discuss application of a conventional SC1 surface cleaning procedure for adjusting silicon film thickness. We also note that silicon removal during cleaning steps must be taken into account when processing thin SOI films.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127426152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Benson, W. Redman-White, C. Easson, N. D'Halleweyn, M. Uren
Investigations of floating body behaviour of partially depleted (PD) SOI MOSFETs have established the presence of frequency-dependent drain conductance behaviour below the onset of the kink effect (Howes and Redman-White, 1992). This is due to capacitive coupling, and is not related to self-heating (Caviglia and Iliadis, 1992; Redman-White et al. 1992). As the conductances associated with the body node are extremely low in this region, we found that there are unexpected constraints on both the formulation of PD SOI compact models and their implementation in circuit simulation packages.
对部分耗尽(PD) SOI mosfet的浮体行为的研究已经确定了在弯曲效应开始以下存在频率相关的漏极电导行为(Howes和Redman-White, 1992)。这是由于电容耦合，与自热无关(Caviglia和Iliadis, 1992;Redman-White et al. 1992)。由于与体节点相关的电导在该区域非常低，我们发现PD SOI紧凑模型的制定及其在电路仿真封装中的实现都存在意想不到的约束。
{"title":"Circuit simulator and compact model requisites for accurate simulation of AC floating body behaviour in PD SOI","authors":"J. Benson, W. Redman-White, C. Easson, N. D'Halleweyn, M. Uren","doi":"10.1109/SOI.1999.819889","DOIUrl":"https://doi.org/10.1109/SOI.1999.819889","url":null,"abstract":"Investigations of floating body behaviour of partially depleted (PD) SOI MOSFETs have established the presence of frequency-dependent drain conductance behaviour below the onset of the kink effect (Howes and Redman-White, 1992). This is due to capacitive coupling, and is not related to self-heating (Caviglia and Iliadis, 1992; Redman-White et al. 1992). As the conductances associated with the body node are extremely low in this region, we found that there are unexpected constraints on both the formulation of PD SOI compact models and their implementation in circuit simulation packages.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125478886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the boom in the wireless communications market, RF CMOS has attracted a great deal of interest because of its low cost and compatibility with logic circuits. The SOI substrate is especially robust in this case due to the low power nature originating from the reduced junction capacitances. To achieve the high operating frequency that is required in RF applications, it is important to have high transconductance, and this can be realized by reducing the gate length. However, shortening the gate length could meanwhile increase the gate resistance and thus degrade the unit power gain frequency. While the gate resistance can be reduced by using thicker silicide, this approach is not feasible wherever shallow junctions exist, as in the case of SOI and sub-0.1 /spl mu/m MOSFETs. In this regard, the polysilicon spacer gate structure (Kun H. To et al., 1998; Johnson et al., 1997) can provide the best solution. This structure, however, imposes a great problem for drain engineering when high performance is needed. In this work, a large tilt angle implant is proposed to implement the drain engineering. Due to the buried oxide, the drain junction depth is well controlled by the silicon film thickness and thus the short channel behaviour can be suppressed by using thinner Si films.
随着无线通信市场的蓬勃发展，射频CMOS因其低成本和与逻辑电路的兼容性而引起了人们的极大兴趣。在这种情况下，SOI衬底由于结电容减小而具有低功率特性，因此特别坚固。为了实现射频应用中所需的高工作频率，具有高跨导是很重要的，这可以通过减小栅极长度来实现。然而，缩短栅极长度同时会增加栅极电阻，从而降低单位功率增益频率。虽然栅极电阻可以通过使用更厚的硅化物来降低，但这种方法在存在浅结的情况下是不可可行的，例如SOI和低于0.1 /spl mu/m的mosfet。对此，多晶硅间隔栅结构(Kun H. To et al.， 1998;Johnson et al.， 1997)可以提供最佳解决方案。然而，这种结构给排水工程带来了很大的问题，当需要高性能时。本文提出了一种大倾角植入物来实现排水工程。由于埋藏的氧化物，漏极结深度由硅膜厚度很好地控制，因此可以通过使用更薄的硅膜来抑制短通道行为。
{"title":"High performance sub-0.1 /spl mu/m SOI polysilicon spacer gate MOSFETs using large angle tilted implant for drain engineering","authors":"K. To, J. Woo","doi":"10.1109/SOI.1999.819869","DOIUrl":"https://doi.org/10.1109/SOI.1999.819869","url":null,"abstract":"With the boom in the wireless communications market, RF CMOS has attracted a great deal of interest because of its low cost and compatibility with logic circuits. The SOI substrate is especially robust in this case due to the low power nature originating from the reduced junction capacitances. To achieve the high operating frequency that is required in RF applications, it is important to have high transconductance, and this can be realized by reducing the gate length. However, shortening the gate length could meanwhile increase the gate resistance and thus degrade the unit power gain frequency. While the gate resistance can be reduced by using thicker silicide, this approach is not feasible wherever shallow junctions exist, as in the case of SOI and sub-0.1 /spl mu/m MOSFETs. In this regard, the polysilicon spacer gate structure (Kun H. To et al., 1998; Johnson et al., 1997) can provide the best solution. This structure, however, imposes a great problem for drain engineering when high performance is needed. In this work, a large tilt angle implant is proposed to implement the drain engineering. Due to the buried oxide, the drain junction depth is well controlled by the silicon film thickness and thus the short channel behaviour can be suppressed by using thinner Si films.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122327474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. A critical factor in the development of SOI wafers and related CMOS technologies is the quality of the buried Si-SiO/sub 2/ interface. Careful wafer preparation is necessary to obtain reduced surface state density in order to suppress back channel leakage and improve hot carrier reliability and radiation hardness. However, the measurement of the back interface properties and in particular the interface state density remains one of the most difficult parameters to measure in SOI transistors. This is because the large thickness of the buried oxide (relative to gate oxide) renders the usual techniques insensitive and very difficult to apply (Ioannou et al., 1991; Wuters et al., 1989). There has recently been renewed interest in an old technique based on the gated-diode concept (Grove and Fitzelard, 1966), new refinements and modifications of which are being used for the study of current bulk CMOS technologies (Cai and Sah, 1999; Guan et al., 1999). The purpose of this paper is to explain how the presence of two channels makes the adaptation of this technique particularly useful for SOI MOSFETs and suitable for evaluation of the buried interface. The present approach is distinct from and complementary to a recently published modification of the gated-diode technique applied to dual-gate SOI devices for measurement of the recombination lifetime (Ernst et al., 1999).
只提供摘要形式。SOI晶圆和相关CMOS技术发展的一个关键因素是埋置Si-SiO/sub - 2/接口的质量。为了抑制回道泄漏，提高热载子可靠性和辐射硬度，需要精心制备晶片以降低表面态密度。然而，后界面特性的测量，特别是界面态密度的测量仍然是SOI晶体管中最难测量的参数之一。这是因为埋藏氧化物(相对于栅极氧化物)的大厚度使得通常的技术不敏感并且很难应用(Ioannou等人，1991;Wuters et al.， 1989)。最近，人们对基于门二极管概念的旧技术重新产生了兴趣(Grove和Fitzelard, 1966)，对其进行了新的改进和修改，用于研究当前的大块CMOS技术(Cai和Sah, 1999;Guan等人，1999)。本文的目的是解释两个通道的存在如何使该技术的适应对SOI mosfet特别有用，并适用于埋藏界面的评估。目前的方法与最近发表的用于测量复合寿命的双栅SOI器件的门二极管技术的改进不同，并且是互补的(Ernst et al.， 1999)。
{"title":"\"Gated-diode\" in SOI MOSFETs: a sensitive tool for characterizing the buried Si-SiO/sub 2/ interface","authors":"Xuejun Zhao, D. Ioannou","doi":"10.1109/SOI.1999.819854","DOIUrl":"https://doi.org/10.1109/SOI.1999.819854","url":null,"abstract":"Summary form only given. A critical factor in the development of SOI wafers and related CMOS technologies is the quality of the buried Si-SiO/sub 2/ interface. Careful wafer preparation is necessary to obtain reduced surface state density in order to suppress back channel leakage and improve hot carrier reliability and radiation hardness. However, the measurement of the back interface properties and in particular the interface state density remains one of the most difficult parameters to measure in SOI transistors. This is because the large thickness of the buried oxide (relative to gate oxide) renders the usual techniques insensitive and very difficult to apply (Ioannou et al., 1991; Wuters et al., 1989). There has recently been renewed interest in an old technique based on the gated-diode concept (Grove and Fitzelard, 1966), new refinements and modifications of which are being used for the study of current bulk CMOS technologies (Cai and Sah, 1999; Guan et al., 1999). The purpose of this paper is to explain how the presence of two channels makes the adaptation of this technique particularly useful for SOI MOSFETs and suitable for evaluation of the buried interface. The present approach is distinct from and complementary to a recently published modification of the gated-diode technique applied to dual-gate SOI devices for measurement of the recombination lifetime (Ernst et al., 1999).","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130737020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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