A new SOI MOSFET structure utilizing a novel body potential control scheme is proposed. In its 'on' state, its body potential is electrically isolated from the external body terminal by the gate depletion layer, and is controlled automatically through the drain current and drain voltage. More than 30% improvement in current drivability is predicted.
{"title":"'Self-body-biased' SOI MOSFET through 'depletion isolation effect'","authors":"M. Terauchi, K. Terada","doi":"10.1109/SOI.1999.819846","DOIUrl":"https://doi.org/10.1109/SOI.1999.819846","url":null,"abstract":"A new SOI MOSFET structure utilizing a novel body potential control scheme is proposed. In its 'on' state, its body potential is electrically isolated from the external body terminal by the gate depletion layer, and is controlled automatically through the drain current and drain voltage. More than 30% improvement in current drivability is predicted.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133772332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A voltage reference circuit with 3 V output has been designed and implemented in an SOI FD (fully-depleted) CMOS technology for very wide temperature range applications. The design uses lateral bipolar transistors and thin-film diffusion resistors. The circuit has been fabricated and tested over the full operating temperature range (25/spl deg/C-300/spl deg/C) and provides a temperature coefficient better than 100 ppm//spl deg/C.
{"title":"A bandgap circuit operating up to 300/spl deg/C using lateral bipolar transistors in thin-film CMOS-SOI technology","authors":"S. Adriaensen, V. Dessard, D. Flandre","doi":"10.1109/SOI.1999.819838","DOIUrl":"https://doi.org/10.1109/SOI.1999.819838","url":null,"abstract":"A voltage reference circuit with 3 V output has been designed and implemented in an SOI FD (fully-depleted) CMOS technology for very wide temperature range applications. The design uses lateral bipolar transistors and thin-film diffusion resistors. The circuit has been fabricated and tested over the full operating temperature range (25/spl deg/C-300/spl deg/C) and provides a temperature coefficient better than 100 ppm//spl deg/C.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114556085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiaohui Tang, X. Baie, V. Bayot, F. van de Wiele, J. Colinge
Single-electron transistors (SETs) are currently being investigated by many research groups as possible devices for ultra-high-density, low-power information processing or storage systems. A single-electron transistor consists of two tunnel junctions (TJ) connected to the source and the drain, a center floating node and a capacitance connected to the device gate. It takes a finite minimum source-to center node bias to inject an electron into the node by tunneling. This effect is called Coulomb blockade. In this paper, SET devices were fabricated using thin-silicon (100 nm) Unibond/sup (R)/ wafers and e-beam lithography, and were found to exhibit the Coulomb blockade effects predicted by theory.
{"title":"An SOI single-electron transistor","authors":"Xiaohui Tang, X. Baie, V. Bayot, F. van de Wiele, J. Colinge","doi":"10.1109/SOI.1999.819851","DOIUrl":"https://doi.org/10.1109/SOI.1999.819851","url":null,"abstract":"Single-electron transistors (SETs) are currently being investigated by many research groups as possible devices for ultra-high-density, low-power information processing or storage systems. A single-electron transistor consists of two tunnel junctions (TJ) connected to the source and the drain, a center floating node and a capacitance connected to the device gate. It takes a finite minimum source-to center node bias to inject an electron into the node by tunneling. This effect is called Coulomb blockade. In this paper, SET devices were fabricated using thin-silicon (100 nm) Unibond/sup (R)/ wafers and e-beam lithography, and were found to exhibit the Coulomb blockade effects predicted by theory.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121192833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Jagar, M. Chan, K. C. Poon, Hongmei Wang, M. Qin, S. Shivani, P. Ko, Yangyuan Wang
In current SOI technology, the formation of circuit elements requires the use of some special starting material like SIMOX, BESOI or Unibond wafers, which usually cannot be made in-house. As such, it leads to a divergence between SOI technology and bulk technology, and there are debates on justification on the initial material cost. TFTs formed in polysilicon have similar structures to SOI, and have been used as the load element in SRAM. Comparing TFT and SOI transistors, the TFT is easier to fabricate in term of starting material and compatibility with bulk processes. However, its performance is usually very poor for high performance circuits. The TFT structure consists of a large number of small size crystallized silicon grains. It is desirable to have a very large grain size so that a single transistor can lie entirely on a single grain. In this case, the TFT becomes an SOI MOSFET. Metal-induced-lateral-crystallization (MILC) has been used to enlarge the polysilicon TFT grain size. However, due to the limitation in low temperature formation, the grain size is still not desirable. With the use of high temperature annealing at a temperature above 900/spl deg/C after MILC, we found that much larger crystals of the order of 10 /spl mu/m can be formed. For the advanced technology which comes with device scaling, it is possible to individually recrystallize the active region of each transistor, giving TFTs (as formed) with SOI MOSFET performance.
{"title":"SOI formation from amorphous silicon by metal-induced-lateral-crystallization (MILC) and subsequent high temperature annealing","authors":"S. Jagar, M. Chan, K. C. Poon, Hongmei Wang, M. Qin, S. Shivani, P. Ko, Yangyuan Wang","doi":"10.1109/SOI.1999.819878","DOIUrl":"https://doi.org/10.1109/SOI.1999.819878","url":null,"abstract":"In current SOI technology, the formation of circuit elements requires the use of some special starting material like SIMOX, BESOI or Unibond wafers, which usually cannot be made in-house. As such, it leads to a divergence between SOI technology and bulk technology, and there are debates on justification on the initial material cost. TFTs formed in polysilicon have similar structures to SOI, and have been used as the load element in SRAM. Comparing TFT and SOI transistors, the TFT is easier to fabricate in term of starting material and compatibility with bulk processes. However, its performance is usually very poor for high performance circuits. The TFT structure consists of a large number of small size crystallized silicon grains. It is desirable to have a very large grain size so that a single transistor can lie entirely on a single grain. In this case, the TFT becomes an SOI MOSFET. Metal-induced-lateral-crystallization (MILC) has been used to enlarge the polysilicon TFT grain size. However, due to the limitation in low temperature formation, the grain size is still not desirable. With the use of high temperature annealing at a temperature above 900/spl deg/C after MILC, we found that much larger crystals of the order of 10 /spl mu/m can be formed. For the advanced technology which comes with device scaling, it is possible to individually recrystallize the active region of each transistor, giving TFTs (as formed) with SOI MOSFET performance.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117170674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Ferlet-Cavrois, A. Bracale, N. Fel, O. Musseau, C. Raynaud, O. Faynot, J. Pelloie
The DTMOS architecture is particularly suited to very low supply voltage applications (0.5-0.6 V) (Colinge, 1987; Matloubian, 1993; Assaderaghi et al., 1994; Pelloie et al., 1999). This paper presents the high frequency behavior of DTMOS devices processed with a partially depleted 0.25 /spl mu/m SOI technology (Wilson et al., 1997; Lagnado and de la Houssaye, 1997; Cable, 1997; Ferlet-Cavrois et al., 1998; Tanaka et al., 1997). The paper compares DTMOS to floating body and grounded body MOS transistors, and shows the advantage of SOI DTMOS for very low power portable telecommunication systems.
DTMOS架构特别适合非常低的电源电压应用(0.5-0.6 V) (Colinge, 1987;Matloubian, 1993;Assaderaghi et al.， 1994;Pelloie et al.， 1999)。本文介绍了部分耗尽0.25 /spl mu/m SOI技术处理的DTMOS器件的高频行为(Wilson et al.， 1997;Lagnado and de la Houssaye, 1997;电缆,1997;Ferlet-Cavrois等人，1998;Tanaka et al.， 1997)。通过与浮体和接地体MOS晶体管的比较，说明了SOI型DTMOS在极低功耗便携式通信系统中的优势。
{"title":"High frequency characterization of SOI dynamic threshold voltage MOS (DTMOS) transistors","authors":"V. Ferlet-Cavrois, A. Bracale, N. Fel, O. Musseau, C. Raynaud, O. Faynot, J. Pelloie","doi":"10.1109/SOI.1999.819840","DOIUrl":"https://doi.org/10.1109/SOI.1999.819840","url":null,"abstract":"The DTMOS architecture is particularly suited to very low supply voltage applications (0.5-0.6 V) (Colinge, 1987; Matloubian, 1993; Assaderaghi et al., 1994; Pelloie et al., 1999). This paper presents the high frequency behavior of DTMOS devices processed with a partially depleted 0.25 /spl mu/m SOI technology (Wilson et al., 1997; Lagnado and de la Houssaye, 1997; Cable, 1997; Ferlet-Cavrois et al., 1998; Tanaka et al., 1997). The paper compares DTMOS to floating body and grounded body MOS transistors, and shows the advantage of SOI DTMOS for very low power portable telecommunication systems.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126977126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
IOS (insulator-on-semiconductor) has emerged as a new type of materials combination for system-on-a chip preparation. For high frequency mobile communication systems, a thin layer of piezoelectric or ferroelectric oxide crystal such as quartz, LiTaO/sub 3/ or LiNbO/sub 3/ on Si is required for high Q-factor and low temperature coefficient SAW filters, surface resonators and oscillators. Combining these materials with Si can lead to the integration of electronic and acoustic devices on the same chip. Voltage-controlled and temperature-compensated high Q-factor crystal oscillators and resonators can thus be realized. The integration of high performance GaAs photodetectors with LiNbO/sub 3/ waveguides makes integrated optical circuits possible. By preparing a thin layer of single crystalline transition metal oxides such as magnetic garnets on Si or on III-V semiconductors, stabilized laser diodes can be realized due to the availability of on-chip thin film optical isolators and circulators. Layer transfer by wafer bonding and H-induced layer splitting provides a manufacturable technology for IOS preparation. In this study, we report feasibility study results for IOS preparation with an insulator layer of many single crystalline insulators such as c-sapphire, LaAlO/sub 2/, PLZT and LiNbO/sub 3/. We have demonstrated that surface blistering and layer splitting of these materials is possible if H implantation is performed at wafer temperatures within the specific temperature range for each material.
半导体绝缘体(insulator-on-semiconductor，简称IOS)作为一种新型的材料组合已经出现在片上系统的制备中。对于高频移动通信系统，高q因子和低温系数SAW滤波器、表面谐振器和振荡器需要一层薄的压电或铁电氧化物晶体，如石英、LiTaO/sub 3/或LiNbO/sub 3/ on Si。将这些材料与硅结合可以将电子和声学器件集成在同一芯片上。因此可以实现电压控制和温度补偿的高q因子晶体振荡器和谐振器。高性能砷化镓光电探测器与LiNbO/sub - 3/波导的集成使集成光学电路成为可能。通过在Si或III-V半导体上制备单晶过渡金属氧化物(如磁性石榴石)的薄层，由于片上薄膜光学隔离器和循环器的可用性，可以实现稳定的激光二极管。通过晶圆键合和h诱导层分裂的层转移为制备IOS提供了一种可制造的技术。在本研究中，我们报告了c-蓝宝石、LaAlO/sub 2/、PLZT和LiNbO/sub 3/等多种单晶绝缘体的绝缘层制备IOS的可行性研究结果。我们已经证明，如果在每种材料的特定温度范围内的晶圆温度下进行H注入，这些材料的表面起泡和层分裂是可能的。
{"title":"IOS-a new type of materials combination for system-on-a chip preparation","authors":"Q. Tong, L. Huang, Y. Chao, Q. Gang, U. Goesele","doi":"10.1109/SOI.1999.819874","DOIUrl":"https://doi.org/10.1109/SOI.1999.819874","url":null,"abstract":"IOS (insulator-on-semiconductor) has emerged as a new type of materials combination for system-on-a chip preparation. For high frequency mobile communication systems, a thin layer of piezoelectric or ferroelectric oxide crystal such as quartz, LiTaO/sub 3/ or LiNbO/sub 3/ on Si is required for high Q-factor and low temperature coefficient SAW filters, surface resonators and oscillators. Combining these materials with Si can lead to the integration of electronic and acoustic devices on the same chip. Voltage-controlled and temperature-compensated high Q-factor crystal oscillators and resonators can thus be realized. The integration of high performance GaAs photodetectors with LiNbO/sub 3/ waveguides makes integrated optical circuits possible. By preparing a thin layer of single crystalline transition metal oxides such as magnetic garnets on Si or on III-V semiconductors, stabilized laser diodes can be realized due to the availability of on-chip thin film optical isolators and circulators. Layer transfer by wafer bonding and H-induced layer splitting provides a manufacturable technology for IOS preparation. In this study, we report feasibility study results for IOS preparation with an insulator layer of many single crystalline insulators such as c-sapphire, LaAlO/sub 2/, PLZT and LiNbO/sub 3/. We have demonstrated that surface blistering and layer splitting of these materials is possible if H implantation is performed at wafer temperatures within the specific temperature range for each material.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126560686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
CMOS is competing with bipolar and GaAs in the radio-frequency integrated circuits (RFIC) arena for wireless communications. SOI technology earns more credit for the Si-based CMOS family due to its improved RF performance. SOI promises better device characteristics than bulk technology and reduces substrate noise coupling. In addition, the buried oxide improves the quality (Q) factor of the on-chip planar inductors. So far, only the results of single-transistor low-noise amplifiers (LNA) based on SOI/SOS technology have been reported (Johnson et al., 1998; Harada et al., 1998). This paper reports the first SOI LNA with a cascode topology which offers performance advantages over other circuit configurations. The LNA circuit, operating at 1.8 GHz, can be used as a front-end amplifier for personal communications services (PCS) systems, which are allocated within the 1.7 GHz and 1.9 GHz band.
在无线通信的射频集成电路(RFIC)领域，CMOS正与双极和GaAs展开竞争。SOI技术由于其改进的射频性能而在基于si的CMOS系列中赢得了更多的赞誉。SOI保证了比本体技术更好的器件特性，并减少了衬底噪声耦合。此外，埋地氧化物提高了片上平面电感的质量(Q)因子。到目前为止，只报道了基于SOI/SOS技术的单晶体管低噪声放大器(LNA)的结果(Johnson et al.， 1998;Harada et al.， 1998)。本文报道了第一个具有级联码拓扑的SOI LNA，它比其他电路配置提供了性能优势。LNA电路工作在1.8 GHz，可以用作个人通信服务(PCS)系统的前端放大器，分配在1.7 GHz和1.9 GHz频段内。
{"title":"1.5-V 1.8-GHz SOI low noise amplifiers for PCS receivers","authors":"W. Jin, Philip C. H. Chan, C. Hai","doi":"10.1109/SOI.1999.819836","DOIUrl":"https://doi.org/10.1109/SOI.1999.819836","url":null,"abstract":"CMOS is competing with bipolar and GaAs in the radio-frequency integrated circuits (RFIC) arena for wireless communications. SOI technology earns more credit for the Si-based CMOS family due to its improved RF performance. SOI promises better device characteristics than bulk technology and reduces substrate noise coupling. In addition, the buried oxide improves the quality (Q) factor of the on-chip planar inductors. So far, only the results of single-transistor low-noise amplifiers (LNA) based on SOI/SOS technology have been reported (Johnson et al., 1998; Harada et al., 1998). This paper reports the first SOI LNA with a cascode topology which offers performance advantages over other circuit configurations. The LNA circuit, operating at 1.8 GHz, can be used as a front-end amplifier for personal communications services (PCS) systems, which are allocated within the 1.7 GHz and 1.9 GHz band.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130635682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Continued device scaling in bulk MOSFETs beyond the sub-100 nm regime may require transition to advanced SOI technologies. It has been reported that the thin film fully-depleted (FD) SOI structure is promising for low voltage, high speed applications due to the improved short channel tolerance and lack of body effect (Wong et al, 1998). However, current techniques to obtain bulk-like quality material for very thin SOI have proved difficult to manufacture in terms of cost, material defects and SOI thickness variation across the wafer. The SOI thickness variation results in V/sub T/ variation, which is a major drawback in FD-SOI technology. Selective epitaxial growth (SEG) offers an alternative way of obtaining a device quality SOI material when it is grown laterally (epitaxial lateral overgrowth; ELO) over the field SiO/sub 2/. The local area chemical mechanical polishing (CMP) etch stop gives good controlled thickness of uniform thin SOI films where FD-SOI MOSFETs can be fabricated (Pae et al, 1998 and 1999). One distinctive advantage of the ELO technique is the formation of very thin bottom gate SiO/sub 2/ for double gate MOSFETs (Wong et al. 1997; Denton et al. 1995), which is difficult to obtain in other SOI technologies. This enables improved dynamic V/sub T/ control using low back gate bias. We report here the most recent results of deep-submicron FD-SOI P-MOSFETs fabricated in two different layers of SOI islands created entirely by ELO. Device characteristics and dynamic V/sub T/ shifting are discussed.
在超过亚100纳米范围的批量mosfet中，器件的持续缩放可能需要过渡到先进的SOI技术。据报道，薄膜全耗尽(FD) SOI结构由于改善了短通道容限和缺乏体效应，在低电压、高速应用中很有前景(Wong et al, 1998)。然而，从成本、材料缺陷和晶圆上的SOI厚度变化等方面来看，目前的技术很难制造出非常薄的SOI材料。SOI厚度的变化会导致V/sub / T的变化，这是FD-SOI技术的一个主要缺点。选择性外延生长(SEG)提供了一种在横向生长时获得器件质量SOI材料的替代方法(外延横向过度生长;ELO)在现场SiO/ sub2 /上。局部化学机械抛光(CMP)蚀刻停止可以很好地控制均匀的SOI薄膜厚度，从而可以制造FD-SOI mosfet (Pae等人，1998年和1999年)。ELO技术的一个显著优势是为双栅mosfet形成非常薄的底栅SiO/sub 2/ (Wong et al. 1997;Denton et al. 1995)，这在其他SOI技术中很难获得。这使得使用低后门偏置改进的动态V/sub / T控制成为可能。我们在这里报告了深亚微米FD-SOI p- mosfet的最新结果，这些fds -SOI p- mosfet是在完全由ELO创建的两个不同的SOI岛层中制造的。讨论了器件特性和动态V/sub / T/换档。
{"title":"Multi-layer SOI island technology by selective epitaxial growth for single-gate and double-gate MOSFETs","authors":"S. Pae, J. Denton, G. Neudeck","doi":"10.1109/SOI.1999.819876","DOIUrl":"https://doi.org/10.1109/SOI.1999.819876","url":null,"abstract":"Continued device scaling in bulk MOSFETs beyond the sub-100 nm regime may require transition to advanced SOI technologies. It has been reported that the thin film fully-depleted (FD) SOI structure is promising for low voltage, high speed applications due to the improved short channel tolerance and lack of body effect (Wong et al, 1998). However, current techniques to obtain bulk-like quality material for very thin SOI have proved difficult to manufacture in terms of cost, material defects and SOI thickness variation across the wafer. The SOI thickness variation results in V/sub T/ variation, which is a major drawback in FD-SOI technology. Selective epitaxial growth (SEG) offers an alternative way of obtaining a device quality SOI material when it is grown laterally (epitaxial lateral overgrowth; ELO) over the field SiO/sub 2/. The local area chemical mechanical polishing (CMP) etch stop gives good controlled thickness of uniform thin SOI films where FD-SOI MOSFETs can be fabricated (Pae et al, 1998 and 1999). One distinctive advantage of the ELO technique is the formation of very thin bottom gate SiO/sub 2/ for double gate MOSFETs (Wong et al. 1997; Denton et al. 1995), which is difficult to obtain in other SOI technologies. This enables improved dynamic V/sub T/ control using low back gate bias. We report here the most recent results of deep-submicron FD-SOI P-MOSFETs fabricated in two different layers of SOI islands created entirely by ELO. Device characteristics and dynamic V/sub T/ shifting are discussed.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134104838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As CMOS device dimensions are scaled toward 0.1 /spl mu/m, formation of controllable thin silicide is critical. For conventional high temperature Ti salicidation, however, it is difficult to control silicide formation due to a fast reaction rate between Ti metal and silicon. Co silicide can achieve low sheet resistance for fine polysilicon lines and source/drain (S/D) regions, but the diode leakage is still a major problem with shallower junctions and SOI for deep sub-micron CMOS (Hsiao et al., 1998). In the past, a low temperature silicide technology has been proposed and applied to 100-nm SOI MOSFETs (Goto et al., 1995). In this paper, Ge/sup +/ pre-amorphized Ti salicide for sub-0.1 /spl mu/m gate length CMOS is investigated in detail and is used to demonstrate 0.1 /spl mu/m CMOS on an ultra thin SOI film of 35 nm for the first time. We focused on the influence of Ge/sup +/ pre-amorphization energy, Ti metal thickness and substrate doping on Ti silicidation kinetics, silicide depth and sheet resistance on bulk and fine polysilicon lines ranging from 1.0 to 0.1 /spl mu/m. Our results showed an effective control of silicide depth in the case of Ge/sup +/-implanted samples. A small grain size averaging 80 nm was observed on fine gate lines and polysilicon lines down to 0.1 m were shown to have good resistivity. The effects of metal thickness and doping species were eliminated. The excellent device performance shows this technology is highly suitable for future 0.1 /spl mu/m SOI MOSFETs and deep sub-micron bulk CMOS devices.
随着CMOS器件尺寸向0.1 /spl mu/m的方向发展，形成可控的薄硅化物至关重要。然而，对于传统的高温钛盐化，由于钛金属与硅之间的反应速度快，难以控制硅化物的形成。硅化钴可以在精细多晶硅线和源/漏极(S/D)区域实现低片电阻，但二极管泄漏仍然是深亚微米CMOS的浅结和SOI的主要问题(Hsiao et al.， 1998)。在过去，低温硅化物技术已被提出并应用于100纳米SOI mosfet (Goto et al.， 1995)。本文对栅极长度低于0.1 /spl μ m的CMOS中Ge/sup +/预非晶化Ti盐化物进行了详细的研究，并首次在35 nm的超薄SOI薄膜上演示了0.1 /spl μ m的CMOS。我们重点研究了Ge/sup +/预非晶化能、钛金属厚度和衬底掺杂对块状和细晶多晶硅线上钛硅化动力学、硅化物深度和薄片电阻的影响，范围从1.0到0.1 /spl mu/m。我们的研究结果表明，在Ge/sup +/-注入样品中，硅化物的深度得到了有效的控制。在细栅线上观察到平均80 nm的小晶粒尺寸，0.1 m以下的多晶硅线具有良好的电阻率。消除了金属厚度和掺杂种类的影响。优异的器件性能表明，该技术非常适合未来的0.1 /spl mu/m SOI mosfet和深亚微米大块CMOS器件。
{"title":"Advanced silicide for sub-0.18 /spl mu/m CMOS on ultra-thin (35 /spl mu/m) SOI","authors":"L. Ren, B. Cheng, J. Woo","doi":"10.1109/SOI.1999.819866","DOIUrl":"https://doi.org/10.1109/SOI.1999.819866","url":null,"abstract":"As CMOS device dimensions are scaled toward 0.1 /spl mu/m, formation of controllable thin silicide is critical. For conventional high temperature Ti salicidation, however, it is difficult to control silicide formation due to a fast reaction rate between Ti metal and silicon. Co silicide can achieve low sheet resistance for fine polysilicon lines and source/drain (S/D) regions, but the diode leakage is still a major problem with shallower junctions and SOI for deep sub-micron CMOS (Hsiao et al., 1998). In the past, a low temperature silicide technology has been proposed and applied to 100-nm SOI MOSFETs (Goto et al., 1995). In this paper, Ge/sup +/ pre-amorphized Ti salicide for sub-0.1 /spl mu/m gate length CMOS is investigated in detail and is used to demonstrate 0.1 /spl mu/m CMOS on an ultra thin SOI film of 35 nm for the first time. We focused on the influence of Ge/sup +/ pre-amorphization energy, Ti metal thickness and substrate doping on Ti silicidation kinetics, silicide depth and sheet resistance on bulk and fine polysilicon lines ranging from 1.0 to 0.1 /spl mu/m. Our results showed an effective control of silicide depth in the case of Ge/sup +/-implanted samples. A small grain size averaging 80 nm was observed on fine gate lines and polysilicon lines down to 0.1 m were shown to have good resistivity. The effects of metal thickness and doping species were eliminated. The excellent device performance shows this technology is highly suitable for future 0.1 /spl mu/m SOI MOSFETs and deep sub-micron bulk CMOS devices.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116490564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High-quality ITOX-SIMOX wafers have been used for the fabrication of 0.25 /spl mu/m fully depleted CMOS SIMOX LSIs with a 50 nm-thick active top Si layer (Ino et al, 1996). As the channel length gets much smaller, the top Si and the gate oxide must be thinner to suppress the short-channel effect (Su et al, 1993). It is very important to confirm the integrity of the gate oxide on a thinner top Si layer since the top Si adjacent to the top Si-buried oxide interface has a high density of small stacking fault complexes (SFC) (Jablonski et al, 1996). There have been few reports on this subject. Accordingly, we fabricated MOS diodes in ITOX-SIMOX wafers with a thinner top Si layer and investigated the electrical characteristics of the gate oxide grown on the wafers. The obtained results reveal that the gate oxide quality is high, and is comparable to the quality of the gate oxide of bulk wafers.
高质量的ITOX-SIMOX晶圆已被用于制造0.25 /spl μ l /m完全耗尽的CMOS SIMOX lsi，具有50 nm厚的有源顶部硅层(Ino等，1996)。由于沟道长度越来越小，顶部Si和栅极氧化物必须更薄以抑制短沟道效应(Su et al, 1993)。确认较薄的顶部Si层上栅极氧化物的完整性是非常重要的，因为靠近顶部Si埋氧化物界面的顶部Si具有高密度的小层错复合体(SFC) (Jablonski等，1996)。关于这个问题的报道很少。因此，我们在顶部硅层较薄的ITOX-SIMOX晶片上制备了MOS二极管，并研究了晶片上生长的栅氧化物的电学特性。结果表明，所制备的栅极氧化物质量较高，可与大块晶圆的栅极氧化物质量相媲美。
{"title":"Integrity of the gate oxide on the thin top Si layer in ITOX-SIMOX wafers","authors":"S. Nakashima, J. Kodate","doi":"10.1109/SOI.1999.819881","DOIUrl":"https://doi.org/10.1109/SOI.1999.819881","url":null,"abstract":"High-quality ITOX-SIMOX wafers have been used for the fabrication of 0.25 /spl mu/m fully depleted CMOS SIMOX LSIs with a 50 nm-thick active top Si layer (Ino et al, 1996). As the channel length gets much smaller, the top Si and the gate oxide must be thinner to suppress the short-channel effect (Su et al, 1993). It is very important to confirm the integrity of the gate oxide on a thinner top Si layer since the top Si adjacent to the top Si-buried oxide interface has a high density of small stacking fault complexes (SFC) (Jablonski et al, 1996). There have been few reports on this subject. Accordingly, we fabricated MOS diodes in ITOX-SIMOX wafers with a thinner top Si layer and investigated the electrical characteristics of the gate oxide grown on the wafers. The obtained results reveal that the gate oxide quality is high, and is comparable to the quality of the gate oxide of bulk wafers.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122306219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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