Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486232
M. Fukui, N. Shinomiya, T. Akino
We propose a new layout synthesis with 2 dimensional transistor arrangement and a spontaneous process of 2 dimensional compaction and local re routing. The compaction enables jumping over objects, minimizing the number of contacts for wiring. We applied the layout synthesis to actual cell design and obtained comparable results to hand crafted design.
{"title":"A new layout synthesis for leaf cell design","authors":"M. Fukui, N. Shinomiya, T. Akino","doi":"10.1109/ASPDAC.1995.486232","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486232","url":null,"abstract":"We propose a new layout synthesis with 2 dimensional transistor arrangement and a spontaneous process of 2 dimensional compaction and local re routing. The compaction enables jumping over objects, minimizing the number of contacts for wiring. We applied the layout synthesis to actual cell design and obtained comparable results to hand crafted design.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130948603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486248
M. Kondo, H. Onodera, K. Tamaru
A model-adaptable parameter extraction system is developed to catch up with rapid development of new advanced MOSFET models. The model-adaptability relies on two techniques; a model-adaptable initial value estimation method and a design environment that stores and reuses extraction procedures. The system makes it easy to develop an extraction procedure for a new MOSFET model through the reuse of an existing procedure for a previous model. We have verified that the system can accommodate major SPICE models including Level2-3 and BSIM1-3.
{"title":"A model-adaptable MOSFET parameter extraction system","authors":"M. Kondo, H. Onodera, K. Tamaru","doi":"10.1109/ASPDAC.1995.486248","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486248","url":null,"abstract":"A model-adaptable parameter extraction system is developed to catch up with rapid development of new advanced MOSFET models. The model-adaptability relies on two techniques; a model-adaptable initial value estimation method and a design environment that stores and reuses extraction procedures. The system makes it easy to develop an extraction procedure for a new MOSFET model through the reuse of an existing procedure for a previous model. We have verified that the system can accommodate major SPICE models including Level2-3 and BSIM1-3.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133946056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486351
K. Wada, S. Takagi, Z. Czarnul, N. Fujii
This paper proposes a design automation for filters using integrators. This is based on a predistortion without knowledge of a filter topology. The predistortion requires an integrator having the same structure, the same-value elements and an electrically controllable unity-gain frequency, and compensates for the deviation of frequency characteristics due to an excess phase shift of an integrator. The effectiveness of the proposed method is demonstrated through SPICE simulations. An algorithm for a filter design automation is also discussed.
{"title":"Design automation for integrated continuous-time filters using integrators","authors":"K. Wada, S. Takagi, Z. Czarnul, N. Fujii","doi":"10.1109/ASPDAC.1995.486351","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486351","url":null,"abstract":"This paper proposes a design automation for filters using integrators. This is based on a predistortion without knowledge of a filter topology. The predistortion requires an integrator having the same structure, the same-value elements and an electrically controllable unity-gain frequency, and compensates for the deviation of frequency characteristics due to an excess phase shift of an integrator. The effectiveness of the proposed method is demonstrated through SPICE simulations. An algorithm for a filter design automation is also discussed.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"300 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122776483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486196
J. Tual, M. Thill, C. Bernard, H. Nguyen, F. Mottini, M. Moreau, P. Vallet
With the introduction of the high range version of the DPS7000 mainframe family, Bull is providing a processor which integrates the DPS7000 CPU and first level of cache on one VLSI chip containing 4.7M transistors and using a 0.5 pm, 3Mlayers CMOS technology. This enhanced CPU has been designed to provide a high integration, high performance and low cost systems. Up to 24 such processors can be integrated in a single system, enabling performance levels in the range of 850 TPC-A (Oracle) with about 12 000 simultaneously active connections. The design methodology involved massive use of formal verification and symbolic layout techniques, enabling to reach first pass right silicon on several foundries. An architectural overview of the CPU with emphasis on several original aspects of the design aspects (synthesis, verification, symbolic layout) are discussed in this paper.
{"title":"Auriga2: a 4.7 million-transistor CISC microprocessor","authors":"J. Tual, M. Thill, C. Bernard, H. Nguyen, F. Mottini, M. Moreau, P. Vallet","doi":"10.1109/ASPDAC.1995.486196","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486196","url":null,"abstract":"With the introduction of the high range version of the DPS7000 mainframe family, Bull is providing a processor which integrates the DPS7000 CPU and first level of cache on one VLSI chip containing 4.7M transistors and using a 0.5 pm, 3Mlayers CMOS technology. This enhanced CPU has been designed to provide a high integration, high performance and low cost systems. Up to 24 such processors can be integrated in a single system, enabling performance levels in the range of 850 TPC-A (Oracle) with about 12 000 simultaneously active connections. The design methodology involved massive use of formal verification and symbolic layout techniques, enabling to reach first pass right silicon on several foundries. An architectural overview of the CPU with emphasis on several original aspects of the design aspects (synthesis, verification, symbolic layout) are discussed in this paper.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115926714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486202
Shih-Hsu Huang, Ta-Yung Liu, Y. Hsu, Yen-Jen Oyang
In behavior synthesis, an improper resource sharing may result in a circuit containing false loops which is non-simulatable or non-timing-analyzable. Previous approaches solve this problem during the datapath allocation phase. To build a false loop free circuit, they may have to allocate additional functional units other than those defined in the resource constraints. In this paper, we present an approach to solve the problem during the scheduling phase. Our scheduling algorithm finds a schedule which guarantees to have a false loop free circuit mapping under the given resource constraints. Experiments show the proposed approach finds false loop free schedule for most of the examples without introducing extra control steps.
{"title":"Synthesis of false loop free circuits","authors":"Shih-Hsu Huang, Ta-Yung Liu, Y. Hsu, Yen-Jen Oyang","doi":"10.1109/ASPDAC.1995.486202","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486202","url":null,"abstract":"In behavior synthesis, an improper resource sharing may result in a circuit containing false loops which is non-simulatable or non-timing-analyzable. Previous approaches solve this problem during the datapath allocation phase. To build a false loop free circuit, they may have to allocate additional functional units other than those defined in the resource constraints. In this paper, we present an approach to solve the problem during the scheduling phase. Our scheduling algorithm finds a schedule which guarantees to have a false loop free circuit mapping under the given resource constraints. Experiments show the proposed approach finds false loop free schedule for most of the examples without introducing extra control steps.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127274857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486249
P. Lindgren
We investigate the properties of the Ordered Ternary Decision Diagram (OTDD) in order to develop an efficient general OTDD package. The OTDD is a three-branched three-terminal diagram based on Kleenean strong ternary logic. The OTDD can represent functions having nontrivial don't-care sets in a single diagram and is capable of provably correct evaluation in the presence of unknown input values. We propose a number of improvements to both OTDD computational methods and data structures. Furthermore we introduce the purged form OTDD which unifies the abbreviated and full form OTDD into a single diagram. A package exploiting these OTDD specific properties is presented and we show the computational advantages of this improved package for LGSynth93 standard benchmarks.
{"title":"Improved computational methods and lazy evaluation of the Ordered Ternary Decision Diagram","authors":"P. Lindgren","doi":"10.1109/ASPDAC.1995.486249","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486249","url":null,"abstract":"We investigate the properties of the Ordered Ternary Decision Diagram (OTDD) in order to develop an efficient general OTDD package. The OTDD is a three-branched three-terminal diagram based on Kleenean strong ternary logic. The OTDD can represent functions having nontrivial don't-care sets in a single diagram and is capable of provably correct evaluation in the presence of unknown input values. We propose a number of improvements to both OTDD computational methods and data structures. Furthermore we introduce the purged form OTDD which unifies the abbreviated and full form OTDD into a single diagram. A package exploiting these OTDD specific properties is presented and we show the computational advantages of this improved package for LGSynth93 standard benchmarks.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128358032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486206
N. Binh, M. Imai, A. Shiomi, N. Hikichi
Proposes a new method to design an optimal pipelined instruction set processor using a formal HW/SW codesign methodology. First, a HW/SW partitioning algorithm for selecting an optimal pipelined architecture is introduced briefly. Then, an adaptive database approach is presented that enables to enhance the optimality of the design through very accurate estimation of the performance of a pipelined ASIP in HW/SW partitioning. The experimental results show that the proposed methods are effective and efficient.
{"title":"A hardware/software codesign method for pipelined instruction set processor using adaptive database","authors":"N. Binh, M. Imai, A. Shiomi, N. Hikichi","doi":"10.1109/ASPDAC.1995.486206","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486206","url":null,"abstract":"Proposes a new method to design an optimal pipelined instruction set processor using a formal HW/SW codesign methodology. First, a HW/SW partitioning algorithm for selecting an optimal pipelined architecture is introduced briefly. Then, an adaptive database approach is presented that enables to enhance the optimality of the design through very accurate estimation of the performance of a pipelined ASIP in HW/SW partitioning. The experimental results show that the proposed methods are effective and efficient.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129198520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486204
C. Shi, J. Brzozowski
A simple mathematical framework, called cluster-cover, is established for several VLSI optimisation problems including logic minimization, constrained encoding, multi-layer topological planar routing, application timing assignment for delay-fault testing, and minimization of monitoring logic for BIST enhancement. Two paradigms, prime covering and greedy peeling, are presented for developing both exact and heuristic algorithms. The paradigms capture generally applicable ingredients from previously developed algorithms for individual applications. This makes it possible to re-use established techniques in new problems, and provide new insights into existing problems. The paradigms are simple enough to be amenable to theoretical analysis. Bounds on the performance of greedy peeling are derived; these bounds are applicable to many published heuristics which previously could be evaluated only by benchmarks.
{"title":"A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems","authors":"C. Shi, J. Brzozowski","doi":"10.1109/ASPDAC.1995.486204","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486204","url":null,"abstract":"A simple mathematical framework, called cluster-cover, is established for several VLSI optimisation problems including logic minimization, constrained encoding, multi-layer topological planar routing, application timing assignment for delay-fault testing, and minimization of monitoring logic for BIST enhancement. Two paradigms, prime covering and greedy peeling, are presented for developing both exact and heuristic algorithms. The paradigms capture generally applicable ingredients from previously developed algorithms for individual applications. This makes it possible to re-use established techniques in new problems, and provide new insights into existing problems. The paradigms are simple enough to be amenable to theoretical analysis. Bounds on the performance of greedy peeling are derived; these bounds are applicable to many published heuristics which previously could be evaluated only by benchmarks.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121892009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-23DOI: 10.1109/ASPDAC.1995.486350
K. Okada, S. Morikawa, I. Shirakawa, Sumitaka Takeuchi
A high performance design methodology is described for a multiplier to be used for digital video transmission. The key factor for such a multiplier is to operate at the speed of 30-100 MHz but with the precision of 8-10 bits, since it is intended for FIR filtering of digital video data. In terms of implementing an FIR filter with more than ten taps, the same number of multipliers are required to be integrated. Moreover, for the preloadability of coefficients to the filter, each coefficient can be treated as a constant during the filtering operation. Motivated by these requirements and functionalities, a novel multiplier architecture is described, which is to be synthesized with the use of a high level synthesis tool PARTHENON in conjunction with manually designed macroblocks. Design results of the multiplier are also shown.
{"title":"A design of high-performance multiplier for digital video transmission","authors":"K. Okada, S. Morikawa, I. Shirakawa, Sumitaka Takeuchi","doi":"10.1109/ASPDAC.1995.486350","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486350","url":null,"abstract":"A high performance design methodology is described for a multiplier to be used for digital video transmission. The key factor for such a multiplier is to operate at the speed of 30-100 MHz but with the precision of 8-10 bits, since it is intended for FIR filtering of digital video data. In terms of implementing an FIR filter with more than ten taps, the same number of multipliers are required to be integrated. Moreover, for the preloadability of coefficients to the filter, each coefficient can be treated as a constant during the filtering operation. Motivated by these requirements and functionalities, a novel multiplier architecture is described, which is to be synthesized with the use of a high level synthesis tool PARTHENON in conjunction with manually designed macroblocks. Design results of the multiplier are also shown.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132997054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ASPDAC.1995.486201
P. Jha, S. Parameswaran, N. Dutt
Describes a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire delays of designs created by a high level synthesis system, and then finding an optimal clockwidth, we resynthesize the controller to improve performance without altering the datapath. Reclocking is versatile and can be applied not only for wire delay consideration, but also for bit-width migration, library migration and for feature size migration supporting the philosophy of design reuse. Experimental results show that with reclocking, the performance of the input designs can be improved by as much as 34%.
{"title":"Reclocking for high level synthesis","authors":"P. Jha, S. Parameswaran, N. Dutt","doi":"10.1109/ASPDAC.1995.486201","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486201","url":null,"abstract":"Describes a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire delays of designs created by a high level synthesis system, and then finding an optimal clockwidth, we resynthesize the controller to improve performance without altering the datapath. Reclocking is versatile and can be applied not only for wire delay consideration, but also for bit-width migration, library migration and for feature size migration supporting the philosophy of design reuse. Experimental results show that with reclocking, the performance of the input designs can be improved by as much as 34%.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129606158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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