Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486214
S. M. Sait, H. Youssef, S. Tanvir, M. Benten
In this paper we present a timing-influenced floorplanner for general cell IC design. The floorplanner works in two phases. In the first phase we restrict the modules to be rigid and the floorplan to be slicing. The second phase of floorplanner allows modification to the aspect ratios of individual modules to further reduce the area of the overall bounding box. The first phase is implemented using genetic algorithm while in the second phase we adopt a constraint graph based approach. Experimental results are also presented.
{"title":"Timing influenced general-cell genetic floorplanner","authors":"S. M. Sait, H. Youssef, S. Tanvir, M. Benten","doi":"10.1109/ASPDAC.1995.486214","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486214","url":null,"abstract":"In this paper we present a timing-influenced floorplanner for general cell IC design. The floorplanner works in two phases. In the first phase we restrict the modules to be rigid and the floorplan to be slicing. The second phase of floorplanner allows modification to the aspect ratios of individual modules to further reduce the area of the overall bounding box. The first phase is implemented using genetic algorithm while in the second phase we adopt a constraint graph based approach. Experimental results are also presented.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126701182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486227
T. Bogue, H. Jürgensen, M. Gössel
In this paper, a new modified BIST structure is investigated. The output of the MISA is monitored during the test by an error detection circuit which is composed of two simple cover circuits. To simplify the cover construction, the cover circuits are randomly chosen to be active for some of the outputs of the MISA. Thus, a time-consuming fault simulation can be completely avoided. The overhead for the cover circuits is determined for several of the ISCAS'85 and Berkeley benchmark circuits. These simulation experiments show that a significant reduction of the aliasing probability can be achieved, confirming and far surpassing theoretically predicted improvements. Moreover, this improvement can be achieved at a nearly negligible cost in additional hardware.
{"title":"BIST with negligible aliasing through random cover circuits","authors":"T. Bogue, H. Jürgensen, M. Gössel","doi":"10.1109/ASPDAC.1995.486227","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486227","url":null,"abstract":"In this paper, a new modified BIST structure is investigated. The output of the MISA is monitored during the test by an error detection circuit which is composed of two simple cover circuits. To simplify the cover construction, the cover circuits are randomly chosen to be active for some of the outputs of the MISA. Thus, a time-consuming fault simulation can be completely avoided. The overhead for the cover circuits is determined for several of the ISCAS'85 and Berkeley benchmark circuits. These simulation experiments show that a significant reduction of the aliasing probability can be achieved, confirming and far surpassing theoretically predicted improvements. Moreover, this improvement can be achieved at a nearly negligible cost in additional hardware.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124635510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486234
Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin
A heuristic algorithm for a given topology of a multiple source and multiple sink bus to reduce the signal delay time is proposed. The algorithm minimizes the delay by inserting buffers into the candidate locations and sizing the buffers. Experiments show up to 7.2 %, 20.7 %, and 29.6 % improvement in delay for 2.0, 0.5, and 0.3 micron technologies, respectively.
{"title":"Performance driven multiple-source bus synthesis using buffer insertion","authors":"Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin","doi":"10.1109/ASPDAC.1995.486234","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486234","url":null,"abstract":"A heuristic algorithm for a given topology of a multiple source and multiple sink bus to reduce the signal delay time is proposed. The algorithm minimizes the delay by inserting buffers into the candidate locations and sizing the buffers. Experiments show up to 7.2 %, 20.7 %, and 29.6 % improvement in delay for 2.0, 0.5, and 0.3 micron technologies, respectively.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"80 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132227912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486216
M. Escalante, N. Dimopoulos
During the design of microprocessor-based systems, once the system architecture has been decided and the major components (processors, memories, to devices) have been selected from a component library, it is necessary to design interface logic to integrate the system. Such an interface design can be carried out based on the protocols used by the components. This paper addresses the problem of determining the feasibility of a design prior to synthesis. A design is called feasible if it achieves the desired functionality and satisfies the given environmental constraints. Because timing is an important aspect of a correct design, protocols are described using timed signal transition graphs, an interpreted Petri net. It is shown here that the feasibility of designs whose corresponding behavior is periodic can be studied using a technique called timing analysis for synthesis.
{"title":"Assessing the feasibility of interface designs before their implementation","authors":"M. Escalante, N. Dimopoulos","doi":"10.1109/ASPDAC.1995.486216","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486216","url":null,"abstract":"During the design of microprocessor-based systems, once the system architecture has been decided and the major components (processors, memories, to devices) have been selected from a component library, it is necessary to design interface logic to integrate the system. Such an interface design can be carried out based on the protocols used by the components. This paper addresses the problem of determining the feasibility of a design prior to synthesis. A design is called feasible if it achieves the desired functionality and satisfies the given environmental constraints. Because timing is an important aspect of a correct design, protocols are described using timed signal transition graphs, an interpreted Petri net. It is shown here that the feasibility of designs whose corresponding behavior is periodic can be studied using a technique called timing analysis for synthesis.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114534773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486247
M. Miyama, G. Yokomizo, M. Iwabuchi, M. Kinoshita
A mixed-mode simulator is described that can simulate voltage fluctuations in the power supply network. Current flow due to logic events is taken into account in order to predict the voltage fluctuations. The difference between the maximum voltage fluctuations calculated by the proposed mixed-mode simulation and these calculated by conventional circuit simulation are within 20%, and we demonstrated the feasibility of the proposed simulation by simulating an entire MOS memory chip (36,000 transistors) in 75 minutes on an HP9000/735.
{"title":"An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctuation","authors":"M. Miyama, G. Yokomizo, M. Iwabuchi, M. Kinoshita","doi":"10.1109/ASPDAC.1995.486247","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486247","url":null,"abstract":"A mixed-mode simulator is described that can simulate voltage fluctuations in the power supply network. Current flow due to logic events is taken into account in order to predict the voltage fluctuations. The difference between the maximum voltage fluctuations calculated by the proposed mixed-mode simulation and these calculated by conventional circuit simulation are within 20%, and we demonstrated the feasibility of the proposed simulation by simulating an entire MOS memory chip (36,000 transistors) in 75 minutes on an HP9000/735.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121964599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486224
Man-Fai Yu, W. Dai
PGA routing has the freedom of routing any pin to any pad. We propose an algorithm (EVENPGA) that generates a monotonic topological routing. The routing has no detours and is uniformly distributed optimally. The wire length is also the shortest possible under the taxicab wiring metric. If the topological routing is routable, the maximum density of critical cuts along a ring is the minimum possible. Once the topological routing is done, physical layout can easily be obtained using Surf, a rubberband-based routing system.
{"title":"Pin assignment and routing on a single-layer pin grid array","authors":"Man-Fai Yu, W. Dai","doi":"10.1109/ASPDAC.1995.486224","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486224","url":null,"abstract":"PGA routing has the freedom of routing any pin to any pad. We propose an algorithm (EVENPGA) that generates a monotonic topological routing. The routing has no detours and is uniformly distributed optimally. The wire length is also the shortest possible under the taxicab wiring metric. If the topological routing is routable, the maximum density of critical cuts along a ring is the minimum possible. Once the topological routing is done, physical layout can easily be obtained using Surf, a rubberband-based routing system.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125104646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486239
B. M. Riess, H.A. Giselbrecht, B. Wurth
This paper considers the problem of partitioning a large, technology mapped circuit onto multiple FPGA devices of a specified device library. We propose an iterative three-step approach applying an analytical embedding technique, initial partitioning, and a k-way ratio cut improvement procedure. We successfully partitioned the ACM/SIGDA XILINX FPGA Benchmark circuits obtaining feasible design solutions with lower total dollar costs than previous methods. Moreover, our approach simultaneously assigns the FPGAs to physical locations on the FPGA board.
{"title":"A new k-way partitioning approach for multiple types of FPGAs","authors":"B. M. Riess, H.A. Giselbrecht, B. Wurth","doi":"10.1109/ASPDAC.1995.486239","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486239","url":null,"abstract":"This paper considers the problem of partitioning a large, technology mapped circuit onto multiple FPGA devices of a specified device library. We propose an iterative three-step approach applying an analytical embedding technique, initial partitioning, and a k-way ratio cut improvement procedure. We successfully partitioned the ACM/SIGDA XILINX FPGA Benchmark circuits obtaining feasible design solutions with lower total dollar costs than previous methods. Moreover, our approach simultaneously assigns the FPGAs to physical locations on the FPGA board.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114433684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486212
Y. Katsura, T. Koide, S. Wakabayashi, N. Yoshida
In this paper, we propose a new and the first MCM system partitioning method considering chip-to-chip delays, chip areas and I/O pins constraints. The proposed method consists of two steps, a clustering step considering the three constraints and an iterative improvement step with mathematical programming. In the first step, we apply two clustering algorithms considering the three constraints and reduce the size of the large MCM system partitioning problem so as to get a solution within a practical computation time. Next, it generates an initial partitioning with 0-1 integer linear programming (ILP) so as to minimize the total wire length. Since there may exist constraint violations in the initial solution, in the second step, we formulate the partitioning problem as a LP problem selecting a maximal independent set and improve it until the total number of cuts is not decreased and the three constraints are satisfied. We also showed that the number of the timing constraints can be reduced by deleting redundant timing constraints. Experimental results showed that the proposed method is able to produce partitions satisfying the three constraints and improves the number of cuts by a 27% on an average and a 30% in maximum over the conventional method [15] considering only two constrains.
{"title":"A new system partitioning method under performance and physical constraints for multi-chip modules","authors":"Y. Katsura, T. Koide, S. Wakabayashi, N. Yoshida","doi":"10.1109/ASPDAC.1995.486212","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486212","url":null,"abstract":"In this paper, we propose a new and the first MCM system partitioning method considering chip-to-chip delays, chip areas and I/O pins constraints. The proposed method consists of two steps, a clustering step considering the three constraints and an iterative improvement step with mathematical programming. In the first step, we apply two clustering algorithms considering the three constraints and reduce the size of the large MCM system partitioning problem so as to get a solution within a practical computation time. Next, it generates an initial partitioning with 0-1 integer linear programming (ILP) so as to minimize the total wire length. Since there may exist constraint violations in the initial solution, in the second step, we formulate the partitioning problem as a LP problem selecting a maximal independent set and improve it until the total number of cuts is not decreased and the three constraints are satisfied. We also showed that the number of the timing constraints can be reduced by deleting redundant timing constraints. Experimental results showed that the proposed method is able to produce partitions satisfying the three constraints and improves the number of cuts by a 27% on an average and a 30% in maximum over the conventional method [15] considering only two constrains.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125018103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486210
J. Y. Lim, G. Kim, O. I.-S., J. Cho, Y. Kim, H. Kim
This paper presents a CSIC (Customer Specification Integrated Circuit) implementation, which includes a 512/1200/2400 bps POCSAG decoder, PDI2400 and MC68HC05 changed by PANTECH. It can receive all the data with the rate of 512/1200/2400 bps of a single clock of 76.8 KHz. It is designed to have maximum 2 own frames for service enhancement. To improve receiver quality, a preamble detection considering frequency tolerance and a SCW (Synchronization Code Word) detection at every 4 bit is suggested. Also we consider an error correction of address and message up to 2 bits. Furthermore, it is possible with proposed PF (Preamble Frequency) error to achieve a battery life increase due to the turn-off of RF circuits when the preamble signal is detected with noises. The chip is designed using VHDL code from PDI2400 micro-architecture level. It is verified with VHDL simulation software of PowerView. Its logic diagrams are synthesized with VHDL synthesis software of PowerView. Proposed decoder and MC68HC05 CPU of MOTOROLA are integrated with about 88000 transistors by using 1.0 /spl mu/m HCMOS process and named MC68HC05PD6. It is proved that the wrong detection numbers of preamble of noises are significantly reduced in the pager system that uses our chip through the real field test. The system receiving performance is improved by 20% of average, compared with other existing systems.
{"title":"A CSIC implementation with POCSAG decoder and microcontroller for paging applications","authors":"J. Y. Lim, G. Kim, O. I.-S., J. Cho, Y. Kim, H. Kim","doi":"10.1109/ASPDAC.1995.486210","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486210","url":null,"abstract":"This paper presents a CSIC (Customer Specification Integrated Circuit) implementation, which includes a 512/1200/2400 bps POCSAG decoder, PDI2400 and MC68HC05 changed by PANTECH. It can receive all the data with the rate of 512/1200/2400 bps of a single clock of 76.8 KHz. It is designed to have maximum 2 own frames for service enhancement. To improve receiver quality, a preamble detection considering frequency tolerance and a SCW (Synchronization Code Word) detection at every 4 bit is suggested. Also we consider an error correction of address and message up to 2 bits. Furthermore, it is possible with proposed PF (Preamble Frequency) error to achieve a battery life increase due to the turn-off of RF circuits when the preamble signal is detected with noises. The chip is designed using VHDL code from PDI2400 micro-architecture level. It is verified with VHDL simulation software of PowerView. Its logic diagrams are synthesized with VHDL synthesis software of PowerView. Proposed decoder and MC68HC05 CPU of MOTOROLA are integrated with about 88000 transistors by using 1.0 /spl mu/m HCMOS process and named MC68HC05PD6. It is proved that the wrong detection numbers of preamble of noises are significantly reduced in the pager system that uses our chip through the real field test. The system receiving performance is improved by 20% of average, compared with other existing systems.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128098405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486358
A. Masuda, Hiroshi Imai, J.P. Hansen, M. Sekine
Most existing high-level synthesis (HLS) systems attempt to generate a circuit from a behavioral description "out of the void", using the entire design space as the search domain. Because of the vastness of the search space, it is impossible to do more than a coarse grain search, often resulting in inefficient designs. This approach ignores the designer's knowledge of the general structure of the circuit to be synthesized. In this paper, we describe the HLS system SIDER (Synthesis by Initial Design Extension and Refinement). SIDER utilizes designer knowledge about the design space in the form of an initial circuit. By limiting search to the neighborhood of this initial circuit, much finer grain search can be performed yielding a higher quality design. The effectiveness of the SIDER approach is shown by HLS of a 300 line C description of 27 instructions from a MC6502 CPU.
大多数现有的高级综合(high-level synthesis, HLS)系统试图从“无中生有”的行为描述中生成电路，使用整个设计空间作为搜索域。由于搜索空间的巨大，不可能进行比粗粒度搜索更多的搜索，这通常会导致低效的设计。这种方法忽略了设计者对要合成的电路的一般结构的了解。在本文中，我们描述了HLS系统的SIDER (Synthesis by Initial Design Extension and Refinement)。SIDER以初始电路的形式利用设计者关于设计空间的知识。通过将搜索限制在初始电路的邻域，可以执行更细粒度的搜索，从而产生更高质量的设计。来自MC6502 CPU的27条指令的300行C描述的HLS显示了SIDER方法的有效性。
{"title":"Search space reduction in high level synthesis by use of an initial circuit","authors":"A. Masuda, Hiroshi Imai, J.P. Hansen, M. Sekine","doi":"10.1109/ASPDAC.1995.486358","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486358","url":null,"abstract":"Most existing high-level synthesis (HLS) systems attempt to generate a circuit from a behavioral description \"out of the void\", using the entire design space as the search domain. Because of the vastness of the search space, it is impossible to do more than a coarse grain search, often resulting in inefficient designs. This approach ignores the designer's knowledge of the general structure of the circuit to be synthesized. In this paper, we describe the HLS system SIDER (Synthesis by Initial Design Extension and Refinement). SIDER utilizes designer knowledge about the design space in the form of an initial circuit. By limiting search to the neighborhood of this initial circuit, much finer grain search can be performed yielding a higher quality design. The effectiveness of the SIDER approach is shown by HLS of a 300 line C description of 27 instructions from a MC6502 CPU.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115339328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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