Pub Date : 2012-11-16DOI: 10.1049/iet-cds.2011.0347
Ning Chen, Bing Li, Ulf Schlichtmann
In this paper, the authors build a new modelling framework for the timing behaviour of a flipflop by putting the clock-to-q delay into a nonlinear functional relationship with the data/clock alignment of the flipflop. This new framework opens new perspectives into the functioning of a digital circuit by viewing it as a fully interconnected and interdependent system. Consequently, the traditional method for timing analysis is rendered insufficient. An iterative timing analysis method is then developed to solve two related problems. One is to check whether a circuit can work at a given clock period; the other is to determine the minimal clock period of a circuit. Experimental results show that a reduction of the clock period is achieved and its significance is observed especially when process variation is considered.
{"title":"Iterative timing analysis based on nonlinear and interdependent flipflop modelling","authors":"Ning Chen, Bing Li, Ulf Schlichtmann","doi":"10.1049/iet-cds.2011.0347","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0347","url":null,"abstract":"In this paper, the authors build a new modelling framework for the timing behaviour of a flipflop by putting the clock-to-q delay into a nonlinear functional relationship with the data/clock alignment of the flipflop. This new framework opens new perspectives into the functioning of a digital circuit by viewing it as a fully interconnected and interdependent system. Consequently, the traditional method for timing analysis is rendered insufficient. An iterative timing analysis method is then developed to solve two related problems. One is to check whether a circuit can work at a given clock period; the other is to determine the minimal clock period of a circuit. Experimental results show that a reduction of the clock period is achieved and its significance is observed especially when process variation is considered.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134192721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-16DOI: 10.1049/iet-cds.2011.0352
Ons Mbarek, A. Pegatoquet, M. Auguin
Building efficient and correct system power-management strategies relies on efficient power architecture decision making as well as respecting structural dependencies induced by such architecture. Transaction level modelling allows a rapid exploration, verification and evaluation of alternative power-management architectures and strategies. This study introduces an efficient methodology for making system power decisions at transaction level (TL) by adding and verifying power intent and management capabilities into TL models. A generic framework that abstracts relevant concepts of the IEEE 1801 unified power format standard and implements assertion-based contracts is used throughout the methodology. A TL-model example is considered to validate the methodology.
{"title":"Using unified power format standard concepts for power-aware design and verification of systems-onchip at transaction level","authors":"Ons Mbarek, A. Pegatoquet, M. Auguin","doi":"10.1049/iet-cds.2011.0352","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0352","url":null,"abstract":"Building efficient and correct system power-management strategies relies on efficient power architecture decision making as well as respecting structural dependencies induced by such architecture. Transaction level modelling allows a rapid exploration, verification and evaluation of alternative power-management architectures and strategies. This study introduces an efficient methodology for making system power decisions at transaction level (TL) by adding and verifying power intent and management capabilities into TL models. A generic framework that abstracts relevant concepts of the IEEE 1801 unified power format standard and implements assertion-based contracts is used throughout the methodology. A TL-model example is considered to validate the methodology.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132602770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-16DOI: 10.1049/iet-cds.2011.0349
A. Rahmani, Kameswar Rao Vaddina, Khalid Latif, P. Liljeberg, J. Plosila, H. Tenhunen
Increasing the number of cores over a 2D plane is not efficient in hyper-core systems due to long interconnects. As a viable alternative over the 2D planar chip, 3D integrated technology offers greater device integration and shorter interlayer interconnects. 3D networks-on-chip (NoC)–bus hybrid mesh architecture, which is a hybrid between packet-switched network and a bus, was proposed to take advantage of the intrinsic attributes of 3D ICs. Even though this architecture was proposed as a feasible one to provide both performance and area benefits, the challenges of combining both media (NoC and bus) to design 3D NoCs have not been addressed. In this study, an efficient 3D NoC architecture is proposed to optimise performance, power consumption and reliability of 3D NoC–bus hybrid mesh system. The mechanism benefits from a congestion-aware and bus failure tolerant routing algorithm called ‘AdaptiveZ’ for vertical communication. In addition, the authors propose thermal-aware scheduling strategy in order to mitigate temperature by herding most of the switching activity closer to the heatsink. To estimate the efficiency of the proposed architecture, the system has been simulated using uniform, hotspot 10% and negative exponential distribution traffic patterns. In addition, a videoconference encoder has been used as a real application for system analysis. Compared with a typical stacked mesh 3D NoC, our extensive simulations demonstrate significant power, performance and peak temperature improvements.
{"title":"Design and management of high-performance, reliable and thermal-aware 3D networks-on-chip","authors":"A. Rahmani, Kameswar Rao Vaddina, Khalid Latif, P. Liljeberg, J. Plosila, H. Tenhunen","doi":"10.1049/iet-cds.2011.0349","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0349","url":null,"abstract":"Increasing the number of cores over a 2D plane is not efficient in hyper-core systems due to long interconnects. As a viable alternative over the 2D planar chip, 3D integrated technology offers greater device integration and shorter interlayer interconnects. 3D networks-on-chip (NoC)–bus hybrid mesh architecture, which is a hybrid between packet-switched network and a bus, was proposed to take advantage of the intrinsic attributes of 3D ICs. Even though this architecture was proposed as a feasible one to provide both performance and area benefits, the challenges of combining both media (NoC and bus) to design 3D NoCs have not been addressed. In this study, an efficient 3D NoC architecture is proposed to optimise performance, power consumption and reliability of 3D NoC–bus hybrid mesh system. The mechanism benefits from a congestion-aware and bus failure tolerant routing algorithm called ‘AdaptiveZ’ for vertical communication. In addition, the authors propose thermal-aware scheduling strategy in order to mitigate temperature by herding most of the switching activity closer to the heatsink. To estimate the efficiency of the proposed architecture, the system has been simulated using uniform, hotspot 10% and negative exponential distribution traffic patterns. In addition, a videoconference encoder has been used as a real application for system analysis. Compared with a typical stacked mesh 3D NoC, our extensive simulations demonstrate significant power, performance and peak temperature improvements.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115458326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1049/iet-cds.2012.0057
M. A. Arafat, A. Rashid
In this study, a novel low-power high data rate ultra-wideband (UWB) pulse generator circuit is presented, which can be fully integrated in complementary metal oxide semiconductor (CMOS) process. The basic part of the circuit generates a UWB Gaussian monocycle pulse using the triangular pulse generation technique. A new bipolar phase shift keying pulse modulator is designed to control the polarity of the output pulses. The design includes additional functionality to make the pulse generator also applicable for transmitted reference (TR) signalling system. The circuit can generate pulses at a maximum rate of 7 giga pulse per second (Gpps) without TR pulse (TRP) and 3.5 Gpps with TRP. The generated pulses are symmetrical, each having a width of 142 ps and a peak-to-peak swing of 500 mV. The −3 dB bandwidth of the pulse spectrum is 9 GHz. The pulse generator consumes only 1.13 pJ per pulse from 1.2 V supply. The circuit is designed and simulated in 90 nm CMOS technology.
{"title":"A novel 7 Gbps low-power CMOS ultra-wideband pulse generator","authors":"M. A. Arafat, A. Rashid","doi":"10.1049/iet-cds.2012.0057","DOIUrl":"https://doi.org/10.1049/iet-cds.2012.0057","url":null,"abstract":"In this study, a novel low-power high data rate ultra-wideband (UWB) pulse generator circuit is presented, which can be fully integrated in complementary metal oxide semiconductor (CMOS) process. The basic part of the circuit generates a UWB Gaussian monocycle pulse using the triangular pulse generation technique. A new bipolar phase shift keying pulse modulator is designed to control the polarity of the output pulses. The design includes additional functionality to make the pulse generator also applicable for transmitted reference (TR) signalling system. The circuit can generate pulses at a maximum rate of 7 giga pulse per second (Gpps) without TR pulse (TRP) and 3.5 Gpps with TRP. The generated pulses are symmetrical, each having a width of 142 ps and a peak-to-peak swing of 500 mV. The −3 dB bandwidth of the pulse spectrum is 9 GHz. The pulse generator consumes only 1.13 pJ per pulse from 1.2 V supply. The circuit is designed and simulated in 90 nm CMOS technology.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115003823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1049/iet-cds.2012.0140
G. Scandurra, G. Cannatà, C. Ciofi
It has recently been proposed by a few authors that the trigonometric Pythagorean identity can be used for the implementation of precision full-wave rectifiers for sinusoidal signals with advantages with respect to diode-based rectifiers for amplitudes in the hundreds of mV range. The approaches proposed so far require a 90° phase shifter and this results in the obvious limitation that the input signal frequency must be known prior to amplitude measurement. In this study, the authors propose a new precision full-wave rectifier, capable of overcoming this limitation. Starting from the sinusoidal input, a squared co-sinusoidal signal is obtained in a wide frequency range by multiplying the output signals of an integrator and of a differentiator. The signal thus obtained is added to the input signal squared, and a square root extractor is employed for obtaining a DC signal proportional to the amplitude of the input signal. A prototype capable of operating within a two decades frequency range across 3200 Hz has been realised and tested with an accuracy better than 2% and a residual ripple of less than 0.3% for input amplitudes larger than 100 mV. A configuration capable of operating in the MHz frequency range is also proposed.
{"title":"Wide bandwidth pythagorean rectifier","authors":"G. Scandurra, G. Cannatà, C. Ciofi","doi":"10.1049/iet-cds.2012.0140","DOIUrl":"https://doi.org/10.1049/iet-cds.2012.0140","url":null,"abstract":"It has recently been proposed by a few authors that the trigonometric Pythagorean identity can be used for the implementation of precision full-wave rectifiers for sinusoidal signals with advantages with respect to diode-based rectifiers for amplitudes in the hundreds of mV range. The approaches proposed so far require a 90° phase shifter and this results in the obvious limitation that the input signal frequency must be known prior to amplitude measurement. In this study, the authors propose a new precision full-wave rectifier, capable of overcoming this limitation. Starting from the sinusoidal input, a squared co-sinusoidal signal is obtained in a wide frequency range by multiplying the output signals of an integrator and of a differentiator. The signal thus obtained is added to the input signal squared, and a square root extractor is employed for obtaining a DC signal proportional to the amplitude of the input signal. A prototype capable of operating within a two decades frequency range across 3200 Hz has been realised and tested with an accuracy better than 2% and a residual ripple of less than 0.3% for input amplitudes larger than 100 mV. A configuration capable of operating in the MHz frequency range is also proposed.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124321814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1049/iet-cds.2011.0238
I. Kianpour, M. Nejad, Lirong Zheng
In this study an ultra-low-power successive approximation register (SAR) analogue-to-digital converter (ADC) for radio frequency identification (RFID) applications is presented. Several techniques ...
{"title":"78 nW ultra-low-power 17 kS/s two-step-successive approximation register analogue-to-digital converter for RFID and sensing applications","authors":"I. Kianpour, M. Nejad, Lirong Zheng","doi":"10.1049/iet-cds.2011.0238","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0238","url":null,"abstract":"In this study an ultra-low-power successive approximation register (SAR) analogue-to-digital converter (ADC) for radio frequency identification (RFID) applications is presented. Several techniques ...","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134109579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1049/iet-cds.2012.0053
S. Askari, M. Nourani
N-tuple modular redundancy techniques have been widely used to improve the reliability of digital circuits. Unfortunately, an equivalent technique has been rarely used for analogue and mixed-signal systems. In this study, propose a redundancy-based fault-tolerant methodology is proposed to design highly reliable analogue and mixed-signal circuits. The key contribution of the proposed work is: (a) systematic sensitivity analysis to identify critical nodes in a circuit and (b) a design methodology for improving the reliability of analogue and mixed-signal circuits using an innovative mean voter. The mean voter is a low-power, small area, very high bandwidth and linearly scalable unit; and it works for both odd and even redundancy factors. For the proof of concept, the authors designed two analogue-to-digital converters and an analogue filter, which are used in mixed-signal applications. Experimental results are reported to verify the concept and measure the system's reliability when failures, such as single upset transient faults, occur.
{"title":"Design methodology for mitigating transient errors in analogue and mixed-signal circuits","authors":"S. Askari, M. Nourani","doi":"10.1049/iet-cds.2012.0053","DOIUrl":"https://doi.org/10.1049/iet-cds.2012.0053","url":null,"abstract":"N-tuple modular redundancy techniques have been widely used to improve the reliability of digital circuits. Unfortunately, an equivalent technique has been rarely used for analogue and mixed-signal systems. In this study, propose a redundancy-based fault-tolerant methodology is proposed to design highly reliable analogue and mixed-signal circuits. The key contribution of the proposed work is: (a) systematic sensitivity analysis to identify critical nodes in a circuit and (b) a design methodology for improving the reliability of analogue and mixed-signal circuits using an innovative mean voter. The mean voter is a low-power, small area, very high bandwidth and linearly scalable unit; and it works for both odd and even redundancy factors. For the proof of concept, the authors designed two analogue-to-digital converters and an analogue filter, which are used in mixed-signal applications. Experimental results are reported to verify the concept and measure the system's reliability when failures, such as single upset transient faults, occur.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127526668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1049/iet-cds.2011.0287
Joaquim A. R. Azevedo, Filipe E. S. Santos
It is well-known that wireless sensor networks (WSNs) promise to revolutionise the way the authors can interact with the physical world. However, the deployment of these systems in practical environments is very limited because of power constraints. Systems based on solar, vibrational and thermal energy are the most used in WSN applications and only a few studies consider the wind for energy harvesting. Another important source of energy is the water flow. In the context of the WSN, it was found that there are practically no systems using such source. The purpose of this study is to evaluate the use of small-scale wind and hydro generators for energy harvesting to power wireless sensor nodes. For this purpose, the power coefficients and the output power of several horizontal-axis and Savonius wind turbines were determined. Systems based on Pelton and propeller turbines were constructed to evaluate the effect of some parameters in small-scale power generation.
{"title":"Energy harvesting from wind and water for autonomous wireless sensor nodes","authors":"Joaquim A. R. Azevedo, Filipe E. S. Santos","doi":"10.1049/iet-cds.2011.0287","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0287","url":null,"abstract":"It is well-known that wireless sensor networks (WSNs) promise to revolutionise the way the authors can interact with the physical world. However, the deployment of these systems in practical environments is very limited because of power constraints. Systems based on solar, vibrational and thermal energy are the most used in WSN applications and only a few studies consider the wind for energy harvesting. Another important source of energy is the water flow. In the context of the WSN, it was found that there are practically no systems using such source. The purpose of this study is to evaluate the use of small-scale wind and hydro generators for energy harvesting to power wireless sensor nodes. For this purpose, the power coefficients and the output power of several horizontal-axis and Savonius wind turbines were determined. Systems based on Pelton and propeller turbines were constructed to evaluate the effect of some parameters in small-scale power generation.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127691578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1049/iet-cds.2012.0002
L. Wen, Z. Li, Y. Li
Dynamic circuits are extensively employed in very-large-scale integration chips because of their high performance. Unfortunately, they are more susceptible to noise than static complementary metal oxide semiconductor circuits. With the continuous down-scaling of process technology and the supply voltage, improved noise immunity in dynamic circuits is essential. In this study, two new schemes are proposed to enhance the noise tolerance of dynamic address decoders, and their performance, noise tolerance and power consumption are compared with those of a conventional dynamic decoding circuit and a previous scheme. A dynamic 4–16 decoder employing the proposed delay technique exhibits 131.5 and 2.6% improvements in noise tolerance and performance, respectively, whereas a 4–16 decoder exploiting the proposed mirror scheme achieves 291.2 and 25.2% improvements; both used 65 nm process technology. Moreover, the proposed techniques are more resistant to process variations and more tolerant of a lower power supply.
{"title":"High-performance dynamic circuit techniques with improved noise immunity for address decoders","authors":"L. Wen, Z. Li, Y. Li","doi":"10.1049/iet-cds.2012.0002","DOIUrl":"https://doi.org/10.1049/iet-cds.2012.0002","url":null,"abstract":"Dynamic circuits are extensively employed in very-large-scale integration chips because of their high performance. Unfortunately, they are more susceptible to noise than static complementary metal oxide semiconductor circuits. With the continuous down-scaling of process technology and the supply voltage, improved noise immunity in dynamic circuits is essential. In this study, two new schemes are proposed to enhance the noise tolerance of dynamic address decoders, and their performance, noise tolerance and power consumption are compared with those of a conventional dynamic decoding circuit and a previous scheme. A dynamic 4–16 decoder employing the proposed delay technique exhibits 131.5 and 2.6% improvements in noise tolerance and performance, respectively, whereas a 4–16 decoder exploiting the proposed mirror scheme achieves 291.2 and 25.2% improvements; both used 65 nm process technology. Moreover, the proposed techniques are more resistant to process variations and more tolerant of a lower power supply.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134055197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1049/iet-cds.2012.0014
S. Liang, W. Redman-White
An integrated frequency synthesiser is designed and implemented in standard 130 nm complementary metal-oxide semiconductor (CMOS) technology for spectrum monitoring receiver function needed in an associated cognitive radio system. This function demands very wide continuous tuning range albeit with only moderate phase noise performance, although low-power consumption and small die area are high priorities. To meet these unusual specifications, a ring oscillator is used as the frequency source, and a novel high-speed low-power integer-N programmable divider is developed to achieve the tuning range. Using a 25 MHz reference frequency, the ring oscillator-based synthesiser tunes continuously from 5 to 7.3 GHz with 100 MHz steps, maintaining the measured phase noise and reference spur levels below −80.5 dBc/Hz at any frequency offset between 100 kHz and 100 MHz for all output frequencies. The power consumption of the complete frequency synthesiser (excluding the output buffer and the reference crystal oscillator) is 9.98 mW from a 1.2 V supply.
{"title":"Integrated CMOS wide tuning range integer-N frequency synthesiser for spectrum monitoring functions in cognitive radio systems","authors":"S. Liang, W. Redman-White","doi":"10.1049/iet-cds.2012.0014","DOIUrl":"https://doi.org/10.1049/iet-cds.2012.0014","url":null,"abstract":"An integrated frequency synthesiser is designed and implemented in standard 130 nm complementary metal-oxide semiconductor (CMOS) technology for spectrum monitoring receiver function needed in an associated cognitive radio system. This function demands very wide continuous tuning range albeit with only moderate phase noise performance, although low-power consumption and small die area are high priorities. To meet these unusual specifications, a ring oscillator is used as the frequency source, and a novel high-speed low-power integer-N programmable divider is developed to achieve the tuning range. Using a 25 MHz reference frequency, the ring oscillator-based synthesiser tunes continuously from 5 to 7.3 GHz with 100 MHz steps, maintaining the measured phase noise and reference spur levels below −80.5 dBc/Hz at any frequency offset between 100 kHz and 100 MHz for all output frequencies. The power consumption of the complete frequency synthesiser (excluding the output buffer and the reference crystal oscillator) is 9.98 mW from a 1.2 V supply.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134569407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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