Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543326
C. Poh, Shao-Wen Chen, Ting-Yi Wang, Min-Lun Chai, W. Lin, Jong-Rong Wang, C. Shih
This paper presents a generalized theoretical model for performance prediction of a thermoelectric module as a generator and a cooler. Performance analysis was done under different input conditions of some thermoelectric generators and thermoelectric coolers which are distinct in number of semiconductor pairs. Results show that the larger number of thermoelectric elements will have a higher coefficient of performance for both generator and cooler.
{"title":"Analysis of characteristics and performance of thermoelectric modules","authors":"C. Poh, Shao-Wen Chen, Ting-Yi Wang, Min-Lun Chai, W. Lin, Jong-Rong Wang, C. Shih","doi":"10.1109/ISNE.2016.7543326","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543326","url":null,"abstract":"This paper presents a generalized theoretical model for performance prediction of a thermoelectric module as a generator and a cooler. Performance analysis was done under different input conditions of some thermoelectric generators and thermoelectric coolers which are distinct in number of semiconductor pairs. Results show that the larger number of thermoelectric elements will have a higher coefficient of performance for both generator and cooler.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125201982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543336
K. Lay, Lee-Jyi Wang, Pei-Lun Han
In this paper, we deal with the situation wherein QR codes are printed on spheres. When an image is obtained from such a QR code, it can be seriously distorted. A scheme based on conic segmentation (CS) is proposed to rectify the distorted QR images.
{"title":"Decoding of QR codes printed on spheres","authors":"K. Lay, Lee-Jyi Wang, Pei-Lun Han","doi":"10.1109/ISNE.2016.7543336","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543336","url":null,"abstract":"In this paper, we deal with the situation wherein QR codes are printed on spheres. When an image is obtained from such a QR code, it can be seriously distorted. A scheme based on conic segmentation (CS) is proposed to rectify the distorted QR images.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128507060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543362
Meng-Lieh Sheu, L. Tsao
A neighbor pixel difference sensing scheme is proposed for sub-fF detectability in the capacitive fingerprint sensor chip. A proof-of-concept chip with 16 × 16 sensing pixels is designed with 0.18μm 1P6M CMOS process. The output range is 0.61–1.22 V at 1.8 V power supply. A sensitivity of 0.61 mV/af is achieved for capacitance difference ranging from −500 aF to 500 aF.
{"title":"A sub-fF capacitive fingerprint sensor with neighbor pixel difference sensing","authors":"Meng-Lieh Sheu, L. Tsao","doi":"10.1109/ISNE.2016.7543362","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543362","url":null,"abstract":"A neighbor pixel difference sensing scheme is proposed for sub-fF detectability in the capacitive fingerprint sensor chip. A proof-of-concept chip with 16 × 16 sensing pixels is designed with 0.18μm 1P6M CMOS process. The output range is 0.61–1.22 V at 1.8 V power supply. A sensitivity of 0.61 mV/af is achieved for capacitance difference ranging from −500 aF to 500 aF.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122814319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543340
Zhenyi Yang, C. Leung, P. Lai, P. Pong
This work studies the influence of the Si/SiO2 interface traps at the sidewall of sectorial SD-MAGFET in detail. Ionized acceptor traps work like negative oxide charges to enhance the magnetic sensing of the device by depleting the conduction channel, but ionized donor traps behave like positive oxide charges to weaken the magnetic sensing by inducing a parasitic channel at the sidewall. In particular, the higher the density of the acceptor or donor traps, the stronger is the effect on the magnetic sensitivity. Moreover, the trap energy also affects the sensitivity, with larger effect for traps lying closer to the valence or conduction band.
{"title":"A numerical investigation on effects of lateral Si/SiO2 interface traps on magnetic sensitivity of sectorial SD-MAGFET","authors":"Zhenyi Yang, C. Leung, P. Lai, P. Pong","doi":"10.1109/ISNE.2016.7543340","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543340","url":null,"abstract":"This work studies the influence of the Si/SiO2 interface traps at the sidewall of sectorial SD-MAGFET in detail. Ionized acceptor traps work like negative oxide charges to enhance the magnetic sensing of the device by depleting the conduction channel, but ionized donor traps behave like positive oxide charges to weaken the magnetic sensing by inducing a parasitic channel at the sidewall. In particular, the higher the density of the acceptor or donor traps, the stronger is the effect on the magnetic sensitivity. Moreover, the trap energy also affects the sensitivity, with larger effect for traps lying closer to the valence or conduction band.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127367469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543366
Neeraj Agarwal, Neeru Agarwal, Manisha Sharma
In this Paper, issues related to substrate coupling in system on chip design are described and demonstrated including the physical phenomenon responsible for its creation, coupling transmission mechanism and media, parameter affecting coupling strengths and its impact on mixed signal integrated circuits. A test chip to find out various aspect of mixed signal interference is planned in 0.8pm N well P sub CMOS technology 5V double poly double metal process. Basic aim of chip is to find out magnitude of interference happening when analog and digital circuit is placed nearby on a common substrate. An instrumentation amplifier with high CMRR is also designed for noise sensing. MOSFET capacitors at the input of instrumentation amplifier are used for the picking of substrate interference.
{"title":"Design a test chip to find out mixed signal interference with broad range instrumentation amplifier","authors":"Neeraj Agarwal, Neeru Agarwal, Manisha Sharma","doi":"10.1109/ISNE.2016.7543366","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543366","url":null,"abstract":"In this Paper, issues related to substrate coupling in system on chip design are described and demonstrated including the physical phenomenon responsible for its creation, coupling transmission mechanism and media, parameter affecting coupling strengths and its impact on mixed signal integrated circuits. A test chip to find out various aspect of mixed signal interference is planned in 0.8pm N well P sub CMOS technology 5V double poly double metal process. Basic aim of chip is to find out magnitude of interference happening when analog and digital circuit is placed nearby on a common substrate. An instrumentation amplifier with high CMRR is also designed for noise sensing. MOSFET capacitors at the input of instrumentation amplifier are used for the picking of substrate interference.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126706419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543367
Xiaowei Chen, Seyed Alireza Pourbakhsh, L. Hou, Na Gong, Jinhui Wang
In three-dimensional (3D) integrated circuit (IC), a large number of dummy through silicon vias (TSV) are required for thermal and thinning concerns. However, limited attention is paid to the fact that these dummy TSVs can be multi-functional and used for timing purposes. In this paper, we propose to use those "timing wasteful" dummy TSVs to replace bit line delay cells. Also, a TSV allocation algorithm is presented to optimize the TSV array layout. Finally, three memory designs are implemented to verify the feasibility and reliability of the proposed technology. It is found that all delay cells in these 3 memories can be replaced by TSV arrays.
{"title":"3D memory design based on through silicon vias enabled timing optimization","authors":"Xiaowei Chen, Seyed Alireza Pourbakhsh, L. Hou, Na Gong, Jinhui Wang","doi":"10.1109/ISNE.2016.7543367","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543367","url":null,"abstract":"In three-dimensional (3D) integrated circuit (IC), a large number of dummy through silicon vias (TSV) are required for thermal and thinning concerns. However, limited attention is paid to the fact that these dummy TSVs can be multi-functional and used for timing purposes. In this paper, we propose to use those \"timing wasteful\" dummy TSVs to replace bit line delay cells. Also, a TSV allocation algorithm is presented to optimize the TSV array layout. Finally, three memory designs are implemented to verify the feasibility and reliability of the proposed technology. It is found that all delay cells in these 3 memories can be replaced by TSV arrays.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"16 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133203953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543300
T. Chiang, Chen Chih Yo, Hong-Wun Gao, Yeong-Her Wang
Based on the device and equivalent transistor models, we present a new device-physics-oriented static noise margin (NM), logic swing, and average power consumption model (Pave) for junctionless double-gate MOSFET (JLDGFET) working on subthreshold CMOS logic gates. Theoretical analysis of the NM and Pave for JLDG MOSFET operating in low-voltage condition is first revealed. The device parameters such as the thick silicon thickness tsi, thick gate oxide thickness tox, large supply voltage Vdd, and short channel length Lg, can severely degrade the NM and induce large Pave due to serious short-channel effect (SCEs). On the contrary, both the small subthreshold slope and balanced transistor strength S induced by device parameters can suppress the NM degradation and reduce Pave efficiently. Being similar to DIBL, both NM and Pave can also be uniquely controlled and determined by the scaling factor according to the scaling theory.
{"title":"A new noise margin and average static power model for junctionless double-gate FETs (JLDGFET) working in subthreshold logic gate","authors":"T. Chiang, Chen Chih Yo, Hong-Wun Gao, Yeong-Her Wang","doi":"10.1109/ISNE.2016.7543300","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543300","url":null,"abstract":"Based on the device and equivalent transistor models, we present a new device-physics-oriented static noise margin (NM), logic swing, and average power consumption model (Pave) for junctionless double-gate MOSFET (JLDGFET) working on subthreshold CMOS logic gates. Theoretical analysis of the NM and Pave for JLDG MOSFET operating in low-voltage condition is first revealed. The device parameters such as the thick silicon thickness tsi, thick gate oxide thickness tox, large supply voltage Vdd, and short channel length Lg, can severely degrade the NM and induce large Pave due to serious short-channel effect (SCEs). On the contrary, both the small subthreshold slope and balanced transistor strength S induced by device parameters can suppress the NM degradation and reduce Pave efficiently. Being similar to DIBL, both NM and Pave can also be uniquely controlled and determined by the scaling factor according to the scaling theory.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131501939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543400
Keng-Yuan Chen, M. Peng, Chyi-Sheng Huang
In the digital implementation, PWM pulses can only change switching states at some specific time instants depending on the system clock frequency. This phenomenon results in the deviation between the desired and the produced phase voltages. Although the deviation is small in each carrier period, the accumulated error will result in large current harmonics for inductive load. In this paper, a high-order filtered SVPWM is proposed for the three-phase motor drive to overcome this problem. By further incorporating the band-stop filter, the specific harmonic component is reduced. Two experiments confirm the reliability and applicability of the proposed modulator.
{"title":"Three-phase filtered SVPWM motor drive","authors":"Keng-Yuan Chen, M. Peng, Chyi-Sheng Huang","doi":"10.1109/ISNE.2016.7543400","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543400","url":null,"abstract":"In the digital implementation, PWM pulses can only change switching states at some specific time instants depending on the system clock frequency. This phenomenon results in the deviation between the desired and the produced phase voltages. Although the deviation is small in each carrier period, the accumulated error will result in large current harmonics for inductive load. In this paper, a high-order filtered SVPWM is proposed for the three-phase motor drive to overcome this problem. By further incorporating the band-stop filter, the specific harmonic component is reduced. Two experiments confirm the reliability and applicability of the proposed modulator.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121276763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543351
Ruisi Ge, Hong Pan, Zhibin Lin, L. Hou, Na Gong, Jinhui Wang
Wireless Sensor Networks (WSNs) have attracted more attentions due to its low cost and convenience. Despite the great potential, power supply restricts the application of WSNs. Especially in the environment such as rural areas, underground and underwater structures, the electrical wire or battery increases the cost of installation and brings the unexpected inconvenience. In this abstract, a far-field radio frequency (RF) powered wireless sensor network is presented. Moreover, a mesh network approach is proposed to solve the data collision issue caused by the discontinuous power supply. Test results verify the feasibility and reliability of this WSNs.
{"title":"RF-powered battery-less Wireless Sensor Network","authors":"Ruisi Ge, Hong Pan, Zhibin Lin, L. Hou, Na Gong, Jinhui Wang","doi":"10.1109/ISNE.2016.7543351","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543351","url":null,"abstract":"Wireless Sensor Networks (WSNs) have attracted more attentions due to its low cost and convenience. Despite the great potential, power supply restricts the application of WSNs. Especially in the environment such as rural areas, underground and underwater structures, the electrical wire or battery increases the cost of installation and brings the unexpected inconvenience. In this abstract, a far-field radio frequency (RF) powered wireless sensor network is presented. Moreover, a mesh network approach is proposed to solve the data collision issue caused by the discontinuous power supply. Test results verify the feasibility and reliability of this WSNs.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121480263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-04DOI: 10.1109/ISNE.2016.7543352
S. Jang, W. Lai, Tsui-Chun Kung
This letter proposes a low phase noise CMOS voltage-controlled oscillator (VCO) using a left-handed (LH) LC network and a switching/tuning varactor pair. The proposed VCO has been implemented with the TSMC 0.18 μm 1P6M CMOS technology and the die area of the oscillator is 0.527 × 0.749 mm2. The VCO can generate differential signals in the high (low)-band frequency range of 6.042~6.163(4.038~4.225) GHz. The measured high (low)-band figure of merit (FOM) is -190.2 (-188.6)dBc/Hz.
{"title":"A low noise class-C voltage-controlled oscillator with left-handed resonator","authors":"S. Jang, W. Lai, Tsui-Chun Kung","doi":"10.1109/ISNE.2016.7543352","DOIUrl":"https://doi.org/10.1109/ISNE.2016.7543352","url":null,"abstract":"This letter proposes a low phase noise CMOS voltage-controlled oscillator (VCO) using a left-handed (LH) LC network and a switching/tuning varactor pair. The proposed VCO has been implemented with the TSMC 0.18 μm 1P6M CMOS technology and the die area of the oscillator is 0.527 × 0.749 mm2. The VCO can generate differential signals in the high (low)-band frequency range of 6.042~6.163(4.038~4.225) GHz. The measured high (low)-band figure of merit (FOM) is -190.2 (-188.6)dBc/Hz.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114425325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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