Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405721
Toshikazu Suzuki, H. Yamauchi, K. Satomi, H. Akamatsu
The logic operating voltage is required to suppress for the battery-operated slow application, while the minimum operating voltage of SRAM increase due to the increase in the random threshold-voltage (Vt) fluctuation of the cell transistor (Tr) and the memory capacitance embedded in SoCs with scaling. To suppress the random Vt fluctuation and to guarantee the stable operation over the large memory capacitance at low voltage, a reduced-Vt (LVt) SRAM cell has been proposed. The random Vt fluctuation was suppressed by the proposed LVt cell (Vt = 150 mV) and increase the static noise margin (SNM) for the data-retention at low voltage compared with conventional higher Vt cell (Vt = 300 mV). Another unique disturb-free biasing scheme has also been proposed to cancel the substantial trade-off relationship between SNM and the write margin (WRTM) of SRAM cell. With a 45-nm CMOS technology, these proposed techniques improved the SNM over 6-sigma random Vt fluctuation with the 0.5-V data-retention voltage and the 0.7-V logic bias voltage. Operating current was reduced by 31% at 32-Kbit SRAM module.
{"title":"A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme","authors":"Toshikazu Suzuki, H. Yamauchi, K. Satomi, H. Akamatsu","doi":"10.1109/CICC.2007.4405721","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405721","url":null,"abstract":"The logic operating voltage is required to suppress for the battery-operated slow application, while the minimum operating voltage of SRAM increase due to the increase in the random threshold-voltage (Vt) fluctuation of the cell transistor (Tr) and the memory capacitance embedded in SoCs with scaling. To suppress the random Vt fluctuation and to guarantee the stable operation over the large memory capacitance at low voltage, a reduced-Vt (LVt) SRAM cell has been proposed. The random Vt fluctuation was suppressed by the proposed LVt cell (Vt = 150 mV) and increase the static noise margin (SNM) for the data-retention at low voltage compared with conventional higher Vt cell (Vt = 300 mV). Another unique disturb-free biasing scheme has also been proposed to cancel the substantial trade-off relationship between SNM and the write margin (WRTM) of SRAM cell. With a 45-nm CMOS technology, these proposed techniques improved the SNM over 6-sigma random Vt fluctuation with the 0.5-V data-retention voltage and the 0.7-V logic bias voltage. Operating current was reduced by 31% at 32-Kbit SRAM module.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126387170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405793
Ke-Hou Chen, J. Lu, Shen-Iuan Liu
A 2.4 GHz full-wave AC-to-DC rectifier for wireless telemetry applications is presented. A conventional full-wave rectifier using diode-connected MOS transistors suffers from the power loss due to the intrinsic threshold voltage. In this paper, a full-wave rectifier using a transformer is presented to improve the efficiency. It has been fabricated by using the MOS transistors with medium threshold voltages in 0.18 mum CMOS process. When input power ranges from 6 dBm~12 dBm, this proposed 2.4 GHz full-wave rectifier improves the efficiency of 2.5%, compared with the conventional one.
介绍了一种用于无线遥测应用的2.4 GHz全波交直流整流器。使用二极管连接MOS晶体管的传统全波整流器由于固有阈值电压而遭受功率损耗。本文提出了一种采用变压器的全波整流器，以提高整流效率。采用中阈值电压的MOS晶体管，采用0.18 μ m CMOS工艺制备了该器件。在输入功率为6dbm ~ 12dbm范围内，与传统整流器相比，该整流器的效率提高了2.5%。
{"title":"A 2.4GHz Efficiency-Enhanced Rectifier for Wireless Telemetry","authors":"Ke-Hou Chen, J. Lu, Shen-Iuan Liu","doi":"10.1109/CICC.2007.4405793","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405793","url":null,"abstract":"A 2.4 GHz full-wave AC-to-DC rectifier for wireless telemetry applications is presented. A conventional full-wave rectifier using diode-connected MOS transistors suffers from the power loss due to the intrinsic threshold voltage. In this paper, a full-wave rectifier using a transformer is presented to improve the efficiency. It has been fabricated by using the MOS transistors with medium threshold voltages in 0.18 mum CMOS process. When input power ranges from 6 dBm~12 dBm, this proposed 2.4 GHz full-wave rectifier improves the efficiency of 2.5%, compared with the conventional one.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126414640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405863
W. Fergusson, Rakesh H. Patel, W. Bereza
The modeling and simulation of an all-digital PLL is presented. Verilog-A, owing to its flexibility, is used to create both behavioral and gate-level models used in system-level and circuit-based simulation. The methodology presented allows us to simulate the PLL closed-loop and accurately take into account reference phase noise, DCO phase noise, quantization noise and any excess of it, allowing us to validate our jitter budget for any given application.
{"title":"Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A","authors":"W. Fergusson, Rakesh H. Patel, W. Bereza","doi":"10.1109/CICC.2007.4405863","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405863","url":null,"abstract":"The modeling and simulation of an all-digital PLL is presented. Verilog-A, owing to its flexibility, is used to create both behavioral and gate-level models used in system-level and circuit-based simulation. The methodology presented allows us to simulate the PLL closed-loop and accurately take into account reference phase noise, DCO phase noise, quantization noise and any excess of it, allowing us to validate our jitter budget for any given application.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115886203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405671
Zheng Xu, K. Shepard
Active deskewing is an important technique for managing variability in clock distributions but introduces latency and power-supply-noise sensitivity to the resulting networks. In this paper, we demonstrate how active deskewing can be achieved with resonant distributions without introducing significant jitter. The prototype network operates at a nominal 2-GHz frequency in a 0.18 mum CMOS technology with more than 25 pF/mm of clock loading.
有源倾斜是一种管理时钟分布可变性的重要技术，但会给网络带来延迟和电源噪声敏感性。在本文中，我们演示了如何在不引入显著抖动的情况下实现谐振分布的主动偏置。该原型网络工作在标称2 ghz频率下，采用0.18 μ m CMOS技术，时钟负载超过25 pF/mm。
{"title":"Low-Jitter Active Deskewing Through Injection-Locked Resonant Clocking","authors":"Zheng Xu, K. Shepard","doi":"10.1109/CICC.2007.4405671","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405671","url":null,"abstract":"Active deskewing is an important technique for managing variability in clock distributions but introduces latency and power-supply-noise sensitivity to the resulting networks. In this paper, we demonstrate how active deskewing can be achieved with resonant distributions without introducing significant jitter. The prototype network operates at a nominal 2-GHz frequency in a 0.18 mum CMOS technology with more than 25 pF/mm of clock loading.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132470432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405762
Jaesik Lee, J. Weiner, Hsin-Hung Chen, Y. Baeyens, V. Aksyuk, Young-Kai Chen
This paper presents a low-power MEMS mirror driver for maskless lithography systems. The CMOS driver consists of a 512 x 128 analog memory cell array to drive the position of 512 x 128 MEMS mirror array. The row driver employs an analog de-multiplexing architecture, which eliminates the need for precise matching among multiple row driver characteristics. It uses two parallel high-speed 8-b DACs with 128 sample-and-hold amplifiers (SHAs) to write a multilevel data into memory cells. To verify its functionality, a prototype test chip is implemented with a self-calibration technique to compensate the cell leakage. The driver chip is implemented in a 0.35-mum digital CMOS process. It consumes a 120 mA power with 3/3.6 V supplies.
{"title":"CMOS-Based MEMS Mirror Driver for Maskless Lithography Systems","authors":"Jaesik Lee, J. Weiner, Hsin-Hung Chen, Y. Baeyens, V. Aksyuk, Young-Kai Chen","doi":"10.1109/CICC.2007.4405762","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405762","url":null,"abstract":"This paper presents a low-power MEMS mirror driver for maskless lithography systems. The CMOS driver consists of a 512 x 128 analog memory cell array to drive the position of 512 x 128 MEMS mirror array. The row driver employs an analog de-multiplexing architecture, which eliminates the need for precise matching among multiple row driver characteristics. It uses two parallel high-speed 8-b DACs with 128 sample-and-hold amplifiers (SHAs) to write a multilevel data into memory cells. To verify its functionality, a prototype test chip is implemented with a self-calibration technique to compensate the cell leakage. The driver chip is implemented in a 0.35-mum digital CMOS process. It consumes a 120 mA power with 3/3.6 V supplies.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124570685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405850
N. Robson, J. Safran, C. Kothandaraman, A. Cestero, Xiang Chen, R. Rajeevakumar, A. Leslie, D. Moy, T. Kirihata, S. Iyer
Electrical fuse (eFUSE) has become a popular choice to enable memory redundancy, chip identification and authentication, analog device trimming, and other applications. We will review the evolution and applications of electrical fuse solutions for 180 nm to 45 nm technologies at IBM, and provide some insight into future uses in 32 nm technology and beyond with the eFUSE as a building block for the autonomic chip of the future.
{"title":"Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips","authors":"N. Robson, J. Safran, C. Kothandaraman, A. Cestero, Xiang Chen, R. Rajeevakumar, A. Leslie, D. Moy, T. Kirihata, S. Iyer","doi":"10.1109/CICC.2007.4405850","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405850","url":null,"abstract":"Electrical fuse (eFUSE) has become a popular choice to enable memory redundancy, chip identification and authentication, analog device trimming, and other applications. We will review the evolution and applications of electrical fuse solutions for 180 nm to 45 nm technologies at IBM, and provide some insight into future uses in 32 nm technology and beyond with the eFUSE as a building block for the autonomic chip of the future.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115072097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405837
A. Hajimiri
Millimeter-waves offer promising opportunities and interesting challenges to silicon integrated circuit and system designers. These challenges go beyond standard circuit design questions and span a broader range of topics including wave propagation, antenna design, and communication channel capacity limits. It is only meaningful to evaluate the benefits and shortcoming of silicon-based mm-wave integrated circuits in this broader context. This paper reviews some of these issues and presents several solutions to them.
{"title":"mm-Wave Silicon ICs: Challenges and Opportunities","authors":"A. Hajimiri","doi":"10.1109/CICC.2007.4405837","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405837","url":null,"abstract":"Millimeter-waves offer promising opportunities and interesting challenges to silicon integrated circuit and system designers. These challenges go beyond standard circuit design questions and span a broader range of topics including wave propagation, antenna design, and communication channel capacity limits. It is only meaningful to evaluate the benefits and shortcoming of silicon-based mm-wave integrated circuits in this broader context. This paper reviews some of these issues and presents several solutions to them.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115084418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405771
F. Carbognani, S. Haene, Manuel Arrigo, Claudio Pagnamenta, F. Bürgin, N. Felber, H. Kaeslin, W. Fichtner
In this paper, resonant clocking is applied to a Viterbi decoder for ultra-low-power WLAN communication. Clock skew balancing and excessive cross-over currents are identified as the most relevant issues: H-clock-trees and a new latch circuit are proposed as innovative power-efficient design solutions. The chip has been integrated in a 0.25 μm CMOS process. Supplied at 1.75 V, the 1.35 mm2 core dissipates 50 mW at 54 Mb/s throughput, with about 27% power savings compared to an equivalent circuit with conventional one-phase single-edge-triggered (SET) clocking strategy and a recently published competitor by C.C. Lin, et al (2005). The chip works up to 77 MHz.
{"title":"A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication","authors":"F. Carbognani, S. Haene, Manuel Arrigo, Claudio Pagnamenta, F. Bürgin, N. Felber, H. Kaeslin, W. Fichtner","doi":"10.1109/CICC.2007.4405771","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405771","url":null,"abstract":"In this paper, resonant clocking is applied to a Viterbi decoder for ultra-low-power WLAN communication. Clock skew balancing and excessive cross-over currents are identified as the most relevant issues: H-clock-trees and a new latch circuit are proposed as innovative power-efficient design solutions. The chip has been integrated in a 0.25 μm CMOS process. Supplied at 1.75 V, the 1.35 mm2 core dissipates 50 mW at 54 Mb/s throughput, with about 27% power savings compared to an equivalent circuit with conventional one-phase single-edge-triggered (SET) clocking strategy and a recently published competitor by C.C. Lin, et al (2005). The chip works up to 77 MHz.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117196149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405807
T. Devoivre, Rich Rouse, N. Verghese, P. Hurat
A current density-based model that incorporates narrow width effects is proposed to predict the drawn current of transistors that exhibit non-uniform device geometry. A continuous, integrable, analytical model of current density that includes the details of stress, edge effects and dopant loss/pileup is first calibrated to silicon data or existing SPICE models. Using the active and poly contours of the actual transistor shape obtained from a lithography-like simulation with an enriched model or directly from SEM images, the current density model is integrated over the width of the transistor to obtain its drawn current. From this predicted current, equivalent transistor parameters for circuit simulation can be extracted. Comparison to silicon drive current measurements of poly T and active T structures on a ST 65 nm process show excellent correlation, with an average difference of less than 0.5% for active shapes and 0.8% for poly shapes.
{"title":"Modeling and Validation of Silicon Contour-Based Extraction and Simulation of Non-Uniform Devices","authors":"T. Devoivre, Rich Rouse, N. Verghese, P. Hurat","doi":"10.1109/CICC.2007.4405807","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405807","url":null,"abstract":"A current density-based model that incorporates narrow width effects is proposed to predict the drawn current of transistors that exhibit non-uniform device geometry. A continuous, integrable, analytical model of current density that includes the details of stress, edge effects and dopant loss/pileup is first calibrated to silicon data or existing SPICE models. Using the active and poly contours of the actual transistor shape obtained from a lithography-like simulation with an enriched model or directly from SEM images, the current density model is integrated over the width of the transistor to obtain its drawn current. From this predicted current, equivalent transistor parameters for circuit simulation can be extracted. Comparison to silicon drive current measurements of poly T and active T structures on a ST 65 nm process show excellent correlation, with an average difference of less than 0.5% for active shapes and 0.8% for poly shapes.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129402869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405865
J. Croon, D. Leenaerts, D. Klaassen
An extensive behavioral model is presented for weakly-nonlinear narrowband LNAs. Both the electrical transfer and noise properties are well described. Performance figures can be predicted for varying source and load conditions. A Verilog-A implementation facilitates cross-platform simulations. The model is compared to transistor-level simulations of a simple textbook LNA and of a state-of-the-art 65 nm CMOS LNA in combination with a mixer. Excellent agreements are achieved.
{"title":"Accurate Modeling of RF Circuit Blocks: Weakly-Nonlinear Narrowband LNAs","authors":"J. Croon, D. Leenaerts, D. Klaassen","doi":"10.1109/CICC.2007.4405865","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405865","url":null,"abstract":"An extensive behavioral model is presented for weakly-nonlinear narrowband LNAs. Both the electrical transfer and noise properties are well described. Performance figures can be predicted for varying source and load conditions. A Verilog-A implementation facilitates cross-platform simulations. The model is compared to transistor-level simulations of a simple textbook LNA and of a state-of-the-art 65 nm CMOS LNA in combination with a mixer. Excellent agreements are achieved.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128229017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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