Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405842
J. May, Gabriel M. Rebeiz
In this paper, we present an active 1:16 30-40 GHz power divider implemented in a 0.18 mum SiGe BiCMOS process (Jazz SBC18HXL). The 2 x 2 mm2 power divider exhibits 4.5 plusmn 1.5 dB total power gain with an rms phase imbalance of less than 6deg from 30 to 40 GHz across all 16 channels. This performance is achieved using wideband degenerated 1:4 splitters, and internal matching between the inter-stage on-chip splitters. The chip consumes 190 mA from a 3.3 V supply, and is 15x smaller than an equivalent Teflon-based PCB transmission-line 1:16 power divider. To our knowledge, this is the first 1:16 Ka-Band active power divider implemented in a commercial SiGe BiCMOS technology, and shows excellent amplitude and phase balance over the 30-40 GHz range.
{"title":"A 30-40 GHz 1:16 Internally Matched SiGe Active Power Divider for Phased Array Transmitters","authors":"J. May, Gabriel M. Rebeiz","doi":"10.1109/CICC.2007.4405842","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405842","url":null,"abstract":"In this paper, we present an active 1:16 30-40 GHz power divider implemented in a 0.18 mum SiGe BiCMOS process (Jazz SBC18HXL). The 2 x 2 mm2 power divider exhibits 4.5 plusmn 1.5 dB total power gain with an rms phase imbalance of less than 6deg from 30 to 40 GHz across all 16 channels. This performance is achieved using wideband degenerated 1:4 splitters, and internal matching between the inter-stage on-chip splitters. The chip consumes 190 mA from a 3.3 V supply, and is 15x smaller than an equivalent Teflon-based PCB transmission-line 1:16 power divider. To our knowledge, this is the first 1:16 Ka-Band active power divider implemented in a commercial SiGe BiCMOS technology, and shows excellent amplitude and phase balance over the 30-40 GHz range.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129046730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405811
Wei Dong, Peng Li, Xiaoji Ye
High performance IC designs impose stringent design specifications on clock distribution networks, where clock skews must be well controlled even under the presence of environmental and process variations. As a result, clock meshes are gaining increasing popularity due to their inherent low skew and immunity to variations. While clock meshes are often analyzed in time-domain for the purpose of verification as well as tuning, the massive couplings within the passive mesh structure and in between a large number of clock drivers are challenging to handle. In contrast, frequency-domain steady-state simulation techniques such as harmonic balance (HB) are specifically advantageous since the massive passive mesh structure can be rather compactly represented using matrix transfer function matrices at a discrete set of harmonic frequencies. The remaining challenge, however, is to develop harmonic balance techniques that can efficiently simulate highly nonlinear steady-steady problems corresponding to a large number of tightly coupled clock drivers. In this paper, we present a hierarchically preconditioned algorithm that is particularly suitable to clock mesh analysis. Moreover, we show that the parallelizable nature of our algorithm allows further runtime improvement of large clock mesh analysis via parallel processing.
{"title":"Efficient Frequency-Domain Simulation of Massive Clock Meshes Using Parallel Harmonic Balance","authors":"Wei Dong, Peng Li, Xiaoji Ye","doi":"10.1109/CICC.2007.4405811","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405811","url":null,"abstract":"High performance IC designs impose stringent design specifications on clock distribution networks, where clock skews must be well controlled even under the presence of environmental and process variations. As a result, clock meshes are gaining increasing popularity due to their inherent low skew and immunity to variations. While clock meshes are often analyzed in time-domain for the purpose of verification as well as tuning, the massive couplings within the passive mesh structure and in between a large number of clock drivers are challenging to handle. In contrast, frequency-domain steady-state simulation techniques such as harmonic balance (HB) are specifically advantageous since the massive passive mesh structure can be rather compactly represented using matrix transfer function matrices at a discrete set of harmonic frequencies. The remaining challenge, however, is to develop harmonic balance techniques that can efficiently simulate highly nonlinear steady-steady problems corresponding to a large number of tightly coupled clock drivers. In this paper, we present a hierarchically preconditioned algorithm that is particularly suitable to clock mesh analysis. Moreover, we show that the parallelizable nature of our algorithm allows further runtime improvement of large clock mesh analysis via parallel processing.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"398 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123373214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405740
Lin Zhang, B. Ciftcioglu, Hui Wu
Injection-locked clocking (ILC) has been proposed previously to improve the skew and jitter performance while reducing the power consumption in multi-gigahertz clock distribution networks. This paper presents a new design of the injection-locked oscillator (ILO) suitable for ILC applications. It uses a transformer to generate differential signals and then directly inject them into the ILO core. It also incorporates a switched-capacitor array for frequency tuning and hence digital deskew in ILC. A 4 GHz test chip was designed and fabricated in a 0.18 mum standard digital CMOS. It consists of four ILOs driven by a balanced H-tree. Each ILO consumes less than 1 mW from a 1 V power supply. 5-bit digital deskew achieves 55 ps delay tuning range and 1.8 ps resolution. Measurement shows that only 30 fs cycle-to-cycle jitter degradation was introduced and no phase noise degradation at frequency offset up to 600 kHz.
{"title":"A 1V, 1mW, 4GHz Injection-Locked Oscillator for High-Performance Clocking","authors":"Lin Zhang, B. Ciftcioglu, Hui Wu","doi":"10.1109/CICC.2007.4405740","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405740","url":null,"abstract":"Injection-locked clocking (ILC) has been proposed previously to improve the skew and jitter performance while reducing the power consumption in multi-gigahertz clock distribution networks. This paper presents a new design of the injection-locked oscillator (ILO) suitable for ILC applications. It uses a transformer to generate differential signals and then directly inject them into the ILO core. It also incorporates a switched-capacitor array for frequency tuning and hence digital deskew in ILC. A 4 GHz test chip was designed and fabricated in a 0.18 mum standard digital CMOS. It consists of four ILOs driven by a balanced H-tree. Each ILO consumes less than 1 mW from a 1 V power supply. 5-bit digital deskew achieves 55 ps delay tuning range and 1.8 ps resolution. Measurement shows that only 30 fs cycle-to-cycle jitter degradation was introduced and no phase noise degradation at frequency offset up to 600 kHz.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121554048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405840
V. Jain, S. Sundararaman, P. Heydari
The design of a CMOS 22-29 GHz pulse-radar receiver (RX) front-end for ultra-wideband (UWB) automotive radar sensors is presented. Fabricated in a 0.18 mum CMOS process, the 3 mm2 RX chip achieves a conversion gain of 35-38.1 dB, noise figure of 5.5-7.4 dB and input return loss less than -14.5 dB in the 22-29 GHz band. The phase noise of the constituent QVCO is -107 dBc/Hz at 1 MHz offset from a center frequency of 26.5 GHz. The total dc power dissipation of the RX including LO/output buffers is 131 mW.
{"title":"A CMOS 22-29GHz Receiver Front-End for UWB Automotive Pulse-Radars","authors":"V. Jain, S. Sundararaman, P. Heydari","doi":"10.1109/CICC.2007.4405840","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405840","url":null,"abstract":"The design of a CMOS 22-29 GHz pulse-radar receiver (RX) front-end for ultra-wideband (UWB) automotive radar sensors is presented. Fabricated in a 0.18 mum CMOS process, the 3 mm2 RX chip achieves a conversion gain of 35-38.1 dB, noise figure of 5.5-7.4 dB and input return loss less than -14.5 dB in the 22-29 GHz band. The phase noise of the constituent QVCO is -107 dBc/Hz at 1 MHz offset from a center frequency of 26.5 GHz. The total dc power dissipation of the RX including LO/output buffers is 131 mW.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126458825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405755
Jun-Hyun Bae, Jin-Ho Seo, H. Yeo, Jae-Whui Kim, J. Sim, Hong-June Park
An all-digital 90deg phase-shift DLL is proposed for 1.6 Gbps DDR interface by using a loop-embedded DCC and a binary phase detector with the lock range extended to 0~4pi radians. The DCC has a small delay and the fixed rising-edge property for loop-embedding. The chip fabricated with a 0.13 um CMOS process gives the DLL data rate of 667 Mbps~1.6 Gbps and the output duty cycle of 47.8%~49% for the input duty cycle of 23%~76%, at 1.6 Gbps and 1.2 V.
采用环嵌式DCC和二进制鉴相器，提出了一种适用于1.6 Gbps DDR接口的全数字90度相移DLL，锁相范围扩展到0~4pi弧度。DCC具有较小的时延和固定的上升沿特性，适合于环嵌入。该芯片采用0.13 um CMOS工艺制作，在1.6 Gbps和1.2 V电压下，DLL数据速率为667mbps ~1.6 Gbps，输出占空比为47.8%~49%，输入占空比为23%~76%。
{"title":"An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface","authors":"Jun-Hyun Bae, Jin-Ho Seo, H. Yeo, Jae-Whui Kim, J. Sim, Hong-June Park","doi":"10.1109/CICC.2007.4405755","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405755","url":null,"abstract":"An all-digital 90deg phase-shift DLL is proposed for 1.6 Gbps DDR interface by using a loop-embedded DCC and a binary phase detector with the lock range extended to 0~4pi radians. The DCC has a small delay and the fixed rising-edge property for loop-embedding. The chip fabricated with a 0.13 um CMOS process gives the DLL data rate of 667 Mbps~1.6 Gbps and the output duty cycle of 47.8%~49% for the input duty cycle of 23%~76%, at 1.6 Gbps and 1.2 V.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126107371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405864
I. Syllaios, P. Balsara, R. Staszewski
A new all-digital phase-locked loop (ADPLL) for RF wireless applications has recently been proposed and commercially demonstrated. It replaces conventional phase/frequency detector and charge pump with a time-to-digital converter (TDC). Analog frequency tuning of a VCO is replaced with an all-digital tuning of a digitally-controlled oscillator (DCO). In this paper, we present novel time-domain modeling and simulation techniques of the ADPLL phase detection mechanism as well as the frequency perturbation and phase noise characteristics of the DCO. The modeling principles are demonstrated for a GSM standard and validated through experimental results.
{"title":"Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications","authors":"I. Syllaios, P. Balsara, R. Staszewski","doi":"10.1109/CICC.2007.4405864","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405864","url":null,"abstract":"A new all-digital phase-locked loop (ADPLL) for RF wireless applications has recently been proposed and commercially demonstrated. It replaces conventional phase/frequency detector and charge pump with a time-to-digital converter (TDC). Analog frequency tuning of a VCO is replaced with an all-digital tuning of a digitally-controlled oscillator (DCO). In this paper, we present novel time-domain modeling and simulation techniques of the ADPLL phase detection mechanism as well as the frequency perturbation and phase noise characteristics of the DCO. The modeling principles are demonstrated for a GSM standard and validated through experimental results.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116259587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405787
D. Manstretta, Leonard Dauphinee
A broadband variable-gain low noise amplifier with triple output for TV tuners has been demonstrated in a 0.18 mum SiGe technology. The gain varies continuously from 27 dB to -28 dB and has better than 1 dB precision over a 1GHz bandwidth. At 27 dB gain the amplifier shows 6.5 dB NF, 82 dBmV OIP3 and 121 dBmV OIP2. OIP3 is above 73 dBmV down to -21 dB gain. With all three outputs enabled the circuit draws 170 mA from a 3.3V supply.
{"title":"A Highly Linear Broadband Variable Gain LNA for TV Applications","authors":"D. Manstretta, Leonard Dauphinee","doi":"10.1109/CICC.2007.4405787","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405787","url":null,"abstract":"A broadband variable-gain low noise amplifier with triple output for TV tuners has been demonstrated in a 0.18 mum SiGe technology. The gain varies continuously from 27 dB to -28 dB and has better than 1 dB precision over a 1GHz bandwidth. At 27 dB gain the amplifier shows 6.5 dB NF, 82 dBmV OIP3 and 121 dBmV OIP2. OIP3 is above 73 dBmV down to -21 dB gain. With all three outputs enabled the circuit draws 170 mA from a 3.3V supply.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121696369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405777
B. Casper, G. Balamurugan, J. Jaussi, J. Kennedy, M. Mansuri
High-aggregate bandwidth interfaces with minimized power, silicon area, cost and complexity will be essential to the viability of future microprocessor systems. Optimization of microprocessor interfaces at the system level is crucial to providing the most cost-effective and efficient solution. This paper details a comprehensive interconnect and system level analysis method that can be used to accurately evaluate platform-level tradeoffs and has been correlated to link measurements with 10% accuracy. System tradeoffs with respect to interconnect quality, equalization, modulation, clock architecture are shown. Interconnect and circuit density improvements are identified as a promising research direction to maximize the bandwidth and power efficiency of future microprocessor platforms.
{"title":"Future Microprocessor Interfaces: Analysis, Design and Optimization","authors":"B. Casper, G. Balamurugan, J. Jaussi, J. Kennedy, M. Mansuri","doi":"10.1109/CICC.2007.4405777","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405777","url":null,"abstract":"High-aggregate bandwidth interfaces with minimized power, silicon area, cost and complexity will be essential to the viability of future microprocessor systems. Optimization of microprocessor interfaces at the system level is crucial to providing the most cost-effective and efficient solution. This paper details a comprehensive interconnect and system level analysis method that can be used to accurately evaluate platform-level tradeoffs and has been correlated to link measurements with 10% accuracy. System tradeoffs with respect to interconnect quality, equalization, modulation, clock architecture are shown. Interconnect and circuit density improvements are identified as a promising research direction to maximize the bandwidth and power efficiency of future microprocessor platforms.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"95 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122703083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405736
Wei-Zen Chen, Shih-Hao Huang
This paper presents the design of a monolithically integrated CMOS optical receiver, including a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. A novel PIN detector is proposed and adopted in this design without technology modification. The optical receiver is capable of delivering 420 mVpp to 50 Omega output load and operating up to 2.5 Gbps without an equalizer. Implemented in a generic 0.18 mum CMOS technology, the total power dissipation is 138 mW. The chip size is 0.53 mm2.
本文介绍了一种单片集成CMOS光接收器的设计，包括光检测器、跨阻放大器和限流放大器。提出了一种新的PIN检测器，并在不修改技术的情况下采用。光接收器能够在50 Omega输出负载下提供420 mVpp，在没有均衡器的情况下运行高达2.5 Gbps。采用通用的0.18 μ m CMOS技术，总功耗为138mw。芯片尺寸为0.53 mm2。
{"title":"A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN Detector","authors":"Wei-Zen Chen, Shih-Hao Huang","doi":"10.1109/CICC.2007.4405736","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405736","url":null,"abstract":"This paper presents the design of a monolithically integrated CMOS optical receiver, including a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. A novel PIN detector is proposed and adopted in this design without technology modification. The optical receiver is capable of delivering 420 mVpp to 50 Omega output load and operating up to 2.5 Gbps without an equalizer. Implemented in a generic 0.18 mum CMOS technology, the total power dissipation is 138 mW. The chip size is 0.53 mm2.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127693938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405698
S. Sunter, A. Roy
After briefly reviewing conventional jitter and jitter tolerance tests for SerDes, this paper shows that ISI is a dominant source of bit errors above 4 Gbps, and is inadequately tested. We demonstrate the correlation between ISI and transition-density dependent delay (TDDD) at 3.1 Gbps, and provide detailed 6.25 Gbps silicon results for an undersampling digital BIST that can measure jitter, TDDD, and other parameters at production speeds with picosecond resolution.
{"title":"Testing SerDes beyond 4 Gbps - changing priorities","authors":"S. Sunter, A. Roy","doi":"10.1109/CICC.2007.4405698","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405698","url":null,"abstract":"After briefly reviewing conventional jitter and jitter tolerance tests for SerDes, this paper shows that ISI is a dominant source of bit errors above 4 Gbps, and is inadequately tested. We demonstrate the correlation between ISI and transition-density dependent delay (TDDD) at 3.1 Gbps, and provide detailed 6.25 Gbps silicon results for an undersampling digital BIST that can measure jitter, TDDD, and other parameters at production speeds with picosecond resolution.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133532055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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