Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405760
R. Barnett, Jin Liu
This paper presents an EEPROM programming controller imbedded in a passive UHF RFID transponder. It generates a 14 V programming voltage for a 224-bit EEPROM memory array from a rectified voltage supply of 2-3 V. A gated clock regulation loop is proposed to keep the programming voltage constant over a wide range of received RF input power, in order to improve the write-erase endurance of the memory. A current surge control scheme is proposed to allow the EEPROM programming voltage ramping in steps, therefore, preventing the collapse of the rectified supply in the remotely powered transponder. Also presented is a nano-power switched bandgap reference to reduce die area through the reduction of Meg-ohm resistors needed for nano-power operation. Measurement results show that a 0.35 mum CMOS transponder IC provides a stable 14 V EEPROM programming voltage and consumes only 7 muW during write operation. The EEPROM programming controller occupies 0.092 mm2 die area.
提出了一种嵌入在无源超高频RFID应答器中的EEPROM编程控制器。它从2-3 V的整流电压电源为224位EEPROM存储器阵列产生14 V的编程电压。为了提高存储器的写擦持久性，提出了一种门控时钟调节回路，使编程电压在较大的射频输入功率范围内保持恒定。提出了一种电流浪涌控制方案，允许EEPROM编程电压逐步上升，从而防止远程供电应答器中的整流电源崩溃。本文还提出了一种纳米功率开关带隙参考，通过减少纳米功率工作所需的欧姆电阻来减少芯片面积。测量结果表明，0.35 μ m CMOS应答器IC可提供稳定的14 V EEPROM编程电压，写入时功耗仅为7 μ w。EEPROM编程控制器的芯片面积为0.092 mm2。
{"title":"An EEPROM Programming Controller for Passive UHF RFID Transponders with Gated Clock Regulation Loop and Current Surge Control","authors":"R. Barnett, Jin Liu","doi":"10.1109/CICC.2007.4405760","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405760","url":null,"abstract":"This paper presents an EEPROM programming controller imbedded in a passive UHF RFID transponder. It generates a 14 V programming voltage for a 224-bit EEPROM memory array from a rectified voltage supply of 2-3 V. A gated clock regulation loop is proposed to keep the programming voltage constant over a wide range of received RF input power, in order to improve the write-erase endurance of the memory. A current surge control scheme is proposed to allow the EEPROM programming voltage ramping in steps, therefore, preventing the collapse of the rectified supply in the remotely powered transponder. Also presented is a nano-power switched bandgap reference to reduce die area through the reduction of Meg-ohm resistors needed for nano-power operation. Measurement results show that a 0.35 mum CMOS transponder IC provides a stable 14 V EEPROM programming voltage and consumes only 7 muW during write operation. The EEPROM programming controller occupies 0.092 mm2 die area.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127660337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405687
Subodh Gupta, J. Anderson, L. Farragher, Qiang Wang
We consider dynamic power dissipation in FPGAs and present CAD techniques for dynamic power reduction. The proposed techniques, comprising power-aware placement, routing, and a novel post-routing transformation, are applied to optimize the power consumed by industrial designs implemented in the Xilinxreg Virtextrade-5 FPGA. Board-level power measurements on a suite of industrial designs show that the techniques reduce power by 10%, on average.
{"title":"CAD Techniques for Power Optimization in Virtex-5 FPGAs","authors":"Subodh Gupta, J. Anderson, L. Farragher, Qiang Wang","doi":"10.1109/CICC.2007.4405687","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405687","url":null,"abstract":"We consider dynamic power dissipation in FPGAs and present CAD techniques for dynamic power reduction. The proposed techniques, comprising power-aware placement, routing, and a novel post-routing transformation, are applied to optimize the power consumed by industrial designs implemented in the Xilinxreg Virtextrade-5 FPGA. Board-level power measurements on a suite of industrial designs show that the techniques reduce power by 10%, on average.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124372066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405670
R. Canegallo, A. Fazzi, L. Ciccarelli, L. Magagni, F. Natali, P. Rolandi, E. Jung, L. Cioccio, R. Guerrieri
A 3D interconnection scheme based on capacitive coupling for high speed chip to chip communication has been implemented in a 0.13 mum CMOS process. This paper provides detailed design example for both synchronous and asynchronous transmitter and receiver circuits. The first approach shows with electrodes 15 times 15 mum2 a wide range of operating frequency up to 900 MHz with an energy consumption of 41fJ/bit. In the asynchronous scheme we demonstrate with electrodes 8 times 8 mum2 a vertical propagation of clock at 1.7 GHz and a propagation delay of 420 ps for general purpose signal with energy consumption of 80 f J/bit. Functionality and performance have been demonstrated by using both die-level and wafer-level assembly flows and BER measurements show the reliability of these AC interconnections with no error on more than 1013 bits transmitted.
在0.13 μ m CMOS工艺下，实现了一种基于电容耦合的高速片间通信三维互连方案。本文给出了同步和异步发送和接收电路的详细设计实例。第一种方法显示，使用15倍15 mum2的电极，工作频率范围可达900 MHz，能耗为41fJ/bit。在异步方案中，我们用8 × 8 mum2电极演示了时钟在1.7 GHz的垂直传播，传输延迟为420 ps，用于通用信号，能耗为80 f J/bit。通过使用芯片级和晶圆级组装流程证明了功能和性能，并且误码率测量显示了这些交流互连的可靠性，在传输超过1013位的情况下没有错误。
{"title":"3D Capacitive Interconnections for High Speed Interchip Communication","authors":"R. Canegallo, A. Fazzi, L. Ciccarelli, L. Magagni, F. Natali, P. Rolandi, E. Jung, L. Cioccio, R. Guerrieri","doi":"10.1109/CICC.2007.4405670","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405670","url":null,"abstract":"A 3D interconnection scheme based on capacitive coupling for high speed chip to chip communication has been implemented in a 0.13 mum CMOS process. This paper provides detailed design example for both synchronous and asynchronous transmitter and receiver circuits. The first approach shows with electrodes 15 times 15 mum2 a wide range of operating frequency up to 900 MHz with an energy consumption of 41fJ/bit. In the asynchronous scheme we demonstrate with electrodes 8 times 8 mum2 a vertical propagation of clock at 1.7 GHz and a propagation delay of 420 ps for general purpose signal with energy consumption of 80 f J/bit. Functionality and performance have been demonstrated by using both die-level and wafer-level assembly flows and BER measurements show the reliability of these AC interconnections with no error on more than 1013 bits transmitted.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122839954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405805
J. Zou, H. Graeb, D. Mueller, Ulf Schlichtmann
This paper presents an optimization method for switched-capacitor σ-δ modulators. The SNR performance is maximized while considering the performance capability of the critical building block, i.e. the Op Amp. Performance space exploration is applied to find the feasible region of the building block's performance, which is represented by a Pareto-optimal front. Through worst-case analysis on design points of the nominal Pareto front, a worst-case-aware Pareto-optimal front can be computed. The maximized SNR and the corresponding yield will be presented. The proposed optimization process is efficient and can be accomplished in some hours.
{"title":"Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts","authors":"J. Zou, H. Graeb, D. Mueller, Ulf Schlichtmann","doi":"10.1109/CICC.2007.4405805","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405805","url":null,"abstract":"This paper presents an optimization method for switched-capacitor σ-δ modulators. The SNR performance is maximized while considering the performance capability of the critical building block, i.e. the Op Amp. Performance space exploration is applied to find the feasible region of the building block's performance, which is represented by a Pareto-optimal front. Through worst-case analysis on design points of the nominal Pareto front, a worst-case-aware Pareto-optimal front can be computed. The maximized SNR and the corresponding yield will be presented. The proposed optimization process is efficient and can be accomplished in some hours.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124232526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405855
P. Levine, P. Gong, K. Shepard, R. Levicky
We describe the design of a 4times4 active sensor array for multiplexed electrochemical biomolecular detection in a 0.25-mum-CMOS process. Integrated potentiostats sense the current flowing through the on-chip Au electrodes that result from reactions occurring at the chip surface. Preliminary experimental results include cyclic voltammetry of several redox species and application to DNA probe coverage characterization.
我们设计了一种用于0.25 μ m cmos工艺中多路电化学生物分子检测的4times4有源传感器阵列。集成的电位器能感应到芯片表面发生的反应所产生的流过片上金电极的电流。初步实验结果包括几种氧化还原物质的循环伏安法和应用于DNA探针覆盖表征。
{"title":"Active CMOS Array for Electrochemical Sensing of Biomolecules","authors":"P. Levine, P. Gong, K. Shepard, R. Levicky","doi":"10.1109/CICC.2007.4405855","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405855","url":null,"abstract":"We describe the design of a 4times4 active sensor array for multiplexed electrochemical biomolecular detection in a 0.25-mum-CMOS process. Integrated potentiostats sense the current flowing through the on-chip Au electrodes that result from reactions occurring at the chip surface. Preliminary experimental results include cyclic voltammetry of several redox species and application to DNA probe coverage characterization.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117146294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405728
Akihiro Nakamura, Masahide Kawaharazaki, M. Yoshikawa, T. Fujino
In this paper, we propose the novel architecture of VCLD (via configurable logic device) called VPEX (via programmable logic using exclusive-OR array) which is optimized for electron beam (EB) direct writing. The logic element (LE) of VPEX consists of complex gate type exclusive OR (EXOR) and inverter (NOT) gates. The single LE can output 12 logics which include all 2-inputs logic functions (NAND, NOR AND, OR bubble AND, bubble OR XOR XNOR), 3 inputs AOI21 and inverted-output multiplexer (MUXI) by changing via-1 layout. Scan D-FlipFlop can be composed by using 5 LEs. The logic of each LE can be defined by double EB exposure using "character beam". The speed performance of VPEX is much better than that of FPGAs, and 1.5 times worse than that of ASICs. We believe that the combination of VPEX architecture and EB direct writing is the best solution for low-volume production LSIs.
本文提出了一种新的VCLD(通过可配置逻辑器件)架构，称为VPEX(通过使用异或阵列的可编程逻辑)，该架构针对电子束(EB)直接写入进行了优化。VPEX的逻辑元件(LE)由复杂门型异或门(EXOR)和反相门(NOT)组成。单个LE可以输出12个逻辑，包括所有2输入逻辑功能(NAND, NOR AND, OR泡AND，泡OR XOR XNOR)， 3输入AOI21和通过改变via-1布局的反输出多路复用器(MUXI)。Scan D-FlipFlop可以由5个LEs组成。每个LE的逻辑可以通过使用“特征光束”的双EB曝光来定义。VPEX的速度性能比fpga好很多，比asic差1.5倍。我们相信VPEX架构和EB直写的结合是小批量生产lsi的最佳解决方案。
{"title":"Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing","authors":"Akihiro Nakamura, Masahide Kawaharazaki, M. Yoshikawa, T. Fujino","doi":"10.1109/CICC.2007.4405728","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405728","url":null,"abstract":"In this paper, we propose the novel architecture of VCLD (via configurable logic device) called VPEX (via programmable logic using exclusive-OR array) which is optimized for electron beam (EB) direct writing. The logic element (LE) of VPEX consists of complex gate type exclusive OR (EXOR) and inverter (NOT) gates. The single LE can output 12 logics which include all 2-inputs logic functions (NAND, NOR AND, OR bubble AND, bubble OR XOR XNOR), 3 inputs AOI21 and inverted-output multiplexer (MUXI) by changing via-1 layout. Scan D-FlipFlop can be composed by using 5 LEs. The logic of each LE can be defined by double EB exposure using \"character beam\". The speed performance of VPEX is much better than that of FPGAs, and 1.5 times worse than that of ASICs. We believe that the combination of VPEX architecture and EB direct writing is the best solution for low-volume production LSIs.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115710397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405830
O. Takahashi, E. Behnen, S. Cottier, P. Coulman, S. Dhong, B. Flachs, H. P. Hofstee, C. J. Johnson, S. Posluszny
The cell BE design methodology is described which enables high frequency, high performance, power efficient, and area optimized design. It includes a hierarchical design style, clean clock boundary, effective use of non-scan latches, at-speed scan testing, custom design like synthesized macro, fine grained clock gating scheme, and cycle accurate power analysis.
{"title":"Cell Broadband Engine Processor Design Methodology","authors":"O. Takahashi, E. Behnen, S. Cottier, P. Coulman, S. Dhong, B. Flachs, H. P. Hofstee, C. J. Johnson, S. Posluszny","doi":"10.1109/CICC.2007.4405830","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405830","url":null,"abstract":"The cell BE design methodology is described which enables high frequency, high performance, power efficient, and area optimized design. It includes a hierarchical design style, clean clock boundary, effective use of non-scan latches, at-speed scan testing, custom design like synthesized macro, fine grained clock gating scheme, and cycle accurate power analysis.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115745912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405776
S. Voinigescu, R. Aroca, T. Dickson, S. Nicolson, T. Chalvatzis, P. Chevalier, P. Garcia, C. Gamier, B. Sautreuil
This paper describes first a half-rate, 2.5-V, 1.4-W, 87-Gb/s transmitter with on-chip PLL fabricated in a production 130-nm SiGe BiCMOS process. Next, the most critical blocks required for the implementation of a full-rate 100-Gb/s serial transceiver are explored. State-of-the art 105-GHz, SiGe HBT static frequency dividers and VCOs operating from 2.5-V supply, as well as 65-nm CMOS, 1.2-V, 90-GHz static frequency dividers, low-phase noise VCOs, and 100-GHz clock distribution network amplifiers are fully characterized over power supply and process spread, and over temperature up to 100degC. Inductor and transformer modeling and scaling beyond 200 GHz in nanoscale CMOS and SiGe BiCMOS technologies, are also described.
{"title":"Towards a sub-2.5V, 100-Gb/s Serial Transceiver","authors":"S. Voinigescu, R. Aroca, T. Dickson, S. Nicolson, T. Chalvatzis, P. Chevalier, P. Garcia, C. Gamier, B. Sautreuil","doi":"10.1109/CICC.2007.4405776","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405776","url":null,"abstract":"This paper describes first a half-rate, 2.5-V, 1.4-W, 87-Gb/s transmitter with on-chip PLL fabricated in a production 130-nm SiGe BiCMOS process. Next, the most critical blocks required for the implementation of a full-rate 100-Gb/s serial transceiver are explored. State-of-the art 105-GHz, SiGe HBT static frequency dividers and VCOs operating from 2.5-V supply, as well as 65-nm CMOS, 1.2-V, 90-GHz static frequency dividers, low-phase noise VCOs, and 100-GHz clock distribution network amplifiers are fully characterized over power supply and process spread, and over temperature up to 100degC. Inductor and transformer modeling and scaling beyond 200 GHz in nanoscale CMOS and SiGe BiCMOS technologies, are also described.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130806596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405826
K. Lakshmikumar, Vinod Mukundagiri, S. Gierkink
Local positive feedback in a delay element enables a ring oscillator with only two stages to oscillate and produce quadrature clocks. Routh-Hurwitz's criterion is applied to prove that such a structure can oscillate. An internally generated power supply from a constant-gm bias keeps the free running frequency to within plusmn 5% from -40 to 125degC over process variations. The 1.25 GHz oscillator in 0.13 mum CMOS draws 3.4 mA and has a phase noise of -88 dBc/Hz at 1MHz offset.
延迟元件中的本地正反馈使只有两个阶段的环形振荡器振荡并产生正交时钟。劳斯-赫维茨准则被用来证明这种结构可以振荡。内部产生的电源从恒定的偏置保持自由运行频率在±5%，从-40到125°c的过程变化。0.13 μ m CMOS的1.25 GHz振荡器消耗3.4 mA，在1MHz偏移时相位噪声为-88 dBc/Hz。
{"title":"A Process and Temperature Compensated Two-Stage Ring Oscillator","authors":"K. Lakshmikumar, Vinod Mukundagiri, S. Gierkink","doi":"10.1109/CICC.2007.4405826","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405826","url":null,"abstract":"Local positive feedback in a delay element enables a ring oscillator with only two stages to oscillate and produce quadrature clocks. Routh-Hurwitz's criterion is applied to prove that such a structure can oscillate. An internally generated power supply from a constant-gm bias keeps the free running frequency to within plusmn 5% from -40 to 125degC over process variations. The 1.25 GHz oscillator in 0.13 mum CMOS draws 3.4 mA and has a phase noise of -88 dBc/Hz at 1MHz offset.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131304315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/CICC.2007.4405764
G. Shahidi
Over the last 15 years, there has been a new CMOS technology node approximately every two years. The key feature of every node has been 2X density shrink and ~35% performance gain per technology node. Chip power has been increasing rapidly, approaching air cool limit. Power limit is transforming CMOS scaling to more of a density driver. As we move to 32 nm node and beyond a number of additional fundamental challenges are faced, which may force additional rethinking of how scaling has been done. This paper is an overview of some upcoming challenges and possible ways of addressing them.
{"title":"Evolution of CMOS Technology at 32 nm and Beyond","authors":"G. Shahidi","doi":"10.1109/CICC.2007.4405764","DOIUrl":"https://doi.org/10.1109/CICC.2007.4405764","url":null,"abstract":"Over the last 15 years, there has been a new CMOS technology node approximately every two years. The key feature of every node has been 2X density shrink and ~35% performance gain per technology node. Chip power has been increasing rapidly, approaching air cool limit. Power limit is transforming CMOS scaling to more of a density driver. As we move to 32 nm node and beyond a number of additional fundamental challenges are faced, which may force additional rethinking of how scaling has been done. This paper is an overview of some upcoming challenges and possible ways of addressing them.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126390229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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